Heterogeneous Integration RoadmapThermal Technical Working Group (TWG)

Presented by Madhu Iyengar (Google), Azmat Malik (Accuventures), Avram Bar-Cohen (Raytheon)for Thermal TWG

HIR Workshop at ECTCMay 27 2019, Las Vegas

1

HIR Thermal TWG - Work Status

2

• Year 1 (2018-2019)• Thermal effort kicked off in March 2019.• ~30 industry and university expert contributors.• Chapter Draft completed in Feb 2019.• Peer Review completed in May 2019.• Final revisions TBD

• Year 2 (2019-2020)• Target work areas currently being brainstormed.• New members expected in Automotive, Memory, and Mobile areas.

Avi Bar-Cohen, RaytheonAli Merrikh, QualcommAmr Helmy, University of TorontoAzmat Malik, AcuventuresBahgat G. Sammakia, Binghamton UniversityBaratunde Cola, Georgia TechBaris Dogruoz, CiscoBenson Chan, Binghamton UniversityBill Bottoms, IEEECraig Green, CarbiceDenise Manning, IEEEDhruv Singh, Global FoundriesGamal Refai-Ahmed, XilinxJamal Yagoobi, Worcester PolytechnicJustin A. Weibel, Purdue UniversityKamal Sikka, IBMKanad Ghose, Binghamton UniversityKenneth Goodson, Stanford University

HIR Thermal TWG Contributors

3

Kevin P. Drummond, Purdue UniversityLi Shi, University of Texas, AustinMadhusudan Iyengar, GoogleMehdi Ashegh, Stanford UniversityMichael J. Ellsworth, IBMPeter de Bock, General electricRavi Mahajan, IntelRockwell Hsu, CiscoSatish Kumar, georgia TechSreekant.Narumanchi, NRELSuresh V. Garimella, Purdue UniversityTimothy Chainer, IBMVadim Gektin, HuaweiVictor Chiriac, QualcommYoonjin Won, University of California, IrvineYogi Joshi, Georgia TechWeihua Tang, IntelWilliam Chen, Asesus

Scope for HIR Thermal TWG

Thermal TWG will consider three areas:(a) Die level.(b) Package integration/SIP/module Level.(c) System Level (limited to board level).

Thermal TWG will focus on articulating the following in quantitative and qualitative terms:

(i) Trends for cooling requirements.(ii) Known technical solutions.(iii) Advanced concepts and research.

4

1. 2D chip with stacked memory on a silicon/glass interposer

2. 3D stacked die with conduction interfaces

3. 3D stacked die with embedded liquid cooling

4. Optics/photonics based Heterogeneous package

5. Harsh environment (military, aerospace, automobile)

6. Mobile application chipset (package on package, fan out, bridge)

7. Voltage Regulators in a Heterogenous Package

Canonical Thermal HI Problems

5

1.2D Enhanced Architecture - Thermal ChallengesWeihua Tang (Intel), Vadim Gektin (Huawei), Yogi Joshi (Georgia Tech)

● Increasing package power density;● Increasing total package power dissipation;● Thermal cross-talk, including the need for thermal isolation;● Different thermal (Tj) requirements and sensitivities.● TIM1 or TIM1.5 thermal insulance (K-mm2/W) uncertainty from increasing

form factor and Si surface flatness and overall warpage impact● Thermo-mechanical enabling● Interposer thermal properties (glass/Si/organic) (see Figure 3) including

anisotropy.● Interposer thermal conductivity has a strong impact on chip thermal

resistance● Glass and Si interposer performance can be made comparable, by

appropriate enhancements● Interposer heat spreading and heat removal 6

1. (cont.) 2D Chip Package Thermal ChallengesWeihua Tang (Intel), Vadim Gektin (Huawei), Yogi Joshi (Georgia Tech)

7Impact of interposer and substrate thermal conductivity on

package thermal resistance

2. 3D Chip Stack Cooling - Conduction InterfacesKamal Sikka (IBM), Vadim Gektin (Huawei)

8

3. 3D Chip Stack Cooling - Embedded CoolingTim Chainer(IBM), Yogi Joshi (Georgia Tech), Vadim Gektin (Huawei)

9Avram Bar-Cohen, DARPA ICECool Apps Phase 1 TDV Results

4. Thermal challenges in Photonic devicesAmr helmy (Univ. Toronto), Weihua Tang (Intel)

10

5. Heterogeneous Integration for Harsh EnvironmentsPeter de Bock (GE), Sreekant Narumanchi (NREL), Craig Green (Carbice)

11

Notional 3D chip architecture and anticipated topology challenges

Inverter in a multi-layered board or stack-up configuration

6. Thermal challenges in Mobile platformsNelson and Galloway (2018)

12

Micro heat pipe in a modern smartphone

Temperature contour data for the external surface of a SmartPhone

7. Thermal challenges in Voltage RegulatorsKanad Ghose (SUNY Binghamton)

13

even at 95% efficiency, a 200W VR (Voltage Regulator) will dissipate 10 Watts – mostly within the power switching devices with a small footprint inside the package.

14

Advanced technologies & research innovations

1. Thermal Interface Materials

2. System thermal limits for HPC multi-chip modules

3. Embedded liquid cooling of chip and chip stacks

4. Advanced Thermal Materials for Thermal Management

5. Thermomechanical Modeling for Heterogeneous Integration

15

Thermal Interface Materials Yoonjin Won, University of California, Irvine

Two common strategies can be employed to create high-performance TIM composites

SEM image of a porous ultrathin graphite foam structure

16

System thermal limits for HPC multi-chip modulesBahgat Sammakia (Binghamton Univ), Mike Ellsworth (IBM)

Within these practical limitations and

assuming a uniform heat flux at the devices

the maximum possible device heat flux is

estimated to be about 84 W/cm2 [20]. Higher

heat flux levels may be possible through

refinements of the heat sink and/or vapor

chamber design and the TIM thermal

resistance, or through the opening up of the

practical limitations such as the allowable

heat sink volume or air flow.

17

Embedded liquid cooling - Manifolded MicrochannelsSuresh Garimella, Justin Weibel, Kevin Drummond, Purdue University CTRC

Two-Phase HFE 7100

18

Embedded liquid cooling - On Silicon Micro-coolerKen Goodson, Mehdi Asheghi, Stanford University

The expected performance targets for

EHFµ-Cooler, and that of the state-of-the-

art devices including Stanford’s previous

work. Critical heat flux levels are from 200

to 1000 W/cm2. The EHFµ-Cooler

represents more than 10× reduction in

thermal resistance, an unprecedented CHF

>1 kW/cm2 for water as working fluid, and

can be scaled up to large areas >10cm2.

19

Embedded liquid cooling - Radial intrachip coolerTim Chainer, Pritish Parida, Mark Schultz, IBM Research, NY

Two-Phase R1234ez

20

Advanced Thermal MaterialsLi Shi, University of Texas, Austin

Examples of advanced materials include cubic crystals,

two-dimensional layered materials, nanostructure networks

and composites, molecular layers and surface

functionalization, and aligned polymer structures.

21

Thermal modeling methodology for HI packagesSatish Kumar (Georgia tech), Dhruv Singh (Global Foundries)

Definition of the design space and execution of FEM simulations with combinatorial and probabilistic input

parameters spanning geometrical descriptions, material properties and interface/boundary conditions

across domains.

2) Training Data: Output FEM state distributions and fields (electric field, power density, temperature,

stress, strain etc.). Training and validation using an artificial neural network with feed forward deep

autoencoders (DAE).

3) Deployment of the validated DAEs generated in (2) to accurately predict the non-linear and statistical

behavior of a design with minimum computational and setup overhead.