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Heterogeneous SoCs Through Advanced Packaging

SubramanianS.Iyer

(s.s.iyer@ucla.edu)

chips.ucla.edu

OurMainThrust:Whatarewetryingtodo?

Developan“app-like”environmentforHardwarethatcan

•  CuttheNmetomarketby5-10X

•  CuttheNREcostby10-20X

•  Allowextremeheterogeneityincludingextensionstocyber-

physicalsystems

•  DevelopasophisNcatedmanufacturingworkforce

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1964-TransistorSLTmodule

6transistors,4resistors

201422nmCMOSTech.ThePowerofSystemonaChip(SoC)

2016-7–IBMPOWER9Processorfabbed@GlobalFoundries

14nmSOIeDRAMtechnology,650mm2

24coresand120MBofon-chipeDRAMmemory

8billiontransistors,17wiringlevels!!

Transistorscalinghasmadethispossible

ButasSoCshavego_enmorecomplex

•  NREcostshaveskyrocketed

•  Timetomarkethasbecomehuge

•  Manufacturingcostshavegrown

•  andyieldshaveplummeted

CourtesyIBM

CompuNngisbecomingheterogeneous

Manycore

Mobilesensors

+processorsCogniNve

storage

Persistent

slower

Hierar

chica

ltoDa

taCentr

ic

Andh

eterog

eneous

Itsnolongerfeasibletoputallthisononedie

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Althoughwedidtry

•  WithoutquesNonthesmallestboardisasinglelargediewith

allthesystemfuncNonsonit

•  HencethequestforthelargestYieldableUnit–theSoC(reNclesizetodaywillyieldat3-15%)

GeneAhmdahl@TrilogySystems

Amdahleventuallydeclaredtheideawould

onlyworkwitha99.99%yield,whichwouldn't

happenfor100years.

It’stheinterconnectdensity–Stupid!

Youcan’tscaleyourself

outofthepowergap

Youneedadifferentarchitecturedrivenbyand

abilitytointerconnectmoreeffecicently

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WhatwouldYogiSay?

1925-2015

10

100

1000

10000

1971

1975

1982

1985

1989

1994

1997

2002

2004

2006

2008

2010

2012

2015

Node

dimen

sion(

nm)

Year

Siliconfeatures1000X

Packagingfeatures

~4X

Package/BoardFeatureshavescaledmodestly

•  WepackedmorefuncNonondie–SoCera

•  SerializaNon–deserializaNontechniquesallowedhighdataratesoverfewerchannels

•  Boardsarelarge•  “Serdes”area(>25%)andpower(>25%)gepngoutofhand

Board channel

Serialzer deseria

lizer

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DoweneedPackages?ShortAnswerNo!*

Epoxy/glassBoardCTE=16-20x10-6/oC

Packagesaresupposedto:

•  Protectthechip–mechanicallyandthermally–sowhydowehaveCPIissuesandheatsinks

•  Connectthechipelectricallytootherchips–really?Sowhydowehavetofan-out?•  AllowsmissionmodetesNngofthechip-Ok–Ithinkthisoneisreal!

*Idorealizethatthisisadangerousthingtosay

atapackagingconference

Evolution Of System Integration

Sys

tem

Per

form

ance

Integration

Stacked Die

Module on Interposer

“Prehistoric”

Now

Future

Interposers/Boards Organic –> Si-> glass

Stacked memory Wafer stacking

Massively integrated Silicon-like Board

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MegaSoIFs*byre-integraNononanInterconnectFabric

*SystemonInterconnectFabric

CHIPSInterconnect:Finepitchandsmallspacings

q VerywideparallelinterconnectØ  RouNngpitchsimilartoCMOStop-level

rouNng

Ø  Bump/padpitchasfineas2μmpossible

q SERDEScanbeavoidedexceptforverylonglinks

Ø  Eventhen,complexityexpectedtobelower

thantradiNonalSERDES

q Primarybenefit:<0.2pJ/bpossibleeven

atmulNTB/saggregatedatarates

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Dieletsizeandinterconnectpitch-CaseStudy-BlueGene®Q

•  Mostdieletsaresmall(<3mmX3mm)

•  LargeDieletsaredominatedbyinterconnectcongesNon–

canbemiNgatedbyextrawiringlevels

•  Interconnectpitchof5µmwouldbewouldsuffice

IncreasinginterconnectPitch

Dielet/ChipletSize

#ofCKTs

IPResuse

I/Ocomplexity

I/Opower

TesNngComplexity

500µm

BGA/LGA

ContactedGatepitch

~50nm

OpNmalpitch

CHIPS–like

regime

2-10µm

PackaginglikeSoClike

Mechanical

constraints

Electrical/logical

constraints

Diehandling

constraint

Dieyieldingconstraint

SerDes-like

CMOSWire–like

IPre-use

Keyconstraints:Interconnectpitchanddieletsize

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MegaSoIFs*byre-integraNononanInterconnectFabric

The”right”interconnectfabric

•  Mechanicallyrobust(flat,sNff,tough…)

•  Capableoffinewiring,finepitchinterconnects

•  ThermallyconducNve

•  CanhaveacNveandpassivebuilt-incomponents

SiliconFitstheBillinmanycases

Challenges:

•  Warpage

•  Topography•  Assembly/Thru’put

•  Thermal

>100µmpitch

Massreflow 100µm>pitch>40µm

Massre-flow+TCB

Fullcontact–TCB

Proximate

•  InducNve

•  CapaciNve

2-10µm

*SystemonInterconnectFabric

TheseissuesarelargelymiRgatedbygoingtoasiliconIFwithsmallDielets

PreliminaryResults

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MulNpledieonSiInterconnectFabric

•  Dieletsize:4mmX4mm

•  Fanoutsize9X9to13X13mm2

•  IFsize:100mmdia

•  Force200N•  Temp350C

•  Time1’perdielet

CHIPSFramework

IntegraRonAprocessingfacilityforInterconnectFabric(IF)&assembly

• Siliconprocessing• Glass• Flexiblesubstrates• AddiNvemanufacturing

• Thermalcompressionbonding

• Waferthinning

• Wafer-waferintegraNon

ApplicaRons&Architecture

HeterogeneousSystems

ApproximateCompuNng

CogniNveCompuNng

FaultTolerance

SupplychainIntegritySecurity

MemorySubsystems

ProcessinginMemoryDFT

NetworkonBoard

MaterialsFinePitchInterconnect

SubstrateMaterials

Warpage,StressFlexibleMaterials

ThermalsoluNons

MaterialsforAddiNveMfg.Reliability

Devices/ComponentsNovelswitches

Newmemory

MEMS

Sensors

Passives,antennae

Medicaldevices

DesignInfrastructure

Thermo-Mechanical

Electrical

Tools

ParNNoning

DFT

AcNveIFDesign

Tier1EquipmentPartners

NewToolConcepts

ToolDevelopment

Scale-Up

Tier1FoundryPartners

Si,CompoundSemis,

MEMS,andOSATs

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BioCompaNbleFlexTrate®

1mm50mm

(a) (c)

(b) (d)

625Sidiesembedded inPDMS

SoCChipData Foundry

Dielet1

Dieletn

Foundry1

Foundry2

Foundry

Foundry

Foundry

Foundryn

DataFragmentaRonintodielets

•  FoundrysourceverificaRonofdielets•  ReintegraRononSiInterconnect

Fabric

Approach

ConvenNonalApproach

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Summary •  WeareinthemidstofasignificanthardwaretransformaNon

•  SemiconductorScalingissaturaNng

•  CompuNngmodelsarechanging

•  Systemsaregepngmoreheterogeneous

•  SoCsdesigncostsandTimes-to-Markethuge

•  TheCHIPSapproachwilldriveamuchmoreholisNcMoore’sLaw

•  But“ittakesavillage”•  IndustryPartners•  UniversityPartners•  GovernmentAgencies

Acknowledgements

FacultyProfs.MarkGoorsky,SudhakarPamarN,PuneetGupta

VisiNngScholars:AdeelBajwa,TakFukushima

Students:SivaJangham,ZheWan,SaptadeepPal,StevenMoran,Goutham

Ezhilarasu,FarazKhan,XuefengGu,PremKi_ur,ArsalanAlam,K.T.Kannan

WethanDARPA(N00014-16-1-2639)andmembersoftheUCLACHIPS

consorNumfortheirsupportofthiswork

chips.ucla.edu