Nov.12. 2015.

High Data Rate 60 GHz CMOS Transceiver Design

Akira Matsuzawa

Tokyo Institute of Technology

1Contents• Background and Motivation • Development of High Data Rate 60 GHz

CMOS Transceivers• High Data Rate Circuits Design• Basic Design Method for 60GHz CMOS

RF Circuits• High Speed and Low Power ADC• Future Prospect of High Data Rate

Wireless Systems• Summary

Nov.12. 2015.

2

Nov.12. 2015.

Background and Motivation

3Progress of data rate in 60 GHz band

Nov.12. 2015.

0

5

10

15

20

25

30

2007 2008 2009 2010 2011 2012 2013 2014

Dat

a ra

te [G

b/s]

Year

UCB

NEC

Univ. of Toronto

SiBeam, CEA-LETI

Toshiba

IMEC

Panasonic

UCB

Broadcom

Tokyo Tech

Our lab. is developing high data rate wireless transceivers.28 Gbps has been attained.

4

Nov.12. 2015.

60GHz bandwidth allocation on IEEE 802.ad

BPSK QPSK 16QAM 64QAM

1ch 1.76 3.52 7.04 10.562ch 3.52 7.04 14.08 21.123ch 5.28 10.56 21.12 31.684ch 7.04 14.08 28.16 42.24

Totally 9 GHz can be used.The use of high # of bit can attain ultra-high data rate com.

5

雑誌・漫画

音楽CD

映像DVD

新聞

単行本

0.01

0.1

1

10

100

1000

10000

100000

1 10 100 1000 10000

コンテンツサイズ [MB]

コンテンツ・ダウンロード推定所要時間

LTEWiMAXA社FTTHB社FTTH

マイクロUHF

ミリ波

モバイル

Visual DVD

Audio CDMagazine Comic

Book

News Paper

Contents size

Estim

ated

tim

e fo

r dow

nloa

d

MM-wave

Microwave, UHF

Mob

ile

Measured average effective data rate as of Jan. 2011

WiMAX 12Mbps

LTE 4Mbps

FTTH (A) 40Mbps

FTTH (B) 120Mbps

Time for big data contents download5/25

60GHz MM wave can transfer the DVD data within several seconds

2014

6WiGig Usage Models

WiGig White Paper, “Defining the Future of Multi-Gigabit Wireless Communications” July 2010

Nov.12. 2015.

7

Nov.12. 2015.

Development of High Data Rate

60 GHz CMOS Transceivers

8The 1st 60GHz transceiver on ISSCC 2011

LNAI Mixer

Q Mixer

PLL

36MHz REFCLK

I+I-

Q+Q-

PA I Mixer

Q Mixer

I+I-

Q+Q-

Rx input

Tx output

20GHz PLL

60GHz QILO

60GHz QILO

Two 60GHz QILOswith 20GHz PLL

TX: 186mW RX: 106mWPLL: 66mW

K. Okada, et al., ISSCC 2011

Nov.12. 2015.

Direct conversion

9The 1st 60GHz transceiver on ISSCC 2011

LNA

I MIXER

Q MIXER

Q. OSC.

PA

LO BUFFER

Q MIXER

I MIXER

LO BUFFER

LO BUFFER

LO BUFFER

QUADRATUREOSCILLATOR

4.2mm

65nm CMOSRx:3.8mm2

Tx:3.5mm2

PLL:1.2mm2

20GHz PLL

4.2m

m Buf.

VCOLPF

11Gb/s (16QAM)8Gb/s (QPSK)

Nov.12. 2015.

10The 2nd 60GHz Transceiver on ISSCC 2012

RF front-end Analog/Digital BB

Rx

VGALPF ADC

VGALPF ADC

DigitalBB

60GHz

60GHz Q

20GHz PLL BB PLL

60GHz I

Tx

DAC

DAC

DigitalBB

60GHz

60GHz Q

60GHz I

20GHz

6.3Gb/s

6.3Gb/s

20GHz

LPF

LPF

K. Okada, et al., ISSCC 2012Nov.12. 2015.

RF and baseband chips have been developed

11The 2nd 60GHz Transceiver on ISSCC 2012

40nm CMOS (BB)

4.2m

m3m

m

Tokyo Tech SONY

65nm CMOS (RF)

LNAQ MIXER

I MIXER

LO BUF.

LO BUF.

Q.OSC.

LogicI MIXER

Q MIXER

LO BUF.

LO BUF.

Q.OSC.PA

PLL LO BUF.

DCTR

DAC(Qch)

ADC(Qch)VGA

VGA

DAC(Ich)PLL

Digital BB

LVDS(11ch)

LVDS(11ch)

LDPC

ADC(Ich)RAM

10Gb/s (16QAM)TX: 319mWRX: 223mW

Nov.12. 2015.

Full transceiver has been developed.

K. Okada, et al., ISSCC 2012

12The 3rd 60 GHz Transceiver on ISSCC 2014

Nov.12. 2015.

PA

60GHzQILO

LNA

I Mixer

Q Mixer

LO buf.

RF amp.

I Mixer

Q Mixer

LO buf.60GHzQILO

20GHzPLL

TX Output

ControlLogic

I Q

I Q

BB amp. (FVF-FVF-SF)

RX Input

RF amp.Psat=10.3dBm

NF=4.2dB

Direct conversion method is used for wider bandwidth and low power*K. Okada, A. Matsuzawa., ISSCC 2014

13The 3rd 60 GHz Transceiver on ISSCC 2014

Nov.12. 2015.

PAQ MIXER

I MIXER

LO BUF.

LO BUF.

Q.OSC.

Logic

PLL

LNAI MIXER& RF amp

LO BUF.

LO BUF.

Q.OSC.

RX

BB

outTX

out

RX

inTX BB in

4.2mm

AreaTX 1.03mm2

RX 1.25mm2

PLL 0.90mm2

Logic 0.67mm2

CMOS 65nm, 1Al+11CuTX: 186mWRX: 155mWPLL: 64mW

Q MIXER& RF amp

Chip was fabricated in 65 nm CMOS technology

14Chip with antenna in package

The 60GHz RF chip are mounted on the antenna in package

Nov.12. 2015.

15Chip measurement setup

Nov.12. 2015.

RF board(TX mode) RF board

(RX mode)

ArbitraryWaveformGenerator

Power supply

Oscilloscope

Power supply

• 25-GS/s AWG• 100-GS/s oscilloscope (33GHz BW)• 14-dBi horn antennas

Chip was measured with high speed measurement system

16Measured result

Nov.12. 2015.

Channel ch.1 58.32GHz

ch.2 60.48GHz

ch.3 62.64GHz

ch.4 64.80GHz

ch.1-ch.4 bond

Modula- tion 64QAM 16QAM

Data rate 10.56Gb/s 10.56Gb/s 10.56Gb/s 10.56Gb/s 28.16Gb/s

Conste- llation

Spec- trum

TX EVM -27.1dB -27.5dB -28.0dB -28.8dB -20.0dB TX-to-RX

EVM -24.6dB -23.9dB -24.4dB -26.3dB -17.2dB

-50-40-30-20-10

0

55.82 58.32 60.82-50-40-30-20-10

0

57.98 60.48 62.98-50-40-30-20-10

0

60.14 62.64 65.14-50-40-30-20-10

0

62.30 64.80 67.30-50-40-30-20-10

0

55.56 58.56 61.56 64.56 67.56

The world’s first 64 QAM has been realizedThe world’s fastest 28 Gbps has been attained.

17Performance comparison

Nov.12. 2015.

Data rate / Modulation TX-to-RX EVM Integration Power

consumption

SiBeam [3] 7.14Gb/s(16QAM) -19dB 65nm, 32x32-array heterodyne, TX, RX, LO

TX: 1,820mWRX: 1,250mW

Tokyo Tech [4, 5]

16Gb/s(16QAM)20Gb/s(16QAM)[5] -21dB 65nm, direct-conversion, TX, RX,

LO, antenna, analog & digital BBTX: 319mWRX: 223mW

IMEC [6] 7Gb/s(16QAM) -18dB 40nm, direct-conversion, TX, RX, w/o PLL

TX: 167mWRX: 112mW

Toshiba [7] 2.62Gb/s(QPSK) N/A 65nm, heterodyne, TX, RX, LO, antenna, analog & digital BB

TX: 160mWRX: 233mW

IMEC [8] 7Gb/s(16QAM) -15dB 40nm, 4-array direct-conversion, TX, RX, LO, antenna

TX: 330mWRX: 284mWfor 1 stream

Panasonic [9] 2.5Gb/s(QPSK) -22dB 90nm, direct-conversion, TX, RX,

LO, antenna, analog & digital BBTX: 347mWRX: 274mW

Broadcom [10] 4.6Gb/s(16QAM) -20dB 40nm, 16-array heterodyne, TX, RX,

LO, antenna, analog/digital BBTX: 960mWRX: 1190mW

This work 10.56Gb/s(64QAM)28.16Gb/s(16QAM) -26dB 65nm, direct-conversion,

TX, RX, LOTX: 251mWRX: 220mW

Highest data rate with low EVM and power dissipation

18

Nov.12. 2015.

High Data Rate Circuits Design

19Data rate in communication

Nov.12. 2015.

Shannon’s theory

NSBWDrate 1log2

Wider bandwidth and higher SNR are required to attain higher data rate

Wider bandwidthMulti-cascaded amplifier

Passive mixer circuit

Higher SNR7 bit ADC

Injection locked I/Q oscillator

20Effect of the gain flatness

Nov.12. 2015.

Poor gain flatness makes ISI (Inter Symbol Interference)due to different gain for plus frequency and minus frequency.

21Multi-cascaded RF amplifiers

Nov.12. 2015.

4-stage PA MIM TL

to antenna

MIM TLTL

4-stage CS-CS LNA

from antenna

W=1m x40 1m x40 2m x20 2m x20

ESD protection

Multi-cascaded RF amplifier can increase the gain flatnessdue to the distributed resonant frequencies.

22Mixer circuit in TX

Nov.12. 2015.

LO+

LO+

LO-

50

To PA BBinput

200

200

Matching

network

Rf

Rf

ZRF

ZRF

RSW

RSW

RSW

RSW

Zin

Zin

LORFSWin ZRZ

Re8//200)( 2

Passive mixer with resistive feedback RF amplifier can realizeWidely flat impedance, rather than LC impedance matching method.

23Measured gain of TX circuit

Nov.12. 2015.

05

1015202530

0.00 1.08 2.16 3.24 4.32

Gai

n [d

B]

Frequency [GHz]

The gain flatness of 2 dB is attained for the band width of 4 GHz.

24Required phase noise of IQ-VCO for 16QAM

0

1

2

3

4

5

-100 -98 -96 -94 -92 -90 -88 -86 -84

AM-AM of PA

16QAM8PSK

QPSKR

equi

red

CN

R [d

B]

Phase noise [dBc/Hz] @ 1MHz offset

0

1

2

3

4

5

-100 -98 -96 -94 -92 -90 -88 -86 -84

AM-AM of PA

16QAM8PSK

QPSKR

equi

red

CN

R [d

B]

Phase noise [dBc/Hz] @ 1MHz offset

A phase noise of LT. -90dBc/Hz@1MHz is required for 16QAM systems

K. Scheir, et al., ISSCC, pp. 494-495,Feb. 2009.

A reported phase noise of 60GHz IQ VCO is -76dBc/Hz @1MHz at most

Nov.12. 2015.

25Q of inductors and capacitor

Nov.12. 2015.

Q of capacitor is rapidly degraded with frequency.Q of Less than 10 at 60 GHz at most.Low phase noise 60 GHz VCO is hard to be realized.

0

10

20

30

40

50

60

0.1 1 10 100

Q

Frequency [GHz]

8nH inductor2nH inductor

0.2nH inductor

switched capacitor

Qc < 10 @ 60GHz

26Frequency Multiplier

12GHz

4x

48GHz

RFIF

*S. Emami, et al., ISSCC 2011

2x

30GHz

90o hybrid 0o

90o

60GHz

**C. Marcu, et al., ISSCC 2009

20GHz

0o, 180o

90o, 270o

60GHz***W. Chan, et al., ISSCC 2008

(1)

(2)

(3)

• for hetero-dyne TRX• reasonable for PN and FTR

• 60GHz QILO***• good for PN and FTR

• 30GHz is too high for PN and FTR

• I/Q phase calibration is required.

(20GHz x 3, 15GHz x4 are OK.)

27Injection locked 60GHz I/Q VCO

Nov.12. 2015.

VDD

INJp

INJn

Ip

In

Qp

Qn

20G

Hzm

atch

ing

bloc

k

60 GHz out

60 GHz out

20 GHz in

We have developed the injection locked 60 GHz I/Q VCOThe 60 GHz quadrature VCO is injected by 20 GHz PLL

A. Musa, K. Okada, A. Matsuzawa., in A-SSCCDig. Tech. Papers, pp. 101–102, Nov. 2010.

2860GHz Quadrature LO Design

36/40MHz ref.

PFD CP LPF

20GHz PLL

4 (54,55,56,5758,59,60)

2

5

4.5

60GHz QILO*

58.32GHz59.40GHz60.48GHz61.56GHz62.64GHz63.72GHz64.80GHz

*K. Okada, et al., ISSCC 2011

• 20GHz PLL: 64mW• 60GHz QILO: 18mW(TX)&15mW(RX)• QILO frequency range: 58-66GHz• Phase noise improvement by injection locking*• -96.5dBc/Hz @ 1MHz at 61.56GHz

29Injection locking technique

OutputINJP

INJN

Injectionsignal

N: Multiple number

t

t

parallel injection

)log(20INJILO NPNPN 9.5dB @ N=3

IIOSC

injoL Q

ff 2

Injection locking technique is a very important circuit techniquefor high frequency signal generation and frequency divider.Phase noise of the oscillator is mandated by the injection signal.

Phase noise

Locking frequency range

Nov.12. 2015.

30Low phase noise can be realized

A. Musa, K. Okada, A. Matsuzawa., in A-SSCCDig. Tech. Papers, pp. 101–102, Nov. 2010.

Quadrature injection locked 60GHz oscillator with 20GHz PLLLow phase noise of -96dBc/Hz @1MHz. Previous one is -76dBc/Hz@1MHz

58-63GHz, -96dBc/Hz-1MHz offsetBest phase noise is achieved.

Nov.12. 2015.

31

Basic Design Method for 60GHz

CMOS RF Circuits

Nov.12. 2015.

32Gain and Noise; fmax and fT

Lower gain MAG is inversely proportional

to the logarithm of the operating frequency fc.

Higher noise NFmin is proportional to the

operating frequency fc.

Wf=2.5μm, Nf=32, Vgs=0.8V and Vds=0.8V.

log-log scale

semi-log scale

Gain and noise are mainly determined by fmax and fT of Transistor

65nm NMOS

sgmT

c RRgffNF

3.11min

cffG max

max

Nov.12. 2015.

33

0

500

1000

1500

2000

2500

2010 2015 2020 2025 2030

fT

CMOS

GaAsInP

0

500

1000

1500

2000

2500

2010 2015 2020 2025 2030

fmax

CMOS

GaAsInP

Bulk CMOSUltra-Thin-Body Fully-Depleted (UTB FD) SOIMulti-Gate MOSFETs

Basic RF performancesfmax and fT of MOS transistor will increase continuously.Gain and NF will be improved by using future CMOS technology.

ITRS RFAMS 2011.

cffG max

max sgmT

c RRgffNF

3.11min

Nov.12. 2015.

34Cross coupled feedback capacitors

Ccc

Ccc

Cgd-Ccc

Cgd-Ccc

Capacitance iscancelled

)()/(2maxdsschggdgsgdmg

T

gRrRCCCgRff

This term is reduced

Differential circuit

Max

Gai

n[dB

]

Frequency[GHz]

0

5

10

15

20

25

30

35

0 20 40 60 80 100 120

w/o cross-coupled cap.w/ cross-coupled cap.

6dB up

Y. Natsukari, et al., VLSI Circuits, Dig. Tech. Papers, pp. 252–253, June 2009.

W. L. Chan, et al., ISSCC. Tech. Dig., pp. 380–381, Feb. 2009.

Cross coupled feedback capacitors in a differential circuitcan reduce the effective capacitance to increase the gain of6dB at 60GHz.

Nov.12. 2015.

35Feedback signal and stability

w/ cros-coupled cap.w/o cross-coupled cap.

-70

-50

-60

-40

-30

-20

-10

0 10 20 30 40 50 60 70 80 90 100 110

S(1,

2) [d

B]

Frequency [GHz]

w/ cros-coupled cap.w/o cross-coupled cap.

-10

10

0

20

30

40

0 10 20 30 40 50 60 70 80 90 100 110St

abili

ty fa

ctor

Frequency [GHz]

Feedback signal Stability factor

Feedback signal is suppressed by the cross coupled capacitorsand this increase the stability of amplifier.

Nov.12. 2015.

36Development history of 60GHz circuits

Device modelingTrial & Error

First 16QAM TRxISSCC 2011

RF+BBISSCC 2012

Nov.12. 2015.

37

Each component isimplemented as an in-housePDK for Agilent ADS.

PVT

RNMOS

MOS cap

VaractorMIM

DC probe

RF PAD

MIM TL

TL with L/T

C

PMOS

In-house PDK

for ADS

Nov.12. 2015.

38Key technology: low loss TR line

• 0.8dB/mm• Manually-placed dummy metal

GND

dummy

signal(10m)

gap(15m) GND

M1&M2 shieldGND GND

0.0

0.5

1.0

1.5

2.0

2.5

0 10 20 30 40 50 60 70Frequency [GHz]

[dB

/mm

]

`

manualauto

303540455055606570

0 10 20 30 40 50 60 70Frequency [GHz]

Z0 [o

hm]

manualauto

Optimized parameter and manually-placed dummy metal realize low loss transmission line.

Nov.12. 2015.

39Basic amplifier design

Matchingnetwork

Amp. 1 Amp. 2

outZ *outZ inZ*

inZGain maxLoss min

Gain max

Feedback pass

1st, 2nd stage 3rd, 4th satge MIM TL for dec.

50, 0.8dB/mm

Z0=3

A several GHz oscillation will occur, if the feedback passes are made.

Amplifier design;accurate sizing, biasing, impedance matching and decoupling.

Nov.12. 2015.

40

0

42

68

10

0 10 20 30 40 50 60 70Z0

[]

Frequency [GHz]

MeasurementProposed Model

Decoupling capacitor

A decoupling capacitor has been developed using MIM capacitorwith distributed structure to prevent a resonance,Which occurs, if used a conventional capacitor structure.A very low impedance of 3 ohm is realized.

Nov.12. 2015.

41Tile-based layout method

T-Junction Tr TL C

GND-TileRF PAD

Each component is previously measured and modeled.The same layout is utilized to maintain modeling accuracy.

MIM TL

5mm pitch

L-Bend

Nov.12. 2015.

42In-house PDK

for Virtuoso

Nov.12. 2015.

We have developed in-house PDK for 60-GHz circuit design

43

0

2

4

6

8

10

40 50 60 70 80Frequency[GHz]

S21[

dB]

S11 S22(RED:meas BLUE:sim)

IN OUTT-Junc.Tr.MOM Cap.

Bend

TL

Design Example

Nov.12. 2015.

High design accuracy at around 60GHz has been attained

44

Nov.12. 2015.

High Speed and Low Power ADC

457bit 2.2GSps ADC for 60GHz ABB

Nov.12. 2015.

Encoder

Coarse SR

LatchTim

e-basedFolder x 4

Fine InterpolatedSR

Latch

D-FF x 7

Resistive A

veraging

Ref ladder

・7bit ADC for the 16QAM modulation・Convert the voltage difference to the timing difference・Folding and interpolation are realized by logic gates

M. Miyahara, A. Matsuzawa, ISSCC 2014

0.25mm

0.21

mm

46V to T conversion in dynamic amplifier

21Δ ininin VVV

TimeVo

ltage

Voa

Vob

T

VDD

VDD/2 Logic threshold

0T

0TVVTeff

in TGSeff VVV

Voltage difference can be converted to time difference in a dynamic amplifier.

Nov.12. 2015.

Vin1

Vin2

VDD

CLK

CL CL

Voa

Vob

gm gm

ID1 ID2

CLK

Dynamic amplifier

47Conversion from the voltage to the timing

V-T

V-T

V-T

DP3

DN3

DP2

DN2

DP1

DN1

L

VINP3

VINN3

VINP2

VINN2

VINP1

VINN1

Nov.12. 2015.

The signal generation of larger voltage difference is fasterin the dynamic amplifier.

Dynamic Amps.

early signal

late signal

48Signal folding in time-domain

Del

ay T

ime

D2_1=D1_1 AND D1_2

D1_1=DN0 OR DP2 D1_2=DN4 OR DP6

（Valley fold：Select late）

（Mountain fold：Select early)

Nov.12. 2015.

OR: Select early pulse

AND: Select late pulse

Signal folding in time-domain can be realized easily by simple logic gates.

49Performance comparison

Nov.12. 2015.

ISSCC 2008 [3] VLSI 2012 [8] VLSI 2013 [9] This workTechnology 90nm 40nm 32nm SOI 40nm LP

Resolution [bit] 5 6 6 7Power Supply [V] 1 1.1 0.85 1.1

Sampling Frequency [GS/s] 1.75 3 5 2.2Power Consumption [mW] 2.2 11 8.5 27.4

SNDR @Nyquist [dB] 27.6 33.1 30.9 37.4FoMw [fJ/conv.-step] 64.5 99.3 59.4 210

FoMs [dB] 143.5 144.4 145.6 143.3Core area [mm2] 0.0165 0.021 0.02 0.052

Calibration Off chip Foreground Off chip No need

Highest SNDR of 37.4 dB is attained in flash ADCsNo calibration circuits are required. This ADC will contribute increase of data rate of 60 GHz transceivers.

Pd is large so far, however can be reduced by the optimization.

50

Nov.12. 2015.

Future Prospect of

High Data Rate Wireless Systems

51Link budget example of wireless system

Nov.12. 2015.

6dBm(Pout)-4dB(back-off)=2dBm

-80.6dBm=-174dBm(kT)+93.4dB(2.2GHz-BW)

-74.6dBm+6dB(NF)

-60.5dBm-3dB(loss)

CNR+14.0dB

Tx

Rx

-71.5dB(1.5m loss)+6dBi(Tx)+6dBi(Rx)

Required CNR: 9.8dB

Antenna gain：6dBiSignal

Noise

Signal

Noise

for QPSK system

60 GHz, 1.5 m

Transmitted RF power is lowered so much at the receiver

52Calculations

Nov.12. 2015.

NSBWDrate 1log2Shannon’s theory

3

)(3.0

log10 dBSNRBWSNRBWDrate

LOSSLARATOFFTXRX SIGGBPdBP )(

c

cLOSS df

cdfc

dS

4log20

4log20

4log20

NFBWdBmPn log10174)(

Received signal

Spatial loss

d: distancefc: career frequency

Noise

Calculate the data rate as function of career frequency and Tx power

53Estimated data rate

Nov.12. 2015.

0

0

0

0

0

50

100

150

0 10 100 1000

Dat

a ra

te (G

bps)

Carrier frequency (GHz)

Pt=20dBm

Pt=10dBm

Pt=0dBm

BPSK

QPSK

16QAM64QAM

Solid line: consider the SNRDashed line: neglect the SNR

Distance：1mAntenna gain：6dBiNF: 6dBBack off： 4dBPower loss： 3dB

There is an optimum frequency for the maximum data rate.Higher Tx power is required to increase the data rate.16 QAM looks the best to attain the maximum data rate.

54Future direction

Nov.12. 2015.

High frequencyand high power Best but very difficult !!

High frequencybut low power

High gainantenna

Low gainantenna

Sharp beam

Fixed point only !

Short distance only !

Medium frequencybut high power

Reasonable high data rate

Reasonable long distance

Future direction should be chosen by the usage model

55Our roadmap for 300Gbps data transfer

7Gbps

28Gbps

10.5Gbps

2014

16QAM 64QAM

42Gbps

328Gbps

56Gbps

20162012 20182015 20172013 2019

Dat

a R

ate

[Gbp

s] Wider BW × larger N×MIMO

Nov.12. 2015.

56Summary• High data rate wireless communication is demanded• 28 Gb/s has been realized • Wider bandwidth and higher SNR are the keys

– Multi-cascaded amplifier– Passive mixer with resistive feedback– Injection locked I/Q oscillator– 7 bit ADC with time domain processing

• Accurate RF modeling and measurement up to 100 GHz is fundamentally important

• Optimum frequency for the maximum data rate.- Higher frequency does not guarantee the higher data rate- Higher Tx power is required to increase the data rate.

• Future direction should be chosen by the usage model– Long distance with reasonable data rate – Short distance with high data rate

Nov.12. 2015.

NSBWDrate 1log2

57Acknowledgement

• I would like to thank Prof. K. Okada and this work was partially supported by MIC, SCOPE, MEXT, STARC, Huawei, Canon Foundation, STAR, and VDEC in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., and Mentor Graphics, Inc., and Agilent Technologies Japan, Ltd.

Nov.12. 2015.

And also,

58Acknowledgement

Han(modeling) Bunsen(Rx)Matsushita(Tx)

Minami(TRx)

Sato(VCO) Asada(PA)

Musa(PLL)Murakami(ILO)

Yamaguchi(ILO)Okada

Bu(LNA)

2010/9/7@ South Bldg. 9, 5F cleanroom

+W. Chaivipas, N. Li, N.Takayama, S.Ito, Y.Nomiyama

Thanks lot to students

Nov.12. 2015.