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High-Level Programming of High-Performance Reconfigurable Computers: MAPLD BOF-H2 Panel. Tarek El-Ghazawi The George Washington University [email protected] http://www.seas.gwu.edu/~tarek. The Question and My Answer. - PowerPoint PPT Presentation
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High-Level Programming of High-Performance
Reconfigurable Computers:MAPLD BOF-H2 Panel
High-Level Programming of High-Performance
Reconfigurable Computers:MAPLD BOF-H2 Panel
Tarek El-Ghazawi
The George Washington University
http://www.seas.gwu.edu/~tarek
Tarek El-Ghazawi
The George Washington University
http://www.seas.gwu.edu/~tarek
Tarek El-Ghazawi, GWU MAPLD BOF-H-2 Panel Washington D.C., September 6-9, 2005 Slide 2
The Question and My Answer
"Can we develop a software-level programming approach (e.g., a C language compiler) for FPGAs that spans the needs of the high performance reconfigurable computing community with amultitude of FPGA-based HPC systems and also the needs of the electronic design automation community with a multitude of FPGA board designs?
My Answer:
You Bet!
Tarek El-Ghazawi, GWU MAPLD BOF-H-2 Panel Washington D.C., September 6-9, 2005 Slide 3
HOW?
Abstraction Design a rich programming model for high-
performance reconfigurable machines
Extend a standard sequential language to conform to the programming model view
Compilers to address common architectural features
Run-time systems to tune to specific machine features
Tarek El-Ghazawi, GWU MAPLD BOF-H-2 Panel Washington D.C., September 6-9, 2005 Slide 4
Programming Models for Parallel Computers
Message Passing Shared Memory DSM/PGASEx: MPI[e.g. +C] Ex: OpenMP[e.g.+C] Ex: UPC
Process/Thread
Address Space
Data Parallel e.g. HPF, C*
Tarek El-Ghazawi, GWU MAPLD BOF-H-2 Panel Washington D.C., September 6-9, 2005 Slide 5
How cont.! Avoid the hype! Need to know that it is hard, will take
enormous time and resources, but REALLY WORTH IT! Needed Efforts
Need abstract programming model(s) to express» fine grain data parallelism and coarse grain functional
parallelism» multiple levels of locality
Need automatic H.W./S.W partitioning and scheduling algorithms
Need compilers to address automatically general hardware optimizations and use reconfiguration to achieve them
Need run-time systems to support further machine specific tunings
Need H.W./S.W. debuggers and performance analysis tools And a lot more!!! But the good news are:
» There are solid intermediate steps» There are works in related areas that can be leveraged