High-Level Test Generation

Test Generation by Enhancing Validation Test

Sets*

* L. Lingappan, et al., VLSI Design, 2007 (Paper available on the class website)

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Basic Idea

Reuse validation test sequencesFixed control sequence, only data path values need to be determinedPrecomputed module tests are usedIf validation sequences are instruction-level, so are the generated testsRTL level analysis means faster times

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Details

Basis for analysis:RTL circuit and controller FSMCDFG and state transition sequence for a given validation test sequence

Not all test sequences are analyzed for all precomputed test vectors because this could be computationally expensive. Instead, heuristics are used to determine compatibility.

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ProcessFault simulate validation test sequences and determine the activation time cycle for each detected fault.If a detected fault falls within a module, the sequence is a candidate for applying precomputed test vectors

Determine compatibility of each test vector with the sequenceIf compatible, then justify and propagate

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Example RTL Circuit

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Controller Specification

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CDFG and State Transition Sequence Exercised by test

T1

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Activation and Detection Cycle

for Target Fault

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Justification of Required Values-1

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Justification of Required Values-2

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Circuits Used in Experiments

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Test Generation Results

Test Generation with Functional Fault Modleing*

* Hansen and Hayes, VLSI Test Symposium, 1995, pp. 20-28.

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Summary

High-level fault modeling ensuring coverage of low-level (physical or single-stuck-line) faults.Fault effects induced from low (gate) to high (RTL or functional) levelAllows discovery of minimum test sets at the high level that are hard to find by low (gate-level) techniques

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Functional Fault ModelsGeneral Faults (Universal)Pin FaultsBoth of the above are implementation and

technology independent

Induced faults: Physically Induced Faults (PIFs) Derived from an implementation by the induction process, hence implementation dependent and may be technology dependent.PIFs derived from single stuck-at faults are denoted as SIFs in the paper.

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Faults, Functions, and Tests

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Example

Consider the effect of some sample SAFs on the circuit function:

A SA0A SA1AP SA0

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SIFs of the Example CircuitConsider Fault Dominance:

Top 6 dominate the rest, hence only need to cover these.

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Minimal SIF Test Set

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Dependence on Implementation

(b) and (c) havefault functions notcovered by thoseof (a). Hence requireadditional SIFs

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Extension to Ripple-Carry Circuit

Ci+1

M

Ci

Ai

Bi

MC0

A0

B0

MC1

A1

B1

MC2

A2

B2

MC3

A3

B3

C4

How many SIF tests are required for the RCC?

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Test Set Sizes

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Larger Examples

CLA Generator (74182)

• Eliminate the logic gates for G and P in the carry circuit• Cascade the above module as in the RCC.

How do the SIFs change for the module?How many tests for the whole circuit?

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Tests Required for 4-bit CLA Generator

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4-bit Adder (74283)The 10 tests for CLA can be extended to cover the XOR modules. Hence 10 tests suffice for this circuit also.

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ALU Circuit (74181)CLA again dominates the test generation.12 Tests are required, of which 10 correspond to testing CLA.

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Summary of Results(For Medium Circuits)

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The paper goes on to apply the technique to ISCAS85 circuits. They needed to extract high-level models for these circuits by painstaking reverse-engineering. These models are available from Prof. Hayes’ website at U. Michigan.

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ConclusionPhysical fault effects induced at the functional levelUnlike prior high-level models, PIFs allow complete low-level coverage.However, the analysis is not automatic and the results do depend on the implementationThe technique allowed obtaining provably minimum test sets for various common known implementations.