High Performance Current Mode Controllers · 2013. 6. 27. · Current Mode Controllers The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They

Semiconductor Components Industries, LLC, 2004

September, 2004 − Rev. 31 Publication Order Number:

UC3844B/D

UC3844B, UC3845B,UC2844B, UC2845B

High PerformanceCurrent Mode Controllers

The UC3844B, UC3845B series are high performance fixedfrequency current mode controllers. They are specifically designed forOff−Line and dc−dc converter applications offering the designer acost−effective solution with minimal external components. Theseintegrated circuits feature an oscillator, a temperature compensatedreference, high gain error amplifier, current sensing comparator, and ahigh current totem pole output ideally suited for driving a powerMOSFET.

Also included are protective features consisting of input andreference undervoltage lockouts each with hysteresis, cycle−by−cyclecurrent limiting, a latch for single pulse metering, and a flip−flopwhich blanks the output off every other oscillator cycle, allowingoutput deadtimes to be programmed from 50% to 70%.

These devices are available in an 8−pin dual−in−line and surfacemount (SOIC−8) plastic package as well as the 14−pin plastic surfacemount (SOIC−14). The SOIC−14 package has separate power andground pins for the totem pole output stage.

The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off),ideally suited for off−line converters. The UCX845B is tailored forlower voltage applications having UVLO thresholds of 8.5 V (on) and7.6 V (off).

Features

• Pb−Free Packages are Available

• Trimmed Oscillator for Precise Frequency Control

• Oscillator Frequency Guaranteed at 250 kHz

• Current Mode Operation to 500 kHz Output Switching Frequency

• Output Deadtime Adjustable from 50% to 70%

• Automatic Feed Forward Compensation

• Latching PWM for Cycle−By−Cycle Current Limiting

• Internally Trimmed Reference with Undervoltage Lockout

• High Current Totem Pole Output

• Undervoltage Lockout with Hysteresis

• Low Startup and Operating Current

14

SOIC−14D SUFFIX

CASE 751A1

See detailed ordering and shipping information in the packagedimensions section on page 2 of this data sheet.

ORDERING INFORMATION

See general marking information in the device markingsection on page 16 of this data sheet.

DEVICE MARKING INFORMATION

1

8

PDIP−8N SUFFIXCASE 626

PIN CONNECTIONS

Compensation

NC

Voltage Feedback

NC

Current Sense

NC

RT/CT

Compensation

Voltage Feedback

Current Sense

RT/CT

Vref

Vref

NC

VCC

VC

Output

GND

Power Ground

VCC

Output

GND

(Top View)

8

7

6

5

1

2

3

4

1

2

3

4

14

13

12

11

5

6

7

10

9

8

(Top View)

SOIC−8D1 SUFFIXCASE 751

1

8

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Pin numbers in parenthesis are for the D suffix SOIC−14 package.

Output

VC

RT/CT

Vref

VCCUndervoltage

Lockout

GND

5.0VReference

VrefUndervoltage

Lockout

LatchingPWM

Oscillator

ErrorAmplifier

5(9)

3(5)

5(8)

6(10)

7(11)

PowerGround

CurrentSense Input

1(1)

2(3)

4(7)

8(14)

Output/Compensation

VoltageFeedback

Input

VCC 7(12)

R

R

Figure 1. Simplified Block Diagram

ORDERING INFORMATION

DeviceOperating

Temperature Range Package Shipping †

UC384xBD SOIC−14 55 Units/Rail

UC384xBDR2 SOIC−14 2500 Tape & Reel

UC3844BDR2G SOIC−14(Pb−Free)

2500 Tape & Reel

UC384xBD1 SOIC−8 98 Units/Rail

UC3844BD1GTA = 0° to +70°C

SOIC−8(Pb−Free)

98 Units/Rail

UC384xBD1R2

A

SOIC−8 2500 Tape & Reel

UC384xBD1R2G SOIC−8(Pb−Free) 2500 Tape & Reel

UC384xBN PDIP−8 50 Units/Rail

UC384xBNG PDIP−8(Pb−Free)

50 Units/Rail

UC2845BD SOIC−14 55 Units/Rail

UC284xBDR2 SOIC−14 2500 Tape & Reel

UC2845BDR2G SOIC−14(Pb−Free)

2500 Tape & Reel

UC2845BD1 TA = −25° to +85°C SOIC−8 98 Units/Rail

UC284xBD1R2

A


UC284xBD1R2G SOIC−8(Pb−Free)

2500 Tape & Reel

UC2844BN PDIP−8 50 Units/Rail

UC384xBVD SOIC−14 55 Units/Rail

UC3844BVDR2 SOIC−14 2500 Tape & Reel

UC384xBVD1 TA = −40° to +105°C SOIC−8 98 Units/Rail

UC384xBVD1R2

A


UC384xBVN PDIP−8 50 Units/Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

x indicates either a 4 or 5 to define specific device part numbers.

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MAXIMUM RATINGS

Rating Symbol Value Unit

Total Power Supply and Zener Current (ICC + IZ) 30 mA

Output Current, Source or Sink (Note 1) IO 1.0 A

Output Energy (Capacitive Load per Cycle) W 5.0 J

Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V

Error Amp Output Sink Current IO 10 mA

Power Dissipation and Thermal CharacteristicsD Suffix, Plastic Package, SOIC−14 Case 751A

Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air

D1 Suffix, Plastic Package, SOIC−8 Case 751Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air

N Suffix, Plastic Package, Case 626Maximum Power Dissipation @ TA = 25°CThermal Resistance, Junction−to−Air

PDRJA

PDRJA

PDRJA

862145

702178

1.25100

mW°C/W

mW°C/W

W°C/W

Operating Junction Temperature TJ +150 °C

Operating Ambient TemperatureUC3844B, UC3845BUC2844B, UC2845B

TA0 to + 70

− 25 to + 85

°C

Storage Temperature Range Tstg − 65 to +150 °CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limitvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.1. Maximum package power dissipation limits must be observed.

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max valuesTA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)

UC284XB UC384XB, XBV

Characteristic Symbol Min Typ Max Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V

Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV

Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV

Temperature Stability TS − 0.2 − − 0.2 − mV/°C

Total Output Variation over Line, Load, and Temperature Vref 4.9 − 5.1 4.82 − 5.18 V

Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − V

Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV

Output Short Circuit Current ISC − 30 − 85 −180 − 30 − 85 −180 mA

OSCILLATOR SECTION

FrequencyTJ = 25°CTA = Tlow to ThighTJ = 25°C (RT = 6.2 k, CT = 1.0 nF)

fOSC4948225

52−

250

5556275

4948225

52−

250

5556275

kHz

Frequency Change with Voltage (VCC = 12 V to 25 V) fOSC/V − 0.2 1.0 − 0.2 1.0 %

Frequency Change with Temperature (TA = Tlow to Thigh) fOSC/T − 1.0 − − 0.5 − %

Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V

Discharge Current (VOSC = 2.0 V)TJ = 25°CTA = Tlow to Thigh (UC284XB, UC384XB)TA = Tlow to Thigh (UC384XBV)

Idischg7.87.5−

8.3−−

8.88.8−

7.87.67.2

8.3−−

8.88.88.8

mA

2. Adjust VCC above the Startup threshold before setting to 15 V.3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B= − 40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV

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ERROR AMPLIFIER SECTION

Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V

Input Bias Current (VFB = 5.0 V) IIB − − 0.1 −1.0 − − 0.1 − 2.0 A

Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB

Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz

Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB

Output CurrentSink (VO = 1.1 V, VFB = 2.7 V)Source (VO = 5.0 V, VFB = 2.3 V)

ISinkISource

2.0− 0.5

12−1.0

−−

2.0− 0.5

12−1.0

−−

mA

Output Voltage SwingHigh State (RL = 15 k to ground, VFB = 2.3 V)Low State (RL = 15 k to Vref, VFB = 2.7 V)

(UC284XB, UC384XB)(UC384XBV)

VOHVOL

5.0

−−

6.2

0.8−

−

1.1−

5.0

−−

6.2

0.80.8

−

1.11.2

V

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 6 & 7)(UC284XB, UC384XB)(UC384XBV)

AV2.85

−3.0−

3.15−

2.852.85

3.03.0

3.153.25

V/V

Maximum Current Sense Input Threshold (Note 6)(UC284XB, UC384XB)(UC384XBV)

Vth0.9−

1.0−

1.1−

0.90.85

1.01.0

1.11.1

V

Power Supply Rejection Ratio(VCC = 12 V to 25 V) (Note 6)

PSRR − 70 − − 70 − dB

Input Bias Current IIB − − 2.0 −10 − − 2.0 −10 A

Propagation Delay (Current Sense Input to Output) tPLH(In/Out) − 150 300 − 150 300 ns

OUTPUT SECTION

Output VoltageLow State (ISink = 20 mA)

(ISink = 200 mA, UC284XB, UC384XB)(ISink = 200 mA, UC384XBV)

High State (ISource = 20 mA, UC284XB, UC384XB)(ISource = 20 mA, UC384XBV)(ISource = 200 mA)

VOL

VOH

−−−13−12

0.11.6−

13.5−

13.4

0.42.2−−−−

−−−13

12.912

0.11.61.613.5

−13.4

0.42.22.3−−−

V

Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V

Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns

Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup ThresholdUCX844B, BVUCX845B, BV

Vth157.8

168.4

179.0

14.57.8

168.4

17.59.0

V

Minimum Operating Voltage After Turn−OnUCX844B, BVUCX845B, BV

VCC(min)9.07.0

107.6

118.2

8.57.0

107.6

11.58.2

V



6. This parameter is measured at the latch trip point with VFB = 0 V.7. Comparator gain is defined as: AV = V Output/Compensation

V Current Sense Input

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PWM SECTION

Duty CycleMaximum (UC284XB, UC384XB)Maximum (UC384XBV)Minimum

DC(max)

DC(min)

47−−

48−−

50−0

4746−

4848−

50500

%

TOTAL DEVICE

Power Supply CurrentStartup (VCC = 6.5 V for UCX845B, Startup (VCC = 14 V for UCX844B, BV)Operating (Note 8)

ICC−

−

0.3

12

0.5

17

−

−

0.3

12

0.5

17

mA

Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V



0.8

2.0

5.0

8.0

20

50

80

RT,

TIM

ING

RE

SIS

TOR

(k

)Ω

1.0 M500 k200 k100 k50 k20 k10 k

fOSC, OSCILLATOR FREQUENCY (kHz)

Figure 2. Timing Resistorversus Oscillator Frequency

Figure 3. Output Deadtimeversus Oscillator Frequency

1.0 M100 k10 k

fOSC, OSCILLATOR FREQUENCY (kHz)

50

% D

T, P

ER

CE

NT

OU

TP

UT

DE

AD

TIM

E

ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ

1.CT = 10 nF2.CT = 5.0 nF3.CT = 2.0 nF4.CT = 1.0 nF5.CT = 500 pF6.CT = 200 pF7.CT = 100 pF

55

60

65

70

75

20 k 50 k 200 k 500 k

2

3

7

5

6NOTE: Output switches at1/2 the oscillator frequency

VCC = 15 VTA = 25°C

0.5 s/DIV

20 m

V/D

IV

2.55 V

2.5 V

2.45 V

VCC = 15 VAV = −1.0TA = 25°C

VCC = 15 VAV = −1.0TA = 25°C

1.0 s/DIV

200

mV

/DIV

2.5 V

3.0 V

2.0 V

Figure 4. Error Amp Small SignalTransient Response

Figure 5. Error Amp Large SignalTransient Response

1

4

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∆, O

UT

PU

T V

OLT

AG

E C

HA

NG

E (

2.0

mV

/DIV

)

O

V

−20

AV

OL

, OP

EN

LO

OP

VO

LTA

GE

GA

IN (

dB)

10 M10

f, FREQUENCY (Hz)

Gain

Phase

0

30

60

90

120

150

180100 1.0 k 10 k 100 k 1.0 M

0

20

40

60

80

100

, EX

CE

SS

PH

AS

E (

DE

GR

EE

S)

φ

0

VO, ERROR AMP OUTPUT VOLTAGE (VO)

0

, CU

RR

EN

T S

EN

SE

INP

UT

TH

RE

SH

OLD

(V

)V

th

0.2

0.4

0.6

0.8

1.0

1.2

2.0 4.0 6.0 8.0

TA = −55°C

ÄÄÄÄÄÄÄÄ

VCC = 15 VRL ≤ 0.1

Figure 6. Error Amp Open Loop Gain andPhase versus Frequency

Figure 7. Current Sense Input Thresholdversus Error Amp Output Voltage

Figure 8. Reference Voltage Changeversus Source Current

Figure 9. Reference Short Circuit Currentversus Temperature

, RE

FE

RE

NC

E V

OLT

AG

E C

HA

NG

E (

mV

)

−16

0

Iref, REFERENCE SOURCE CURRENT (mA)

20 40 60 80 100 120

ref

V

−12

−8.0

−4.0

0

, RE

FE

RE

NC

E S

HO

RT

CIR

CU

IT C

UR

RE

NT

(mA

)S

CI

50−55

TA, AMBIENT TEMPERATURE (°C)

−25 0 25 50 75 100 125

70

90

110

∆

−20

−24

TA = 125°C

VCC = 15 VVO = 2.0 V to 4.0 VRL = 100 kTA = 25°C

VCC = 15 V

TA = 25°C

∆, O

UT

PU

T V

OLT

AG

E C

HA

NG

E (

2.0

mV

/DIV

)

O

2.0 ms/DIV

V

2.0 ms/DIV

VCC = 12 V to 25 VTA = 25°C

VCC = 15 VIO = 1.0 mA to 20 mATA = 25°C

Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation

VCC = 15 V

TA = 125°C

TA = 25°C

TA = −55°C

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ÄÄÄÄÄÄÄÄÄÄ

Sink Saturation(Load to VCC)

ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ

RT = 10 kCT = 3.3 nFVFB = 0 VISense = 0 VTA = 25°C

, SU

PP

LY C

UR

RE

NT

(mA

)C

CI

00

VCC, SUPPLY VOLTAGE (V)

10 20 30 40

5

10

15

20

25

UC

X84

5B

UC

X84

4B

Figure 12. Output Saturation Voltageversus Load Current

Figure 13. Output Waveform

ÄÄÄÄÄÄ

TA = 25°C

ÄÄÄÄÄÄÄÄ

TA = −55°C

ÄÄVCC ÄÄÄÄÄÄÄÄÄÄ

VCC = 15 V80 s Pulsed Load120 Hz Rate

ÄÄÄÄÄÄÄÄ

TA = −55°C

ÄÄÄÄÄÄÄÄ

TA = 25°C

0

V sat

, OU

TP

UT

SA

TU

RA

TIO

N V

OLT

AG

E (

V)

8000

IO, OUTPUT LOAD CURRENT (mA)

200 400 600

1.0

2.0

3.0

−2.0

−1.0

0

ÄÄÄÄÄÄÄÄÄÄ

Source Saturation(Load to Ground)

ÄÄÄGND

50 ns/DIV

90%

10%

VCC = 15 VCL = 1.0 nFTA = 25°C

100 ns/DIV

VCC = 30 VCL = 15 pFTA = 25°C

, SU

PP

LY C

UR

RE

NT

100

mA

/DIV

20 V

/DIV

I, O

UT

PU

T V

OLT

AG

EV

CC

O

Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage

PIN FUNCTION DESCRIPTION

Pin

8−Pin 14−Pin Function Description

1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.

2 3 Voltage Feedback

This is the inverting input of the Error Amplifier. It is normally connected to the switching powersupply output through a resistor divider.

3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses thisinformation to terminate the output switch conduction.

4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistorRT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.

5 GND This pin is the combined control circuitry and power ground.

6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourcedand sunk by this pin. The output switches at one−half the oscillator frequency.

7 12 VCC This pin is the positive supply of the control IC.

8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.

8 Power Ground

This pin is a separate power ground return that is connected back to the power source. It is usedto reduce the effects of switching transient noise on the control circuitry.

11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power sourceconnection, it can reduce the effects of switching transient noise on the control circuitry.

9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.

2,4,6,13 NC No connection. These pins are not internally connected.

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OPERATING DESCRIPTION

The UC3844B, UC3845B series are high performance,fixed frequency, current mode controllers. They arespecifically designed for Off−Line and dc−dc converterapplications offering the designer a cost−effective solutionwith minimal external components. A representative blockdiagram is shown in Figure 16.

OscillatorThe oscillator frequency is programmed by the values

selected for the timing components RT and CT. Capacitor CTis charged from the 5.0 V reference through resistor RT toapproximately 2.8 V and discharged to 1.2 V by an internalcurrent sink. During the discharge of CT, the oscillatorgenerates an internal blanking pulse that holds the centerinput of the NOR gate high. This causes the Output to be ina low state, thus producing a controlled amount of outputdeadtime. An internal flip−flop has been incorporated in theUCX844/5B which blanks the output off every other clockcycle by holding one of the inputs of the NOR gate high. Thisin combination with the CT discharge period yields outputdeadtimes programmable from 50% to 70%. Figure 2 showsRT versus Oscillator Frequency and Figure 3, OutputDeadtime versus Frequency, both for given values of CT.Note that many values of RT and CT will give the sameoscillator frequency but only one combination will yield aspecific output deadtime at a given frequency. The oscillatorthresholds are temperature compensated to within ±6% at 50 kHz. Also, because of industry trends moving theUC384X into higher and higher frequency applications, theUC384XB is guaranteed to within ±10% at 250 kHz.

In many noise−sensitive applications it may be desirableto frequency−lock the converter to an external system clock.This can be accomplished by applying a clock signal to thecircuit shown in Figure 18. For reliable locking, thefree−running oscillator frequency should be set about 10%less than the clock frequency. A method for multi−unitsynchronization is shown in Figure 19. By tailoring theclock waveform, accurate Output duty cycle clamping canbe achieved to realize output deadtimes of greater than 70%.

Error AmplifierA fully compensated Error Amplifier with access to the

inverting input and output is provided. It features a typicaldc voltage gain of 90 dB, and a unity gain bandwidth of1.0 MHz with 57 degrees of phase margin (Figure 6). Thenon−inverting input is internally biased at 2.5 V and is notpinned out. The converter output voltage is typically divideddown and monitored by the inverting input. The maximuminput bias current is −2.0 A which can cause an outputvoltage error that is equal to the product of the input biascurrent and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provided for externalloop compensation (Figure 29). The output voltage is offsetby two diode drops (≈1.4 V) and divided by three before itconnects to the inverting input of the Current Sense

Comparator. This guarantees that no drive pulses appear atthe Output (Pin 6) when Pin 1 is at its lowest state (VOL).This occurs when the power supply is operating and the loadis removed, or at the beginning of a soft−start interval(Figures 21, 22). The Error Amp minimum feedbackresistance is limited by the amplifier’s source current(0.5 mA) and the required output voltage (VOH) to reach thecomparator’s 1.0 V clamp level:

Rf(min) ≈3.0 (1.0 V) + 1.4 V

0.5 mA= 8800

Current Sense Comparator and PWM LatchThe UC3844B, UC3845B operate as a current mode

controller, whereby output switch conduction is initiated bythe oscillator and terminated when the peak inductor currentreaches the threshold level established by the ErrorAmplifier Output/Compensation (Pin 1). Thus the errorsignal controls the peak inductor current on acycle−by−cycle basis. The Current Sense Comparator PWMLatch configuration used ensures that only a single pulseappears at the Output during any given oscillator cycle. Theinductor current is converted to a voltage by inserting theground−referenced sense resistor RS in series with thesource of output switch Q1. This voltage is monitored by theCurrent Sense Input (Pin 3) and compared to a level derivedfrom the Error Amp Output. The peak inductor current undernormal operating conditions is controlled by the voltage atPin 1 where:

Ipk =V(Pin 1) − 1.4 V

3 RS

Abnormal operating conditions occur when the powersupply output is overloaded or if output voltage sensing islost. Under these conditions, the Current Sense Comparatorthreshold will be internally clamped to 1.0 V. Therefore themaximum peak switch current is:

Ipk(max) =1.0 V

RS

When designing a high power switching regulator itbecomes desirable to reduce the internal clamp voltage in orderto keep the power dissipation of RS to a reasonable level. Asimple method to adjust this voltage is shown in Figure 20. Thetwo external diodes are used to compensate the internal diodes,yielding a constant clamp voltage over temperature. Erraticoperation due to noise pickup can result if there is an excessivereduction of the Ipk(max) clamp voltage.

A narrow spike on the leading edge of the currentwaveform can usually be observed and may cause the powersupply to exhibit an instability when the output is lightlyloaded. This spike is due to the power transformerinterwinding capacitance and output rectifier recovery time.The addition of an RC filter on the Current Sense Input witha time constant that approximates the spike duration willusually eliminate the instability (refer to Figure 24).

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Figure 16. Representative Block Diagram

Figure 17. Timing Diagram

Capacitor CT

Latch Set" Input

Output/Compensation

Current SenseInput

Latch Reset"Input

Output

Large RT/Small CTSmall RT/Large CT

+−

ReferenceRegulator

VCCUVLO

+− Vref

UVLO3.6V

36V

S

RQ

InternalBias

+ 1.0mA

Oscillator

2.5V

R

R

R

2R

ErrorAmplifier

VoltageFeedback

Input

Output/Compensation Current Sense

Comparator

1.0V

VCC 7(12)

GND 5(9)

VC

7(11)

Output

6(10)

Power Ground

5(8)

Current Sense Input

3(5)RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

RT

CT

Vref

= Sink Only Positive True LogicPin numbers adjacent to terminals are for the 8−pin dual−in−line package.Pin numbers in parenthesis are for the D suffix SOIC−14 package.

PWMLatch

(SeeText)

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Undervoltage LockoutTwo undervoltage lockout comparators have been

incorporated to guarantee that the IC is fully functionalbefore the output stage is enabled. The positive powersupply terminal (VCC) and the reference output (Vref) areeach monitored by separate comparators. Each has built−inhysteresis to prevent erratic output behavior as theirrespective thresholds are crossed. The VCC comparatorupper and lower thresholds are 16 V/10 V for the UCX844B,and 8.4 V/7.6 V for the UCX845B. The Vref comparatorupper and lower thresholds are 3.6 V/3.4 V. The largehysteresis and low startup current of the UCX844B makesit ideally suited in off−line converter applications whereefficient bootstrap startup techniques are required(Figure 30). The UCX845B is intended for lower voltagedc−dc converter applications. A 36 V Zener is connected asa shunt regulator from VCC to ground. Its purpose is toprotect the IC from excessive voltage that can occur duringsystem startup. The minimum operating voltage for theUCX844B is 11 V and 8.2 V for the UCX845B.

OutputThese devices contain a single totem pole output stage that

was specifically designed for direct drive of powerMOSFETs. It is capable of up to ±1.0 A peak drive currentand has a typical rise and fall time of 50 ns with a 1.0 nF load.Additional internal circuitry has been added to keep theOutput in a sinking mode whenever an undervoltage lockoutis active. This characteristic eliminates the need for anexternal pulldown resistor.

The SOIC−14 surface mount package provides separatepins for VC (output supply) and Power Ground. Properimplementation will significantly reduce the level ofswitching transient noise imposed on the control circuitry.This becomes particularly useful when reducing the Ipk(max)clamp level. The separate VC supply input allows the

designer added flexibility in tailoring the drive voltageindependent of VCC. A Zener clamp is typically connectedto this input when driving power MOSFETs in systemswhere VCC is greater than 20 V. Figure 23 shows properpower and control ground connections in a current−sensingpower MOSFET application.

ReferenceThe 5.0 V bandgap reference is trimmed to ±1.0%

tolerance at TJ = 25°C on the UC284XB, and ±2.0% on theUC384XB. Its primary purpose is to supply charging currentto the oscillator timing capacitor. The reference hasshort−circuit protection and is capable of providing inexcess of 20 mA for powering additional control systemcircuitry.

Design ConsiderationsDo not attempt to construct the converter on

wire−wrap or plug−in prototype boards. High frequencycircuit layout techniques are imperative to preventpulse−width jitter. This is usually caused by excessive noisepick−up imposed on the Current Sense or Voltage Feedbackinputs. Noise immunity can be improved by lowering circuitimpedances at these points. The printed circuit layout shouldcontain a ground plane with low−current signal andhigh−current switch and output grounds returning onseparate paths back to the input filter capacitor. Ceramicbypass capacitors (0.1 F) connected directly to VCC, VC,and Vref may be required depending upon circuit layout.This provides a low impedance path for filtering the highfrequency noise. All high current loops should be kept asshort as possible using heavy copper runs to minimizeradiated EMI. The Error Amp compensation circuitry andthe converter output voltage divider should be located closeto the IC and as far as possible from the power switch andother noise−generating components.

Bias

+

Osc

R

R

R

2R

EA

5(9)

1(1)

2(3)

4(7)

8(14)

RT

CT

Vref

Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp andMulti−Unit Synchronization

0.01

The diode clamp is required if the Sync amplitude is large enough to causethe bottom side of CT to go more than 300 mV below ground.

ExternalSyncInput

47

+

R

R

R

2R

Bias

Osc

EA

5(9)

1(1)

2(3)

4(7)

8(14)

To AdditionalUCX84XBs

R

SQ

8 4

6

5

2

1

C

3

7

RA

RB5.0k

5.0k

5.0kMC1455

f 1.44(RA 2RB)C

D(max) RARA 2RB

UC3844B, UC3845B, UC2844B, UC2845B

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If: SENSEFET = MTP10N10MRS = 200

Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit

Figure 22. Adjustable Buffered Reduction of Clamp Level with Soft−Start

+−

5.0V Ref

+−

S

RQ

Bias

+

Osc

R

R

R2R

EA

1.0V

5(9)

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

R1

VClampR2

Ipk(max) VClamp

RS

Where: 0 ≤ VClamp ≤ 1.0 V

5.0V Ref

+−

S

RQ

Bias

+

1.0mA

Osc

R

R

R2R

EA

1.0V

5(9)

1(1)

2(3)

4(7)

8(14)

C

1.0M

tSoft−Start ≈ 3600C in F

+−

+−

S

R

+

R

R

R2R

Ipk(max) VClamp

RS

Figure 23. Current Sensing Power MOSFET

5.0V Ref

Q

Bias

Osc

EA

1.0V

5(9)

7(11)

6(10)

5(8)

3(5)RS

Q1

VCC Vin

1(1)

2(3)

4(7)

8(14)

R1

R2

Where: 0 ≤ VClamp ≤ 1.0 V

MPSA63

+−

5.0V Ref

+−

S

RQ

(11)

(10)

(8)

Comp/Latch

(5) RS1/4 W

VCC Vin

K

M

D SENSEFET

GS

Power Ground:To Input Source

Return

Control Circuitry Ground:To Pin (9)

Virtually lossless current sensing can be achieved with the implementationof a SENSEFET power switch. For proper operation during over−currentconditions, a reduction of the Ipk(max) clamp level must be implemented.Refer to Figures 20 and 22.

VPin5 RSIpkrDS(on)

rDM(on) RS

Then : VPin5 0.075Ipk

7(12)

7(12)

1.0 mA

Comp/Latch

Comp/Latch

1.0 mA

(12)

T

T

T TVClamp

VClamp ≈1.67

R2R1

1 + 0.33x10−3 R1R2R1 R2

VClamp ≈1.67

R2R1

1

tSoft-Start In1 VC

3VClampC R1R2

R1 R2

UC3844B, UC3845B, UC2844B, UC2845B

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Figure 24. Current Waveform Spike Suppression

+−

5.0V Ref

+

−

S

RQ

7(11)

6(10)

5(8)

3(5)

RS

Q1

VCC Vin

C

R

The addition of the RC filter will eliminateinstability caused by the leading edge spike on the current waveform.

7(12)

Comp/Latch

T

Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive

+−

S

R

5.0V Ref

Q

7(11)

6(10)

5(8)

3(5) RS

Q1

VCC Vin

Series gate resistor Rg will damp any high frequencyparasitic oscillations caused by the MOSFET inputcapacitance and any series wiring inductance in thegate−source circuit.

6(10)

5(8)

3(5) RS

Q1

Vin

C1

Base ChargeRemoval

The totem pole output can furnish negative base currentfor enhanced transistor turn−off, with the addition ofcapacitor C1.

IB

+

−

0

7(12)

Rg

Comp/Latch

T

+

−

UC3844B, UC3845B, UC2844B, UC2845B

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+

R

2R1.0mA

EA

2(3)

5(9)

2.5V

1(1)

RfCfRd

Rp

From VO

Error Amp compensation circuit for stabilizing current mode boostand flyback topologies operating with continuous inductor current.

Cp

Ri

Figure 27. Isolated MOSFET Drive

Figure 28. Latched Shutdown

Figure 29. Error Amplifier Compensation

+−

S

R

5.0V Ref

Q

7(11)

6(10)

5(8)

3(5)

RS

Q1

VCC Vin

IsolationBoundary

VGS Waveforms

+

−

0

50% DC 25% DC

NSNp

Bias

+

Osc

R

R

R

2R

EA

5(9)

1(1)

2(3)

4(7)

8(14)

The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). Thesimple two transistor circuit can be used in place of the SCR as shown. Allresistors are 10 k.

MCR101

2N3905

2N3903

+

R

2R1.0mA

EA

2(3)

5(9)

2.5V

1(1)

RfCfRd

Ri

From VO

Error Amp compensation circuit for stabilizing any current mode topology exceptfor boost and flyback converters operating with continuous inductor current.

Rf ≥ 8.8k

Comp/Latch

7(12)

R

C NSNP

1.0 mA

T

+

−0

+

−

Ipk =V(Pin1) − 1.4

3 RS

UC3844B, UC3845B, UC2844B, UC2845B

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MUR110

+−

+−

S

R

+

R

R

5.0V Ref

Q

Bias

EA

5(9)

7(11)

6(10)

5(8)

3(5)0.5

MTP4N50

1(1)

2(3)

4(7)

8(14)

33k

1.0nF

470pF

150k100pF

18k

4.7k

Figure 30. 7 W Off−Line Flyback Regulator

0.01

100

+

1.0k

115 Vac

4.7MDA202

250

56k

4.7k 3300pF

1N4935 1N4935

+ +68

47

1N4937

1N4937680pF 2.7k

L3

L2

L1

+ +

+ +

+ +

1000

1000

2200

10

10

1000

5.0V/4.0A

5.0V RTN

12V/0.3A

±12V RTN

−12V/0.3A

Primary: 45 Turns #26 AWGSecondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar WoundSecondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar WoundSecondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar WoundCore: Ferroxcube EC35−3C8Bobbin: Ferroxcube EC35PCB1Gap: ≈ 0.10" for a primary inductance of 1.0 mH

MUR110

MBR1635

T1

22Osc

T1 −

7(12)

Comp/Latch

T

L1L2, L3

− 15 H at 5.0 A, Coilcraft Z7156− 25 H at 5.0 A, Coilcraft Z7157

1N5819

Test Conditions Results

Line Regulation: 5.0 V±12 V

Vin = 95 Vac to 130 Vac = 50 mV or ±0.5% = 24 mV or ±0.1%

Load Regulation: 5.0 V±12 V

Vin = 115 Vac, Iout = 1.0 A to 4.0 AVin = 115 Vac, Iout = 100 mA to 300 mA

= 300 mV or ±3.0% = 60 mV or ±0.25%

Output Ripple: 5.0 V±12 V

Vin = 115 Vac 40 mVpp80 mVpp

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents unless otherwise noted.

UC3844B, UC3845B, UC2844B, UC2845B

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Osc

+−

ReferenceRegulator

+−

34V

S

RQ

InternalBias

+

0.5mA

Osc

R

R

R

2R

ErrorAmplifier

1.0V

7(12)

7(11)

6(10)

5(8)

3(5)

R1

Vin = 15V

1(1)

2(3)

4(7)

8(14)

10k

1.0nF

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistormay be required when using tantalum or other low ESR capacitors. The converter’s output can provide excellent lineand load regulation by connecting the R2/R1 resistor divider as shown.

Figure 31. Step−Up Charge Pump Converter

5(9)

PWM

T

Latch

Current SenseComparator

2.5V

3.6V

VCC

UVLO

Vref

UVLO

UC3845B+

47

1N5819

15 101N5819

+47

R2Connect toPin 2 forclosed loopoperation.

R2R1

1

VO ≈ 2 (Vin)

Output Load Regulation(Open Loop Configuration)

IO (mA) VO (V)

0291836

29.928.828.327.424.4

+−

+−

S

R

+

R

R

R

2R

5(9)

PWM

T

Latch

Current SenseComparator

+47

15 101N5819

+47

ReferenceRegulator

34V

Q

InternalBias

0.5mA

ErrorAmplifier

1.0V

7(12)

7(11)

6(10)

5(8)

3(5)

Vin = 15V

1(1)

2(3)

4(7)

8(14)

10k

1.0nF

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.An additional series resistor may be required when using tantalum or other low ESR capacitors.

Figure 32. Voltage−Inverting Charge Pump Converter

2.5V

3.6V

VCC

UVLO

Vref

UVLO

UC3845B

VO ≈ −Vin

Output Load Regulation

IO (mA) VO (V)

0291832

−14.4−13.2−12.5−11.7−10.6

1N5819

+

VO = 2.5

UC3844B, UC3845B, UC2844B, UC2845B

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x = 4 or 5F = Wafer FabA = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work Week

SOIC−14D SUFFIX

CASE 751A

MARKING DIAGRAMS

UC384xBDAWLYWW

14

1

UC384xBN AWL YYWW

PDIP−8N SUFFIXCASE 626

1

8

384xBALYW

SOIC−8D1 SUFFIXCASE 751

1

8

UC384xBVDAWLYWW

14

1

384xBALYWV

1

8

UC3844BVN AWL YYWW

1

8

UC284xBDAWLYWW

14

1

284xBALYW

1

8

UC2844BN FAWL YYWW

1

8

UC3845BVN FAWL YYWW

1

8

UC3844B, UC3845B, UC2844B, UC2845B

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PACKAGE DIMENSIONS

PDIP−8N SUFFIX

CASE 626−05ISSUE L

NOTES:1. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.2. PACKAGE CONTOUR OPTIONAL (ROUND OR

SQUARE CORNERS).3. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

1 4

58

F

NOTE 2 −A−

−B−

−T−SEATING

PLANE

H

J

G

D K

N

C

L

M

MAM0.13 (0.005) B MT

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.40 10.16 0.370 0.400B 6.10 6.60 0.240 0.260C 3.94 4.45 0.155 0.175D 0.38 0.51 0.015 0.020F 1.02 1.78 0.040 0.070G 2.54 BSC 0.100 BSCH 0.76 1.27 0.030 0.050J 0.20 0.30 0.008 0.012K 2.92 3.43 0.115 0.135

L 7.62 BSC 0.300 BSCM −−− 10 −−− 10 N 0.76 1.01 0.030 0.040

UC3844B, UC3845B, UC2844B, UC2845B

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PACKAGE DIMENSIONS

SOIC−8D1 SUFFIX

CASE 751−07ISSUE AC

SEATINGPLANE

1

4

58

N

J

X 45

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

mminches

SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

UC3844B, UC3845B, UC2844B, UC2845B

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PACKAGE DIMENSIONS

SOIC−14D SUFFIX

CASE 751A−03ISSUE G

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.127(0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIALCONDITION.

−A−

−B−

G

P 7 PL

14 8

71

M0.25 (0.010) B M

SBM0.25 (0.010) A ST

−T−

FR X 45

SEATINGPLANE

D 14 PL K

C

JM

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019

UC3844B, UC3845B, UC2844B, UC2845B

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATIONN. American Technical Support : 800−282−9855 Toll FreeUSA/Canada

Japan : ON Semiconductor, Japan Customer Focus Center2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051Phone : 81−3−5773−3850

UC3844B/D

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

LITERATURE FULFILLMENT :Literature Distribution Center for ON SemiconductorP.O. Box 61312, Phoenix, Arizona 85082−1312 USAPhone : 480−829−7710 or 800−344−3860 Toll Free USA/CanadaFax: 480−829−7709 or 800−344−3867 Toll Free USA/CanadaEmail : [email protected]

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Documents

High Performance Current Mode Controllers · 2013. 6. 27. · Current Mode Controllers The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They