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Prepared:OELPW Anders ÅhlanderApproved:
Checked:
Date:2015-02-08Confidentiality Class:COMPANY UNCLASSIFIED
Document Number:enRevision:PA1Document Name:
High Performance EmbeddedComputing
Challenges in long lifetime applications
Chalmers Computing Lab Tech TalksFebruary 8 2015
COMPANY UNCLASSIFIED
Page 2 (33)PAGE 2PAGE 2ELECTRONIC DEFENCE SYSTEMSPAGE 2
ELECTRONIC DEFENCE SYSTEMS
SURFACE RADARSYSTEMS
FUTURE SENSORSYSTEMS
AIRBORNESURVEILLANCE
SYSTEMS
SOURCING &PRODUCTION
EW SYSTEMS
SeniorVice
President
Stafffunctions
COMPANY UNCLASSIFIED
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World-leading centre of competence for microwave andantenna technology. Advanced airborne, ground-based andnaval radar systems as well as radar upgrade expertise.
Full range of assets in the Electronic Warfare area, forsignals intelligence, warning and self-protection.
MSEK 2013 2012 2011
Order intake 7,620 2,739 3,229Sales 4,161 4,276 4,561No employees 2,588 2,620 2,557
MSEK 2013 2012 2011
Order intake 7,620 2,739 3,229Sales 4,161 4,276 4,561No employees 2,588 2,620 2,557
KEY CAPABILITIESAND FIGURES
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GLOBAL OPERATIONS
Competence centres in five countries.
Systems in operation in more than 30 countries.
Key markets: Sweden, Germany, UK, US, Brazil, Middle East,India, Thailand, South Korea.
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Outline
Long-lifetime HPEC applications• Particular challenges• Aspects of cost-effective application development
Exploiting the processing technology development
Possibilities to obtain cost-efficiency• Previous and ongoing “FoT” projects
An ongoing project: ESCHER
Summary
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Active Electronically Scanned Array
Performance
Time
before AESA after AESA
GFLOPS
TFLOPS
Cost:High demands on signal processorHigh complexity
en
Example: AESA based sensor systems
Benefit:Powerful system operation
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Processing challenges
AESA SP performance in the same “box”as for conventional systems, considering• Physical size• Power dissipation• Physical robustness
Cost-effective development of the processing• Engineering efficiency; mastering complexity• Flexibility; easy and efficient enabling of various options• Sustainability; application support over many years of lifetime
Contradictory?
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Engineering efficiency
Mastering complexity• high computational load – high parallelism• multi-functional – complex resource management and scheduling
The aggregated complexity scales differently with the system• More channels ->
- same complexity on algorithm level (only larger matrices)- more complexity in realization (more processors)
• More functions/new algorithms ->- more complex control and interactions
Technology improvement may make it possible to trade hardwareperformance for reduced development time• use higher levels of abstraction
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Flexibility
Possibility to enable software options for differentproducts or for different users• different functions• different types and number of sensors• efficient testing and deployment of the systems
Possibility to configure the system for the mission at hand
Capability to meet changing demands on the fly
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Sustainability
Technology insertion• Possible to upgrade the SW and refresh the
HW over lifetime
Scalability• Easy to scale up or down functionality/performance in order to tolerate
different hardware implementations of the system• Easy to “ride on Moore´s law”
Layered application development• A modern, sustainable codebase• A clear separation of hardware features from the application requirement
is made
General-purpose vs. special-purpose hardware• Certain functions can be implemented in acceleration hardware as long
as there is a clear path (and a clean interface) to replace the hardwarewhen it becomes obsolete
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Desired platform properties
Possible to
Take advantage of the rapid technology development to shortenthe application development timeDecouple system SW from the HW implementationMultiple implementation options for any given applicationA simple way to replace or add hardware modulesLayered development of application SW and support for re-use ofSW componentsScalability in terms of problem size as well as technologydevelopment
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How to combine• high processing efficiency with• high engineering efficiency?
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Generality-performance trade-off
COTS
custom
time
enoughgenerality
for applicationdomain
architectureadvantage
performancegaintime lead
performance
generality
scales withtechnologydevelopment
Combine the best of two worlds- performance, engineering efficiency
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high performance
The application domain
linear operations
MM FIR FFTdataset
multi-functional
high complexity
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Technology development
The International Technology Roadmap for Semiconductors (ITRS)
• Includes time-lines up to about 15 years into the future
• ITRS is sponsored by- the European Semiconductor Industry Association- the Japan Electronics and Information Technology
Industries Association- the Korean Semiconductor Industry Association- the Taiwan Semiconductor Industry Association- the United States Semiconductor Industry Association
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ITRS market drivers
ITRS identifies different market drivers for the technologydevelopment
Portable/consumer, Medical, Defense, Automotive, etc.
The market drivers drive the development of, e.g., microprocessorsand System-on-a-chip (SoC) devices
Portable/consumer market driver is chosen here• High power efficiency is paramount in HPEC
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Number of processing cores on a chip
Suits luckily typically our applications well
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Trend according to ITRS
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Performance trend
0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
Year
log(
norm
aliz
edpe
rform
ance
)
Trend: Performance Requirement: Performance
Soc Consumer Portable Processing Performance Trends (source ITRS)
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Power trend
0
2
4
6
8
10
12
14
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
Year
Pow
er(W
att)
Trend: Total chip power Requirement: Total chip power
Soc Consumer Portable total power trend (source ITRS)
Total power = static power (gate leakage etc.) + dynamic power (switching)
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Performance/power ratio trend
0
5
10
15
20
25
30
35
40
45
50
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
Year
Norm
aliz
edra
tio
Trend: Performance/power ratio
Consumer Portable performance per power trend, normalized to 2009
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Sensor signal processing
0
5
10
15
20
25
30
35
40
45
50
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
Year
Nor
mal
ized
ratio
Trend: Performance/power ratio
32 channels
1 channel
short-term long-term
Illustration, requirements on SP power efficiency vs. HW trend
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Energy efficiency
Different aspects of energy efficiency
Larger high-end systems• Many watts of available power but very high
computational performance• E.g. multi-channel adaptive processing in AESA based systems
Small handheld systems• Short range - low transmit power, thus more focus on
SP power• Often high frequency - many resolution cells, thus hiigh
SP performance• Battery powered
en
(illustration)
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How to exploit the technology development
The processor chips goes towards many-core (100+ cores)
How shall we efficiently use all the cores?• Application programming• Mapping on the processor architecture
Joint industry/academy research projectsaddress this
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Research projects
en
1995 2014
REMAP HSSP EEE
TELLUSSPREWS
national/international joint industry/academic projects
EDA projects2009 2014
TELLUS 2
SMECY ESCHEREPC JUMP
… and others
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ERTCENS
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High Speed Signal ProcessingExample of project result
en
• Mainly COTS Application development environment• Commercial RTOS• ANSI C• In-house algorithmic library
• A TFLOPS system realization proposal• Five BYB601 cassettes• LSI Logic G13 ASICs with commercial RISC masters• LVDS ring network, 1.6 GB/s data channel + control
channel• Realizable in year 2001
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An ongoing project: ESCHER
Embedded Streaming Computations onHeterogeneous Energy-efficient aRchitectures
KK-foundation HÖG project, 2014-2016Lead: CERES at Halmstad University
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Processing eras
Single-Core Era
Enabled by:+Moore’s Law+Voltage Scaling+Micro Architecture/RISC
Constrained by:– Power– Complexity
Time
we arehere
Sin
gle
thre
adpe
rform
ance
27
Multi-Core Era
Enabled by:+Moore’s Law+Desire for throughput+20 years of SMP
Constrained by:– Power– Parallel SW available– Scalability
Time (# processors)
we arehere
Thro
ughp
utpe
rform
ance
Many-Core/Heterogeneous
Systems EraEnabled by:
+Power efficiency throughhigh parallelism+Moore’s Law
Currently Constrained by:– Power– Programming models– Communication overhead
Time
we arehere
Targ
eted
appl
icat
ion
perfo
rman
ce
Assembler => C => C++/Java pthreads => OpenMP/TBB ... OpenCL/CUDA, StreamIt, CAL,Occam-Pi, Chapel, ZPL,...
Inspired by "The Future Is Heterogeneous Computing",Mike Houston, Advanced Micro Devices, 2010
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ESCHER
Two main parts:
Application Development support and Languages forHeterogeneous Manycore Architectures
Heterogeneous Many-core Architectures for Real-TimeEmbedded Streaming Systems
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Embedded Real-Time StreamingComputations
The Applications of the Industrial Partners are often in the form ofEmbedded Streaming Applications like:
Sensor systems
Autonomous Vehicles
Vision/Video
Communication
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ESCHER
Maximize the “four Ps”• Programmer Productivity• Program Portability• Performance• Power efficiency
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Applications
ScientificComputing
Streaming Real-time Processing
Data Mining
Machine Learning
Architectures
Many-core
GPGPU
Course-grainedReconfig. Arch.
FPGA
Programmability
Inspired by Kevin J. Brown, et al.,“A Heterogeneous Parallel Framework for Domain-Specific Languages”,PACT 2011
Parallel Programming Language
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Applications
ScientificComputing
Streaming Real-time Processing
Data Mining
Machine Learning
Architectures
Many-core
GPGPU
Course-grainedReconfig. Arch.
FPGA
Programmability Chasm
Inspired by Kevin J. Brown, et al.,“A Heterogeneous Parallel Framework for Domain-Specific Languages”,PACT 2011
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Applications
ScientificEngineering
Streaming Real-time Processing
Data Mining
Machine Learning
Architectures
Many-Core
GPGPU
Course-grainedReconfig. Arch.
FPGA
How to bridge theProgrammability Chasm?
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Saab EDS in ESCHER
Brings in expertise• Signal and data processing• HW and SW development for sensor processing
Provides application use casesEvaluates the developed design environments
Goals: get knowledge if the studied development approaches willoutperform traditional approaches in aspects such as engineeringefficiency, performance, and powerA concrete goal: a proof of concept realization of an AESA signalprocessing chain using the design tool flows on real hardware
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Summary
High performance efficiency and high engineering efficiency musttypically be combined in HPECTypically a lifetime mismatch between SP technology and sensorapplicationsPossibilities• Cost-effective sustainable solutions are possible• Possible to ride on Moore’s law – scale in problem size and function
Risks• Applications are not portable to new hardware platforms
Solutions• Layered application development• Domain specific languages with the right abstraction level• Intermediate representations that support portability over hardware• HW architecture that is “general enough”
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