High speed board layout guidelines

8/14/2019 High speed board layout guidelines

1/32

Altera Corporation 111

May 2007

11. High-Speed Board LayoutGuidelines

Introduction Printed circuit board (PCB) layout becomes more complex as device pindensity and system frequency increase. A successful high-speed boardmust effectively integrate devices and other elements while avoidingsignal transmission problems associated with high-speed I/O standards.

Because Altera devices include a variety of high-speed features,including fast I/O pins and edge rates less than one hundredpicoseconds, it is imperative that an effective design successfully:

Reduces system noise by filtering and evenly distributing power toall devices

Matches impedance and terminates the signal line to diminish signalreflection

Minimizes crosstalk between parallel traces Reduces the effects of ground bounce

This chapter provides guidelines for effective high-speed board designusing Altera devices and discusses the following issues:

PCB material selection Transmission line layouts Routing schemes for minimizing crosstalk and maintaining signal

integrity

Termination schemes Simultaneous switching noise (SSN) Electromagnetic interference (EMI) Additional FPGA-specific board design/signal integrity information

PCB Material

Selection

Fast edge rates contribute to noise and crosstalk, depending on the PCBdielectric construction material. Dielectric material can be assigned a

dielectric constant ( r) that is related to the force of attraction betweentwo opposite charges separated by a distance in a uniform medium asfollows:

F =Q1Q2

4r2

SII52012-1.4


2/32

112 Altera Corporation

Stratix II Device Handbook, Volume 2 May 2007

PCB Material Selection

where:

Q1, Q2 = chargesr = distance between the charges (m)F = force (N)

= permittivity of dielectric (F/m).

Each PCB substrate has a different relative dielectric constant. Thedielectric constant is the ratio of the permittivity of a substance to that of

free space, as follows:

where:

r = dielectric constant

o = permittivity of empty space (F/m)

= permittivity (F/m)

The dielectric constant compares the effect of an insulator on thecapacitance of a conductor pair, with the capacitance of the conductorpair in a vacuum. The dielectric constant affects the impedance of atransmission line. Signals can propagate faster in materials that have alower dielectric constant.

A high-frequency signal that propagates through a long line on the PCBfrom driver to receiver is severely affected by the loss tangent of thedielectric material. A large loss tangent means higher dielectricabsorption.

The most widely used dielectric material for PCBs is FR-4, a glasslaminate with epoxy resin that meets a wide variety of processingconditions. The dielectric constant for FR-4 is between 4.1 and 4.5. GETEKis another material that can be used in high-speed boards. GETEK iscomposed of epoxy and resin (polyphenylene oxide) and has a dielectric

constantbetween 3.6 and 4.2.

r=


3/32


May 2007 Stratix II Device Handbook, Volume 2

High-Speed Board Layout Guidelines

Table 111 shows the loss tangent value for FR-4 and GETEK materials.

Transmission

Line Layout

The transmission line is a trace and has a distributed mixture ofresistance (R), inductance (L), and capacitance (C). There are two types oftransmission line layouts, microstrip and stripline.

Figure 111 shows a microstrip transmission line layout, which refers toa trace routed as the top or bottom layer of a PCB and has one

voltage-reference plane (power or ground). Figure 112 shows a striplinetransmission line layout, which uses a trace routed on the inside layer ofa PCB and has two voltage-reference planes (power and/or ground).

Figure 111. Microstrip Transmission Line Layout Note (1)

Note toFigure 111:(1) W= width of trace, T= thickness of trace, andH= height between trace and

reference plane.

Figure 112. Stripline Transmission Line Layout Note (1)

Note toFigure 112:(1) W= width of trace, T= thickness of trace, andH= height between trace and two

reference planes.

Table 111. Loss Tangent Value of FR-4 & GETEK Materials

Manufacturer Material Loss Tangent Value

GE Electromaterials GETEK 0.010 @ 1 MHz

Isola Laminate Systems FR-4 0.019 @ 1 MHz

W

Dialectric Material

Power/GND

Trace

H

T

W

DielectricMaterial

Power/Ground

H Trace

Power/Ground

T


4/32



Transmission Line Layout

Impedance Calculation

Any circuit trace on the PCB has characteristic impedance associated withit. This impedance is dependent on the width (W) of the trace, thethickness (T) of the trace, the dielectric constant of the material used, andthe height (H) between the trace and reference plane.

Microstrip Impedance

A circuit trace routed on an outside layer of the PCB with a referenceplane (GND or VCC) below it, constitutes a microstrip layout. Use the

following microstrip impedance equation to calculate the impedance of amicrostrip trace layout:

Using typical values of W= 8 mil,H= 5 mil, T= 1.4 mil, the dielectricconstant, and (FR-4) = 4.1, with the microstrip impedance equation,solving for microstrip impedance (Zo) yields:

1 The measurement unit in the microstrip impedance equation ismils (i.e., 1 mil = 0.001 inches). Also, copper (Cu) trace thickness

is usually measured in ounces for example, 1 oz = 1.4 mil).

Figure 113 shows microstrip trace impedance with changing trace width(W), using the values in the microstrip impedance equation, keepingdielectric height and trace thickness constant.

Z0 =87

r + 1.41ln ( )

5.98 H

0.8W+ T

Z0 =

Z0 ~

87

4.1 + 1.41

ln ( )5.98 (5)

0.8(8) + 1.4

50


5/32




Figure 113. Microstrip Trace Impedance with Changing Trace Width

Figure 114 shows microstrip trace impedance with changing height,using the values in the microstrip impedance equation, keeping tracewidth and trace thickness constant.

Figure 114. Microstrip Trace Impedance with Changing Height

The impedance graphs show that the change in impedance is inverselyproportional to trace width and directly proportional to trace heightabove the ground plane.

80

70

60

50

40

30

20

10

0

4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9

Z0

W(mil)

Z0() T= 1.4 milsH= 5.0 mils

80

70

60

50

40

30

20

10

0

4 5 6 7 8 9

H(mil)

Z0()

10

Z0

T= 1.4 mils

W= 8.0 mils


6/32




Figure 115 plots microstrip trace impedance with changing tracethickness using the values in the microstrip impedance equation, keepingtrace width and dielectric height constant. Figure 115 shows that as tracethickness increases, trace impedance decreases.

Figure 115. Microstrip Trace Impedance with Changing Trace Thickness

Stripline Impedance

A circuit trace routed on the inside layer of the PCB with two low-voltagereference planes (power and/or GND) constitutes a stripline layout. Youcan use the following stripline impedance equation to calculate the

impedance of a stripline trace layout:

Using typical values of W= 9 mil,H= 24 mil, T= 1.4 mil, dielectricconstant and (FR-4) = 4.1 with the stripline impedance equation andsolving for stripline impedance (Zo) yields:

Figure 116 shows impedance with changing trace width using thestripline impedance equation, keeping height and thickness constant forstripline trace.

60

50

40

30

20

10

0

0.7 1.4 2.8 4.2

T (mil)

Z0 ()

Z0

H= 5.0 milsW= 8.0 mils

Zo =60

r

ln ( )4H

0.67 (T+ 0.8W)

Zo=60

4.1ln ( )4 (24) 0.67 (1.4) + 0.8(9)

Zo ~ 50


7/32




Figure 116. Stripline Trace Impedance with Changing Trace Width

Figure 117 shows stripline trace impedance with changing dielectricheight using the stripline impedance equation, keeping trace width andtrace thickness constant.

Figure 117. Stripline Trace Impedance with Changing Dielectric Height

As with the microstrip layout, the stripline layout impedance alsochanges inversely proportional to line width and directly proportional toheight. However, the rate of change with trace height above GND is muchslower in a stripline layout compared with a microstrip layout. A striplinelayout has a signal sandwiched by FR-4 material, whereas a microstriplayout has one conductor open to air. This exposure causes a highereffective dielectric constant in stripline layouts compared with microstrip

80

70

60

50

40

30

20

10

0

4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9

W(mil)

Z0 ()

10

Z0

T= 1.4 mils

H= 24.0 mils

80

70

60

50

40

30

20

10

0

16 20 24 28 32 36

H(mil)

Z0 ()

40 44

Z0

T= 1.4 mils

W= 9.0 mils


8/32




layouts. Thus, to achieve the same impedance, the dielectric span must begreater in stripline layouts compared with microstrip layouts. Therefore,stripline-layout PCBs with controlled impedance lines are thicker thanmicrostrip-layout PCBs.

Figure 118 shows stripline trace impedance with changing tracethickness, using the stripline impedance equation, keeping trace widthand dielectric height constant. Figure 118 shows that the characteristicimpedance decreases as the trace thickness increases.

Figure 118. Stripline Trace Impedance with Changing Trace Thickness

Propagation DelayPropagation delay (tPD) is the time required for a signal to travel from one

point to another. Transmission line propagation delay is a function of thedielectric constant of the material.

Microstrip LayoutPropagationDelay

You can use the following equation to calculate the microstrip trace layoutpropagation delay:

Stripline LayoutPropagationDelay

You can use the following equation to calculate the stripline trace layoutpropagation delay.

60

50

40

30

20

10

0

0.7 1.4 2.8 4.2

T (mil)

Z0 ()

Z0

H= 24.0 milsW= 9.0 mils

tPD (microstrip) = 0.475r+ 0.6785

tPD (stripline) = r85


9/32




Figure 119 shows the propagation delay versus the dielectric constantfor microstrip and stripline traces. As the dielectric constant increases, thepropagation delay also increases.

Figure 119. Propagation Delay Versus Dielectric Constant for Microstrip & Stripline Traces

Pre-Emphasis

Typical transmission media like copper trace and coaxial cable havelow-pass characteristics, so they attenuate higher frequencies more thanlower frequencies. A typical digital signal that approximates a squarewave contains high frequencies near the switching region and lowfrequencies in the constant region. When this signal travels throughlow-pass media, its higher frequencies are attenuated more than thelower frequencies, resulting in increased signal rise times. Consequently,the eye opening narrows and the probability of error increases.

The high-frequency content of a signal is also degraded by what is calledthe skin effect. The cause of skin effect is the high-frequency currentthat flows primarily on the surface (skin) of a conductor. The changingcurrent distribution causes the resistance to increase as a function offrequency.

You can use pre-emphasis to compensate for the skin effect. By Fourier

analysis, a square wave signal contains an infinite number of frequencies.The high frequencies are located in the low-to-high and high-to-lowtransition regions and the low frequencies are located in the flat (constant)regions. Increasing the signals amplitude near the transition regionemphasizes higher frequencies more than the lower frequencies. Whenthis pre-emphasized signal passes through low-pass media, it will comeout with minimal distortion, if you apply the correct amount ofpre-emphasis (see Figure 1110).

300

250

200

150

100

50

0

1 2 3 4 5 6 7 8 9

r

tPD (ps/inch)

Microstrip

StriplineT= 1.4

Z0 = 50

Wstripline = 9.0 mils

Wmicrostrip = 8.0 mils


10/32




Figure 1110. Input & Output Signals with & without Pre-Emphasis

|H (jw)|

1

W

Signal is attenuatedat high frequencies.

Transmission Line

Output Vo(t)Input Vi (t)

Vi(t) Vo(t)

Input signal approximatesa square wave but has nopre-emphasis.

Output signal has higher rise time,and the eye opening is smaller.

Input signal has pre-emphasis.

Vi(t) Vo(t)

Output signal has similar risetime and eye opening as inputsignal.

t

t

t

t


11/32




Stratix II and Stratix GX devices provide programmable pre-emphasis tocompensate for variable lengths of transmission media. You can set thepre-emphasis to between 5 and 25%, depending on the value of theoutput differential voltage (VOD) in the Stratix GX device. Table 112

shows the available Stratix GX programmable pre-emphasis settings.

RoutingSchemes for

Minimizing

Crosstalk &

Maintaining

Signal Integrity

Crosstalk is the unwanted coupling of signals between parallel traces.Proper routing and layer stack-up through microstrip and striplinelayouts can minimize crosstalk.

To reduce crosstalk in dual-stripline layouts that have two signal layersnext to each other, route all traces perpendicular, increase the distancebetween the two signal layers, and minimize the distance between thesignal layer and the adjacent reference plane (see Figure 1111).

Table 112. Programmable Pre-Emphasis with Stratix GX Devices

VODPre-emphasis Setting (%)

5 10 15 20 25

400 420 440 460 480 500

480 504 528 552 576 600

600 630 660 690 720 750

800 840 880 920 960 1,000

960 1,008 1,056 1,104 1,152 1,200

1,000 1,050 1,100 1,150 1,200 1,250

1,200 1,260 1,320 1,380 1,440 1,500

1,400 1,470 1,540 - - -

1,440 1,512 1,584 - - -

1,500 1,575 - - - -

1,600 - - - - -


12/32



Routing Schemes for Minimizing Crosstalk & Maintaining Signal Integrity

Figure 1111. Dual- and Single-Stripline Layouts

Take the following actions to reduce crosstalk in either microstrip orstripline layouts:

Widen spacing between signal lines as much as routing restrictionswill allow. Try not to bring traces closer than three times the dielectricheight.

Design the transmission line so that the conductor is as close to theground plane as possible. This technique will couple thetransmission line tightly to the ground plane and help decouple itfrom adjacent signals.

Use differential routing techniques where possible, especially forcritical nets (i.e., match the lengths as well as the turns that each tracegoes through).

If there is significant coupling, route single-ended signals ondifferent layers orthogonal to each other. Minimize parallel run lengths between single-ended signals. Route

with short parallel sections and minimize long, coupled sectionsbetween nets.

Crosstalk also increases when two or more single-ended traces runparallel and are not spaced far enough apart. The distance between thecenters of two adjacent traces should be at least four times the trace width,as shown in Figure 1112. To improve design performance, lower thedistance between the trace and the ground plane to under 10 mils withoutchanging the separation between the two traces.

WW

DielectricMaterial

Ground

Ground

HTrace

Single-Stripline Layout Dual-Stripline Layout


13/32




Figure 1112. Separating Traces for Crosstalk

Compared with high dielectric materials, low dielectric materials helpreduce the thickness between the trace and ground plane whilemaintaining signal integrity. Figure 1113 plots the relationship of heightversus dielectric constant using the microstrip impedance and striplineimpedance equations, keeping impedance, width, and thicknessconstant.

Figure 1113. Height Versus Dielectric Constant

Signal Trace Routing

Proper routing helps to maintain signal integrity. To route a clean trace,you should perform simulation with good signal integrity tools. Thefollowing section describes the two different types of signal tracesavailable for routing, single-ended traces, and differential pair traces.

A

4A

A

30

25

20

15

10

5

0

2.2 2.9 3.3 4.1 4.5

r

H (mil)

Microstrip

StriplineT= 1.4Z0 = 50 Wstripline = 9.0 milsWmicrostrip = 8.0 mils


14/32




Single-Ended Trace Routing

A single-ended trace connects the source and the load/receiver.Single-ended traces are used in general point-to-point routing, clockrouting, low-speed, and non-critical I/O routing. This section discussesdifferent routing schemes for clock signals. You can use the followingtypes of routing to drive multiple devices with the same clock:

Daisy chain routing With stub Without stub

Star routing Serpentine routing

Use the following guidelines to improve the clock transmission linessignal integrity:

Keep clock traces as straight as possible. Use arc-shaped tracesinstead of right-angle bends.

Do not use multiple signal layers for clock signals. Do not use vias in clock transmission lines. Vias can cause impedance

change and reflection. Place a ground plane next to the outer layer to minimize noise. If you

use an inner layer to route the clock trace, sandwich the layerbetween reference planes.

Terminate clock signals to minimize reflection. Use point-to-point clock traces as much as possible.

Daisy Chain Routing With StubsDaisy chain routing is a common practice in designing PCBs. Onedisadvantage of daisy chain routing is that stubs, or short traces, areusually necessary to connect devices to the main bus (see Figure 1114). Ifa stub is too long, it will induce transmission line reflections and degradesignal quality. Therefore, the stub length should not exceed the followingconditions:

TDstub < (T10% to 90%)/3

where TDstub = Electrical delay of the stub

T10% to 90% = Rise or fall time of signal edge

For a 1-ns rise-time edge, the stub length should be less than 0.5 inches(see the References section). If your design uses multiple devices, allstub lengths should be equal to minimize clock skew.


15/32




1 If possible, you should avoid using stubs in your PCB design.For high-speed designs, even very short stubs can create signalintegrity problems.

Figure 1114. Daisy Chain Routing with Stubs

Figures 1115 through 1117 show the SPICE simulation with differentstub length. As the stub length decreases, there is less reflection noise,which causes the eye opening to increase.

Figure 1115. Stub Length = 0.5 Inch

Figure 1116. Stub Length = 0.25 Inch

Device 1 Device 2

ClockSource

Main Bus

Stub

TerminationResistor

DevicePin(BGA Ball)


16/32




Figure 1117. Stub Length = Zero Inches

Daisy Chain Routing without StubsFigure 1118 shows daisy chain routing with the main bus runningthrough the device pins, eliminating stubs. This layout removes the riskof impedance mismatch between the main bus and the stubs, minimizing

signal integrity problems.

Figure 1118. Daisy Chain Routing without Stubs

Star RoutingIn star routing, the clock signal travels to all the devices at the same time(see Figure 1119). Therefore, all trace lengths between the clock sourceand devices must be matched to minimize the clock skew. Each loadshould be identical to minimize signal integrity problems. In star routing,you must match the impedance of the main bus with the impedance of thelong trace that connects to multiple devices.

Device 1 Device 2

ClockSource

TerminationResistor

Main Bus

DevicePin(BGA Ball)


17/32




Figure 1119. Star Routing

Serpentine Routing

When a design requires equal-length traces between the source andmultiple loads, you can bend some traces to match trace lengths (seeFigure 1120). However, improper trace bending affects signal integrity

and propagation delay. To minimize crosstalk, ensure that S3 H,where S is the spacing between the parallel sections andHis the height ofthe signal trace above the reference ground plane (see Figure 1121).

Device 1

ClockSource

Main Bus

Device 2

TerminationResistor

Device 3

DevicePin(BGA Ball)


18/32




Figure 1120. Serpentine Routing

1 Altera recommends avoiding serpentine routing, if possible.Instead, use arcs to create equal-length traces.

Differential Trace Routing

To maximize signal integrity, proper routing techniques for differentialsignals are important for high-speed designs. Figure 1121 shows twodifferential pairs using the microstrip layout.

Figure 1121. Differential Trace Routing Note (1)

Note toFigure 1121:

(1) D = distance between two differential pair signals; W= width of a trace in a differential pair; S = distance betweenthe trace in a differential pair; andH= dielectric height above the group plane.

Use the following guidelines when using two differential pairs:

Keep the distance between the differential traces (S) constant overthe entire trace length.

ClockSourceTermination

Resistor

TerminationResistor

S

Device 1

Device 2

W W D

S

W W

S

Dielectric Material

GND

H


19/32




Ensure that D > 2S to minimize the crosstalk between the twodifferential pairs.

Place the differential traces S = 3Has they leave the device tominimize reflection noise.

Keep the length of the two differential traces the same to minimize

the skew and phase difference. Avoid using multiple vias because they can cause impedance

mismatch and inductance.

Termination

Schemes

Mismatched impedance causes signals to reflect back and forth along thelines, which causes ringing at the load receiver. The ringing reduces thedynamic range of the receiver and can cause false triggering. To eliminatereflections, the impedance of the source (ZS) must equal the impedance of

the trace (Zo), as well as the impedance of the load (ZL). This section

discusses the following signal termination schemes:

Simple parallel termination Thevenin parallel termination Active parallel termination Series-RC parallel termination Series termination Differential pair termination

Simple Parallel Termination

In a simple parallel termination scheme, the termination resistor (RT) is

equal to the line impedance. Place the RT as close to the load as possible

to be efficient (see Figure 1122).

Figure 1122. Simple Parallel Termination

The stub length from the RT to the receiver pin and pads should be as

small as possible. A long stub length causes reflections from the receiverpads, resulting in signal degradation. If your design requires a longtermination line between the terminator and receiver, the placement ofthe resistor becomes important. For long termination line lengths, usefly-by termination (see Figure 1123).

Zo = 50

RT = Zo

S L

Stub

S= SourceL = Load


20/32



Termination Schemes

Figure 1123. Simple Parallel Fly-By Termination

Thevenin Parallel Termination

An alternative parallel termination scheme uses a Thevenin voltagedivider (see Figure 1124). The RT is split between R1 and R2, which equals

the line impedance when combined.

Figure 1124. Thevenin Parallel Termination

As noted in the previous section, stub length is dependent on signal riseand fall time and should be kept to a minimum. If your design requires along termination line between the terminator and receiver, use fly-bytermination or Thevenin fly-by termination (see Figures 1123 and1125).

Zo = 50

RT = Zo

Receiver / Load

Pad

Source

Zo= 50

R2

R1

R1 R2 = Zo

S L

VCC

Stub


21/32




Figure 1125. Thevenin Parallel Fly-By Termination

Active Parallel Termination

Figure 1126 shows an active parallel termination scheme, where theterminating resistor (RT = Zo) is tied to a bias voltage (VBIAS). In this

scheme, the voltage is selected so that the output drivers can draw currentfrom the high- and low-level signals. However, this scheme requires aseparate voltage source that can sink and source currents to match theoutput transfer rates.

Figure 1126. Active Parallel Termination

Zo = 50

R2

R1

VCC

Receiver/Load

PadSource

Zo = 50

RT = Zo

S L

VBIAS

Stub


22/32



Termination Schemes

Figure 1127 shows the active parallel fly-by termination scheme.

Figure 1127. Active Parallel Fly-By Termination

Series-RC Parallel Termination

A series-RC parallel termination scheme uses a resistor and capacitor(series-RC) network as the terminating impedance. RT is equal to Z0. The

capacitor must be large enough to filter the constant flow of DC current.For data patterns with long strings of 1 or 0, this termination scheme maydelay the signal beyond the design thresholds, depending on the size ofthe capacitor.

Capacitors smaller than 100 pF diminish the effectiveness of termination.The capacitor blocks low-frequency signals while passing high-frequencysignals. Therefore, the DC loading effect of RT does not have an impact on

the driver, as there is no DC path to ground. The series-RC terminationscheme requires balanced DC signaling, the signals spend half the timeon and half the time off. AC termination is typically used if there is morethan one load (see Figure 1128).

Figure 1128. Series-RC Parallel Termination

Zo = 50

RT = Zo

VBIAS

Receiver/Load

Pad

Source

Zo= 50

RT = Zo

C

S L

Stub


23/32




Figure 1129 shows series-RC parallel fly-by termination.

Figure 1129. Series-RC Parallel Fly-By Termination

Series Termination

In a series termination scheme, the resistor matches the impedance at thesignal source instead of matching the impedance at each load (seeFigure 1130). Stratix II devices have programmable output impedance.You can choose output impedance to match the line impedance withoutadding an external series resistor. The sum of RT and the impedance of the

output driver should be equal to Z0. Because Altera device output

impedance is low, you should add a series resistor to match the signalsource to the line impedance. The advantage of series termination is thatit consumes little power. However, the disadvantage is that the rise time

degrades because of the increased RC time constant. Therefore, forhigh-speed designs, you should perform the pre-layout signal integritysimulation with Altera I/O buffer information specification (IBIS) modelsbefore using the series termination scheme.

Figure 1130. Series Termination

Differential Pair Termination

Differential signal I/O standards require an RTbetween the signals at the

receiving device (see Figure 1131). For the low-voltage differential signal(LVDS) and low-voltage positive emitter-coupled logic (LVPECL)standard, the RT should match the differential load impedance of the bus

(typically 100 ).

Zo = 50 S

Receiver/

Load

RT = Zo

C

Pad

Z0 = 50

RT

S L


24/32



Simultaneous Switching Noise

Figure 1131. Differential Pair (LVDS & LVPECL) Termination

Figure 1132shows the differential pair fly-by termination scheme for theLVDS and LVPECL standard.

Figure 1132. Differential Pair (LVDS & LVPECL) Fly-By Termination

f See the Board Design Guidelines for LVDS Systems White Paper for moreinformation on terminating differential signals.

Simultaneous

Switching Noise

As digital devices become faster, their output switching times decrease.This causes higher transient currents in outputs as the devices dischargeload capacitances. These higher transient currents result in a board-levelphenomenon known as ground bounce.

Because many factors contribute to ground bounce, you cannot use astandard test method to predict its magnitude for all possible PCBenvironments. You can only test the device under a given set ofconditions to determine the relative contributions of each condition andof the device itself. Load capacitance, socket inductance, and the numberof switching outputs are the predominant factors that influence themagnitude of ground bounce in FPGAs.

Altera requires 0.01- to 0.1-F surface-mount capacitors in parallel toreduce ground bounce. Add an additional 0.001-F capacitor in parallelto these capacitors to filter high-frequency noise (>100 MHz). You canalso add 0.0047-F and 0.047-F capacitors.

Z0 = 50

Z0 = 50

100 S L

Stub

Stub

Z0 = 50

Z0 = 50

100 S Pads

Receiver/Load

+


25/32




Altera recommends that you take the following action to reduce groundbounce and VCC sag:

Configure unused I/O pins as output pins, and drive the output lowto reduce ground bounce. This configuration will act as a virtual

ground. Connect the output pin to GND on your board. Configure the unused I/O pins as output, and drive high to prevent

VCC sag. Connect the output pin to VCCIO of that I/O bank.

Create a programmable ground or VCC next to switching pins.

Reduce the number of outputs that can switch simultaneously anddistribute them evenly throughout the device.

Manually assign ground pins in between I/O pins. (Separating I/Opins with ground pins prevents ground bounce.)

Set the programmable drive strength feature with a weaker drivestrength setting to slow down the edge rate.

Eliminate sockets whenever possible. Sockets have inductanceassociated with them.

Depending on the problem, move switching outputs close to either apackage ground or VCC pin. Eliminate pull-up resistors, or usepull-down resistors.

Use multi-layer PCBs that provide separate VCC and ground planes

to utilize the intrinsic capacitance of the VCC /GND plane.

Create synchronous designs that are not affected by momentarilyswitching pins.

Add the recommended decoupling capacitors to VCC/GND pairs.

Place the decoupling capacitors as close as possible to the power andground pins of the device.

Connect the capacitor pad to the power and ground plane with

larger vias to minimize the inductance in decoupling capacitors andallow for maximum current flow.

Use wide, short traces between the vias and capacitor pads, or placethe via adjacent to the capacitor pad (see Figure 1133).

Figure 1133. Suggested Via Location that Connects to Capacitor Pad

Via Adjacentto Capacitor Pad

Via

CapacitorPads

Wide andShort Trace


26/32



Simultaneous Switching Noise

Traces stretching from power pins to a power plane (or island, or adecoupling capacitor) should be as wide and as short as possible.This reduces series inductance, thereby reducing transient voltagedrops from the power plane to the power pin which, in turn,decreases the possibility of ground bounce.

Use surface-mount low effective series resistance (ESR) capacitors tominimize the lead inductance. The capacitors should have an ESRvalue as small as possible.

Connect each ground pin or via to the ground plane individually. Adaisy chain connection to the ground pins shares the ground path,which increases the return current loop and thus inductance.

Power Filtering & Distribution

You can reduce system noise by providing clean, evenly distributedpower to VCC on all boards and devices. This section describes techniques

for distributing and filtering power.

Filtering Noise

To decrease the low-frequency (< 1 kHz) noise caused by the powersupply, filter the noise on power lines at the point where the powerconnects to the PCB and to each device. Place a 100-F electrolyticcapacitor where the power supply lines enter the PCB. If you use avoltage regulator, place the capacitor immediately after the pin thatprovides the VCC signal to the device(s). Capacitors not only filterlow-frequency noise from the power supply, but also supply extra currentwhen many outputs switch simultaneously in a circuit.

To filter power supply noise, use a non-resonant, surface-mount ferritebead large enough to handle the current in series with the power supply.Place a 10- to 100-F bypass capacitor next to the ferrite bead (seeFigure 1134). (If proper termination, layout, and filtering eliminateenough noise, you do not need to use a ferrite bead.) The ferrite bead actsas a short for high-frequency noise coming from the VCC source. Any

low-frequency noise is filtered by a large 10-F capacitor after the ferritebead.


27/32




Figure 1134. Filtering Noise with a Ferrite Bead

Usually, elements on the PCB add high-frequency noise to the powerplane. To filter the high-frequency noise at the device, place decouplingcapacitors as close as possible to each VCC and GND pair.

f See the Operating Requirements for Altera Devices Data Sheet for moreinformation on bypass capacitors.

PowerDistribution

A system can distribute power throughout the PCB with either powerplanes or a power bus network.

You can use power planes on multi-layer PCBs that consist of two or moremetal layers that carry VCC and GND to the devices. Because the power

plane covers the full area of the PCB, its DC resistance is very low. Thepower plane maintains VCC and distributes it equally to all devices while

providing very high current-sink capability, noise protection, and

shielding for the logic signals on the PCB. Altera recommends usingpower planes to distribute power.

The power bus networkwhich consists of two or more wide-metaltraces that carry VCC and GND to devicesis often used on two-layer

PCBs and is less expensive than power planes. When designing withpower bus networks, be sure to keep the trace widths as wide as possible.The main drawback to using power bus networks is significant DCresistance.

Altera recommends using separate analog and digital power planes. Forfully digital systems that do not already have a separate analog powerplane, it can be expensive to add new power planes. However, you cancreate partitioned islands (split planes). Figure 1135 shows an exampleboard layout with phase-locked loop (PLL) ground islands.

VCC Source Ferrite Bead VCC

10 F


28/32



Electromagnetic Interference (EMI)

Figure 1135. Board Layout for General-Purpose PLL Ground Islands

If your system shares the same plane between analog and digital powersupplies, there may be unwanted interaction between the two circuittypes. The following suggestions will reduce noise:

For equal power distribution, use separate power planes for theanalog (PLL) power supply. Avoid using trace or multiple signal

layers to route the PLL power supply. Use a ground plane next to the PLL power supply plane to reduce

power-generated noise. Place analog and digital components only over their respective

ground planes. Use ferrite beads to isolate the PLL power supply from digital power

supply.

Electromagnetic

Interference

(EMI)

Electromagnetic interference (EMI) is directly proportional to the changein current or voltage with respect to time. EMI is also directlyproportional to the series inductance of the circuit. Every PCB generatesEMI. Precautions such as minimizing crosstalk, proper grounding, andproper layer stack-up significantly reduce EMI problems.

Place each signal layer in between the ground plane and power (orground) plane. Inductance is directly proportional to the distance anelectric charge has to cover from the source of an electric charge toground. As the distance gets shorter, the inductance becomes smaller.

Power andgroundgapwidth atleast

25to 100milsAltera Device

AnalogGroundPlane

CommonGroundArea

DigitalGroundPlane

PCB


29/32




Therefore, placing ground planes close to a signal source reducesinductance and helps contain EMI. Figure 1136 shows an example of aneight-layer stack-up. In the stack-up, the stripline signal layers are thequietest because they are centered by power and GND planes. A solidground plane next to the power plane creates a set of low ESR capacitors.

With integrated circuit edge rates becoming faster and faster, thesetechniques help to contain EMI.

Figure 1136. Example Eight-Layer Stack-Up

Component selection and proper placement on the board is important tocontrolling EMI.

The following guidelines can reduce EMI:

Select low-inductance components, such as surface mount capacitorswith low ESR, and effective series inductance.

Use proper grounding for the shortest current return path.

Use solid ground planes next to power planes. In unavoidable circumstances, use respective ground planes next to

each segmented power plane for analog and digital circuits.

Additional

FPGA-Specific

Information

This section provides the following additional informationrecommended by Altera for board design and signal integrity:FPGA-specific configuration, Joint Test Action Group (JTAG) testing, andpermanent test points.

Configuration

The DCLK signal is used in configuration devices and passive serial (PS)and passive parallel synchronous (PPS) configuration schemes. Thissignal drives edge-triggered pins in Altera devices. Therefore, anyovershoot, undershoot, ringing, crosstalk, or other noise can affectconfiguration. Use the same guidelines for designing clock signals to

Signal

Ground

Ground

Ground

Signal

Signal

Signal

Power


30/32



Summary

route the DCLK trace (see the Signal Trace Routingsection). If yourdesign uses more than five configuration devices, Altera recommendsusing buffers to split the fan-out on the DCLK signal.

JTAG

As PCBs become more complex, testing becomes increasingly important.Advances in surface mount packaging and PCB manufacturing haveresulted in smaller boards, making traditional test methods such asexternal test probes and bed-of-nails test fixtures harder to implement.As a result, cost savings from PCB space reductions can be offset by costincreases in traditional testing methods.

In addition to boundary scan testing (BST), you can use the IEEEStd. 1149.1 controller for in-system programming. JTAG consists of fourrequired pins, test data input (TDI), test data output (TDO), test modeselect (TMS), and test clock input (TCK) as well as an optional test resetinput (TRST) pin.

Use the same guidelines for laying out clock signals to route TCK traces.Use multiple devices for long JTAG scan chains. Minimize the JTAG scanchain trace length that connects one devices TDOpins to another devicesTDI pins to reduce delay.

f SeeApplication Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing inAltera Devices for additional details on BST.

Test PointAs device package pin density increases, it becomes more difficult toattach an oscilloscope or a logic analyzer probe on the device pin. Usinga physical probe directly on to the device pin can damage the device. If

the ball grid array (BGA) or FineLine BGA package is mounted on topof the board, it is difficult to probe the other side of the board. Therefore,the PCB must have a permanent test point to probe. The test point can bea via that connects to the signal under test with a very short stub.However, placing a via on a trace for a signal under test can causereflection and poor signal integrity.

Summary You must carefully plan out a successful high-speed PCB. Factors such asnoise generation, signal reflection, crosstalk, and ground bounce caninterfere with a signal, especially with the high speeds that Altera devicestransmit and receive. The signal routing, termination schemes, and powerdistribution techniques discussed in this chapter contribute to a moreeffectively designed PCB using high-speed Altera devices.


31/32




References Johnson, H. W., and Graham, M., High-Speed Digital Design. PrenticeHall, 1993.

Hall, S. H., Hall, G. W., and McCall J. A., High-Speed Digital SystemDesign. John Wiley & Sons, Inc. 2000.

Document

Revision History

Table 113 shows the revision history for this chapter.

Table 113. Document Revision History

Date and

Document

Version

Changes Made Summary of Changes

May 2007, v1.4 Updated Simultaneous Switching Noise section.

Moved the Document Revision History section to

the end of the chapter.

December 2005,

v1.3

Minor content update.

March 2005, v1.2 Minor content updates.

January 2005,

v1.1

This chapter was formally chapter 12.

February 2004,v1.0

Added document to the Stratix II DeviceHandbook.


32/32

Document Revision History

Documents

High speed board layout guidelines