High-Speed CMOS Data - OoCities

DL129/DRev. 7, Mar-2000

ON Semiconductor

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High-Speed CMOS Data

03/00DL129REV 7

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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DL129/D

High–Speed CMOS Data

DL129/DRev. 7, Mar–2000

SCILLC, 2000Previous Edition 1996“All Rights reserved”

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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Table of Contents

Chapter 1. Function Selector GuideAlphanumeric Index 6. . . . . . . . . . . . . . . . . . . . . . . . . Buffers/Inverters 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gates 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schmitt Triggers 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Transceivers 12. . . . . . . . . . . . . . . . . . . . . . . . . . . Latches 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip–Flops 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Data Selectors/Multiplexers 16. . . . . . . . . . . . . Decoders/Demultiplexers/Display Drivers 17. . . . . . . Analog Switches/Multiplexers/Demultiplexers 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Registers 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counters 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2. Design ConsiderationsIntroduction 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precautions 24. . . . . . . . . . . . . . . . . . . . . . . . Power Supply Sizing 28. . . . . . . . . . . . . . . . . . . . . . . . .

Battery Systems 28. . . . . . . . . . . . . . . . . . . . . . . . . . CPD Power Calculation 29. . . . . . . . . . . . . . . . . . .

Inputs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–State Outputs 35. . . . . . . . . . . . . . . . . . . . . . . . . . Open–Drain Outputs 35. . . . . . . . . . . . . . . . . . . . . . Input/Output Pins 35. . . . . . . . . . . . . . . . . . . . . . . . . Bus Termination 36. . . . . . . . . . . . . . . . . . . . . . . . . . Transmission Line Termination 37. . . . . . . . . . . . .

CMOS Latch Up 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Power Dissipation 40. . . . . . . . . . . . . . . . . .

HC Quiescent Power Dissipation 40. . . . . . . . . . . HCT Quiescent Power Dissipation 40. . . . . . . . . . HC and HCT Dynamic Power Dissipation 40. . . .

Thermal Management 41. . . . . . . . . . . . . . . . . . . . . . . Capacitive Loading Effects onPropagation Delay 43. . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Effects on DC and ACParameters 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Effects on Drive Currentand Propagation Delay 44. . . . . . . . . . . . . . . . . . . . . . . Decoupling Capacitors 45. . . . . . . . . . . . . . . . . . . . . . . Interfacing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Parametric Values 48. . . . . . . . . . . . . . . . . . . . Reduction of ElectromagneticInterference (EMI) 49. . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Circuit Guidelines 49. . . . . . . . . . . . . . . . . . . . . Schmitt–Trigger Devices 50. . . . . . . . . . . . . . . . . . . . . Oscillator Design with High–Speed CMOS 51. . . . . .

RC Oscillators 51. . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillators 51. . . . . . . . . . . . . . . . . . . . . . . .

Printed Circuit Board Layout 52. . . . . . . . . . . . . . . . . . Definitions and Glossary of Terms 53. . . . . . . . . . .

HC vs. HCT 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary of Terms 53. . . . . . . . . . . . . . . . . . . . . . . .

Applications Assistance Form 56. . . . . . . . . . . . . .

Chapter 3. Device Datasheets57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4. Application Notes381. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 5. Ordering InformationDevice Nomenclature 398. . . . . . . . . . . . . . . . . . . . . . . Case Outlines 398. . . . . . . . . . . . . . . . . . . . . . . . . . . . ON Semiconductor Major WorldwideSales Offices 405. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Definitions 406. . . . . . . . . . . . . . . . . . . . . .

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CHAPTER 1Function Selector Guide

Alphanumeric Index 6. . . . . . . . . . . . . . . . . . . . . . . . . Buffers/Inverters 8. . . . . . . . . . . . . . . . . . . . . . . . . . . Gates 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schmitt Triggers 12. . . . . . . . . . . . . . . . . . . . . . . . . . Bus Transceivers 12. . . . . . . . . . . . . . . . . . . . . . . . . Latches 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip–Flops 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Data Selectors/Multiplexers 16. . . . . . . . . . Decoders/Demultiplexers/Display Drivers 17. . . . Analog Switches/Multiplexers/Demultiplexers 18. . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Registers 20. . . . . . . . . . . . . . . . . . . . . . . . . . . Counters 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous 22. . . . . . . . . . . . . . . . . . . . . . . . . . . .

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ALPHANUMERIC INDEX

Device Number FunctionPage

Number

MC74HC00A Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58MC74HC02A Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62MC74HC03A Quad 2–Input NAND Gate With Open–Drain Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66MC74HC04A Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70MC74HCT04A Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74MC74HCU04A Hex Unbuffered Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78MC74HC08A Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83MC74HC14A Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87MC74HCT14A Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92MC74HC32A Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95MC74HC74A Dual D Flip–Flop With Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99MC74HCT74A Dual D Flip–Flop With Set and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104MC74HC86A Quad 2–Input Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108MC74HC125A Quad With 3–State Outputs Non–Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112MC74HC126A Quad With 3–State Outputs Non–Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112MC74HC132A Quad 2–Input NAND Gate With Schmitt Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116MC74HC138A 1–of–8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120MC74HCT138A 1–of–8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125MC74HC139A Dual 1–of–4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130MC74HC157A Quad 2–Input Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134MC74HC161A Presettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139MC74HC163A Presettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139MC74HC164A 8–Bit Serial–Input/Parallel–Output Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151MC74HC165A 8–Bit Serial or Parallel–Input/Serial–Output Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 157MC74HC174A Hex D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165MC74HC175A Quad D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169MC74HC240A Octal With 3–State Outputs Inverting Buffer/Line Driver/line Receiver . . . . . . . . . . . . . . . . . 175MC74HC244A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 180MC74HCT244A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 185MC74HC245A Octal With 3–State Outputs Non–Inverting Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 189MC74HCT245A Octal With 3–State Outputs Non–Inverting Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 194MC74HC273A Octal D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199MC74HCT273A Octal D Flip–Flop With Common Clock & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204MC74HC373A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 208MC74HCT373A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 214MC74HC374A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220MC74HCT374A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225MC74HC390A Dual 4–Stage Binary Ripple Counter W ÷2, ÷5 Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230MC74HC393A Dual 4–Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236MC74HC540A Octal With 3–State Outputs Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . . . . . . 242MC74HC541A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 246MC74HCT541A Octal With 3–State Outputs Non–Inverting Buffer/Line Driver/Line Receiver . . . . . . . . . . . 250MC74HC573A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 254MC74HCT573A Octal With 3–State Outputs Non–Inverting Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . 260MC74HC574A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265MC74HCT574A Octal With 3–State Outputs Non–Inverting D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271MC74HC589A 8–Bit Serial or Parallel–Input/Serial–Output Shift Register With 3–State Outputs . . . . . . . 276MC74HC595A 8–Bit Serial–Input/Serial or Parallel–Output Shift Register With Latched 3–State Outputs 285MC74HC4020A 14–Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293MC74HC4040A 12–Stage Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299MC74HC4046A Phase–Locked–Loop With VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

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ALPHANUMERIC INDEX

Device NumberPage

NumberFunction

MC74HC4051A 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319MC74HC4052A Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319MC74HC4053A Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319MC74HC4060A 14–Stage Binary Ripple Counter With Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332MC74HC4066A Quad Analog Switch/Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341MC74HC4316A Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/

Digital Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350MC74HC4538A Dual Precision Monostable Multivibrator Retriggerable, Resettable) . . . . . . . . . . . . . . . . . . 360MC74HC4851A Analog Multiplexer/Demultiplexer with Injection Current Effect Control . . . . . . . . . . . . . . . . 371MC74HC4852A Analog Multiplexer/Demultiplexer with Injection Current Effect Control . . . . . . . . . . . . . . . . 371

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BUFFERS/INVERTERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumber

MC74

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Function

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

FunctionalEquivalent

LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX


Direct PinCompatibility

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Numberof

Pins

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

HC04AHCT04AHCU04AHC14A

HCT14A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Hex InverterHex Inverter with LSTTL–Compatible InputsHex Unbuffered InverterHex Schmitt–Trigger InverterHex Schmitt–Trigger Inverter with LSTTL–Compatible

Inputs


LS04LS04LS04LS14LS14


*4069*4069406945844584


LS/CMOSLS/CMOSLS/CMOSLS/CMOSLS/CMOS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1414141414

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

HC125AHC126AHC240A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Quad 3–State Noninverting BufferQuad 3–State Noninverting BufferOctal 3–State Inverting Buffer/Line Driver/Line Receiver


LS125,LS125ALS126,LS126A

LS240



LSLSLS

ÎÎÎÎÎÎÎÎÎÎÎÎ

141420


HC244A

HCT244A

HC245AHCT245A


Octal 3–State Noninverting Buffer/Line Driver/LineReceiver

Octal 3–State Noninverting Buffer/Line Driver/LineReceiver with LSTTL–Compatible Inputs

Octal 3–State Noninverting Bus TransceiverOctal 3–State Noninverting Bus Transceiver with

LSTTL–Compatible Inputs


LS244

LS244

LS245LS245



LS

LS

LSLS


20

20

2020

ÎÎÎÎÎÎÎÎÎÎ

HC540A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Octal 3–State Inverting Buffer/Line Driver/Line Receiver ÎÎÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎ

20ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

HC541A

HCT541A


Octal 3–State Noninverting Buffer/Line Driver/LineReceiver

Octal 3–State Noninverting Buffer/Line Driver/LineReceiver with LSTTL–Compatible Inputs


LS541

LS541



LS

LS


20

20

HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device

ÎÎÎÎÎÎÎÎÎ

HCHCT04A

ÎÎÎÎÎÎÎÎÎ

HCU04A


HC14A

ÎÎÎÎÎÎÎÎÎ

HC125A

ÎÎÎÎÎÎÎÎÎ

HC126A


HC240A

ÎÎÎÎÎÎÎÎÎ

HCHCT244A

ÎÎÎÎÎÎÎÎÎ

HCHCT245A


# Pins ÎÎÎÎÎÎ

14ÎÎÎÎÎÎ

14ÎÎÎÎÎÎÎÎ

14 ÎÎÎÎÎÎ

14ÎÎÎÎÎÎ

14ÎÎÎÎÎÎÎÎ

20 ÎÎÎÎÎÎ

20ÎÎÎÎÎÎ

20


Quad DeviceHex DeviceOctal DeviceNine–Wide Device



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ







Noninverting OutputsInverting Outputs

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


Single Stage (unbuffered) ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchmitt Trigger ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




3–State OutputsOpen–Drain OutputsCommon Output EnablesActive–Low Output EnablesActive–High Output EnablesSeparate 4–Bit SectionsSeparate 2–Bit and 4–Bit Sections



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ







TransceiverDirection Control

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


Logic–Level Down Converter ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



http://onsemi.com9

BUFFERS/INVERTERS (Continued)

HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device

ÎÎÎÎÎÎÎÎÎ

HC540A

ÎÎÎÎÎÎÎÎÎ

HCHCT541A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

# Pins ÎÎÎÎÎÎ

20ÎÎÎÎÎÎ

20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Quad DeviceHex DeviceOctal DeviceNine–Wide Device





ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Single Stage (unbuffered) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchmitt Trigger ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


3–State OutputsOpen–Drain OutputsCommon Output EnablesActive–Low Output Enables



http://onsemi.com10

GATESÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumber

MC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC00AHC02AHC03AHC08AHC32AHC86AHC132A


Quad 2–Input NAND GateQuad 2–Input NOR GateQuad 2–Input NAND Gate with Open–Drain OutputsQuad 2–Input AND GateQuad 2–Input OR GateQuad 2–Input Exclusive OR GateQuad 2–Input NAND Gate with Schmitt–Trigger Inputs


LS00

LS08LS32LS86LS132


40114001*40114081407140704093


LS

LSLSLSLS


14141414141414

HC Devices Have CMOS–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device

ÎÎÎÎÎÎÎÎÎ

HC00A


HC02A

ÎÎÎÎÎÎÎÎÎ

HC03A


HC08A

ÎÎÎÎÎÎÎÎÎ

HC32A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

# Pins ÎÎÎÎÎÎ

14ÎÎÎÎÎÎÎÎ

14 ÎÎÎÎÎÎ

14ÎÎÎÎÎÎÎÎ

14 ÎÎÎÎÎÎ

14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Single DeviceDual DeviceTriple DeviceQuad Device







NANDNORANDOR





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Exclusive ORExclusive NORAND–NORAND–OR





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2–Input3–Input4–Input8–Input13–Input






ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Schmitt–Trigger InputsÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Open–Drain OutputsÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

http://onsemi.com11

GATES (Continued)

HC Devices Have CMOS–Compatible Inputs.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceÎÎÎÎÎÎÎÎ

HC86AÎÎÎÎÎÎ

HC132A


# PinsÎÎÎÎÎÎÎÎ

14ÎÎÎÎÎÎ

14ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

NANDNORANDOR



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Exclusive ORExclusive NORAND–NORAND–OR


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2–Input3–Input4–Input8–Input13–Input




Schmitt–Trigger Inputs ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


Open–Drain Outputs ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

http://onsemi.com12

SCHMITT TRIGGERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC14AHCT14A

HC132A


Hex Schmitt–Trigger InverterHex Schmitt–Trigger Inverter with LSTTL–Compatible

InputsQuad 2–Input NAND Gate with Schmitt–Trigger Inputs


LS14LS14

LS132


45844584

4093


LS/CMOSLS

LS


1414

14

BUS TRANSCEIVERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC245AHCT245A


Octal 3–State Noninverting Bus TransceiverOctal 3–State Noninverting Bus Transceiver withLSTTL–Compatible Inputs


LS245LS245



LSLS

ÎÎÎÎÎÎÎÎÎ

2020

HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device


HCHCT245A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

# Pins ÎÎÎÎÎÎ

20


Quad DeviceOctal Device

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


BufferStorage Capability

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Inverting OutputsNoninverting Outputs

ÎÎÎÎÎÎÎÎÎ


Common Output EnableActive–Low Output EnableActive–High Output Enable

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDirection Control

ÎÎÎÎÎÎ

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LATCHESÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC373AHCT373A


Octal 3–State Noninverting Transparent LatchOctal 3–State Noninverting Transparent Latch with



LS373LS373



LS373LS373

ÎÎÎÎÎÎÎÎÎ

2020


HC573AHCT573A


Octal 3–State Noninverting Transparent LatchOctal 3–State Noninverting Transparent Latch with



LS373LS373



LS573LS573


2020

HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDevice


HCHCT373A

ÎÎÎÎÎÎÎÎÎ

HCHCT573AÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ# PinsÎÎÎÎÎÎÎÎ20

ÎÎÎÎÎÎ20ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Single DeviceDual DeviceOctal Device




Number of Bits Controlled by Latch Enable:28


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


TransparentAddressableReadback Capability






ÎÎÎÎÎÎÎÎÎ


Common Latch Enable, Active–Low ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


3–State OutputsCommon Output Enable, Active–Low

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

These devices are identical in function and are different in pinout only: HC/HCT373A and HC/HCT573A

http://onsemi.com14

FLIP–FLOPSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumber

MC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC74AHCT74A


Dual D Flip–Flop with Set and ResetDual D Flip–Flop with Set and Reset with



LS74,LS74ALS74,LS74A


*40134013


LSLS

ÎÎÎÎÎÎÎÎÎ

1414


HC174AHC175A


Hex D Flip–Flop with Common Clock and ResetQuad D Flip–Flop with Common Clock and Reset


LS174LS175


41744175


LS/CMOSLS/CMOS

ÎÎÎÎÎÎÎÎÎ

1616


HC273AHCT273A

HC374AHCT374A


Octal D Flip–Flop with Common Clock and ResetOctal D Flip–Flop with Common Clock and Reset with

LSTTL–Compatible InputsOctal 3–State Noninverting D Flip–FlopOctal 3–State Noninverting D Flip–Flop with



LS273LS273

LS374LS374



LSLS

LS374LS374


2020

2020


HC574AHCT574A


Octal 3–State Noninverting D Flip–FlopOctal 3–State Noninverting D Flip–Flop with



LS374LS374



ÎÎÎÎÎÎÎÎÎ

2020

*Suggested alternative

HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device


HCHCT74A


HC174A


HC175/A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ# Pins ÎÎÎÎ14 ÎÎÎÎ16 ÎÎÎ16ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎType

ÎÎÎÎÎÎÎÎD

ÎÎÎÎÎÎÎÎD

ÎÎÎÎÎÎDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Dual DeviceQuad DeviceHex DeviceOctal Device




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Common ClockNegative–Transition ClockingPositive–Transition Clocking




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Common, Active–Low Data Enables ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNoninverting OutputsInverting Outputs

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


3–State OutputsCommon, Active–Low Output Enables



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Common ResetActive–Low ResetActive–High Reset



ÎÎÎÎÎÎÎÎÎ


Active–Low SetÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ






ÎÎÎÎÎÎÎÎÎ

http://onsemi.com15

FLIP–FLOPS (Continued)

HC Devices Have CMOS–Compatible Inputs. HCT Devices Have LSTTL–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDevice


HCHCT273A


HCHCT374A

ÎÎÎÎÎÎÎÎÎ

HCHCT574A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ# Pins

ÎÎÎÎÎÎÎÎ20

ÎÎÎÎÎÎÎÎ20

ÎÎÎÎÎÎ20ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎType

ÎÎÎÎÎÎÎÎ

DÎÎÎÎÎÎÎÎ

DÎÎÎÎÎÎ

DÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Dual DeviceQuad DeviceHex DeviceOctal Device




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Common ClockNegative–Transition ClockingPositive–Transition Clocking




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCommon, Active–Low Data Enables

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ






ÎÎÎÎÎÎÎÎÎ


3–State OutputsCommon, Active–Low Output Enables



ÎÎÎÎÎÎÎÎÎ


Common ResetActive–Low ResetActive–High Reset




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎActive–Low Set ÎÎÎÎ







ÎÎÎÎÎÎÎÎÎThese devices are identical in function and are different in pinout only: HC374A and HC574A

http://onsemi.com16

DIGITAL DATA SELECTORS/MULTIPLEXERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC157AÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Quad 2–Input Noninverting Data Selector/Multiplexer ÎÎÎÎÎÎÎÎÎÎ

LS157 ÎÎÎÎÎÎÎÎÎÎ


LS ÎÎÎÎÎÎ

16


HC251HC253

HC257


8–Input Data Selector/Multiplexer with 3–State OutputsDual 4–Input Data Selector/Multiplexer with 3–State

OutputsQuad 2–Input Data Selector/Multiplexer with 3–State

Outputs


LS251LS253

LS257B


*4512 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

LSLS

LS


1616

16


HC Devices Have CMOS–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device

ÎÎÎÎÎÎÎÎÎ

HC157A


# Pins ÎÎÎÎÎÎ

16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Description ÎÎÎÎÎÎÎÎÎÎÎÎ

One oftwo 4–bitwords isselected


Single DeviceDual DeviceQuad Device

ÎÎÎÎÎÎÎÎÎ


Data Latch with Active–Low Latch Enable ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Common Address1–Bit Binary Address2–Bit Binary Address3–Bit Binary Address


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Address Latch (Transparent)Address Latch (Non–transparent)Active–Low Address Latch Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Noninverting OutputInverting Output

ÎÎÎÎÎÎ


3–State OutputsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Common Output EnableActive–High Output EnableActive–Low Output Enable


http://onsemi.com17

DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC138AHCT138A

HC139A


1–of–8 Decoder/Demultiplexer1–of–8 Decoder/Demultiplexer with LSTTL–Compatible

InputsDual 1–of–4 Decoder/Demultiplexer


LS138LS138

LS139


*4028*4028

4556


LSLS

LS/CMOS


1616

16


HC Devices Have CMOS–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device


HCHCT138A


HC139AÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ# Pins


16ÎÎÎÎÎÎÎÎ

16ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input DescriptionÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

3–Bit BinaryAddress


2–Bit BinaryAddress

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Description ÎÎÎÎÎÎÎÎÎÎ

One of 8 ÎÎÎÎÎÎÎÎ

One of 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Single DeviceDual Device




Address Input LatchActive–High Latch EnableActive–Low Latch Enable



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎActive–Low Inputs ÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎActive–Low OutputsActive–High Outputs


ÎÎÎÎÎÎÎÎ


Active–Low Output EnableActive–High Output Enable




Active–Low Reset ÎÎÎÎÎÎÎÎÎÎ



Active–Low Blanking InputActive–High Blanking Input



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎActive–Low Lamp–Test Input ÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Phase Input (for LCD’s) ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ Implies the device has two such enables

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ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC4051AHC4052AHC4053AHC4066A


8–Channel Analog Multiplexer/DemultiplexerDual 4–Channel Analog Multiplexer/DemultiplexerTriple 2–Channel Analog Multiplexer/DemultiplexerQuad Analog Switch/Multiplexer/Demultiplexer



405140524053

4066,4016


CMOSCMOSCMOSCMOS


16161614


HC4316/A

HC4851A

HC4852A


Quad Analog Switch/Multiplexer/Demultiplexer withSeparate Analog and Digital Power Supplies

Analog Multiplexer/Demultiplexer with Injection Current Effect ControlAnalog Multiplexer/Demultiplexer with Injection Current Effect Control



*4016

*4051

*4052



16

20

20

*Suggested alternative High–Speed CMOS design only

HC Devices Have CMOS–Compatible Inputs.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Device


HC4051A


HC4052A


HC4053A


HC4066A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

# Pins ÎÎÎÎÎÎÎÎÎÎ

16 ÎÎÎÎÎÎÎÎÎÎÎÎ

16 ÎÎÎÎÎÎÎÎÎÎ


14

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Description ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

A 3–Bit AddressSelects One of 8

Switches



Switches


A 3–Bit AddressSelects VaryingCombinations ofthe 6 Switches


4 IndependentlyControlledSwitches








1–to–1 Multiplexing2–to–1 Multiplexing4–to–1 Multiplexing8–to–1 Multiplexing






Active–High ON/OFF Control ÎÎÎÎÎÎÎÎÎÎ





Common Address Inputs2–Bit Binary Address3–Bit Binary Address

Address Latch with Active–Low LatchEnable





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Common Switch EnableActive–Low EnableActive–High Enable





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSeparate Analog and Control Reference

Power SuppliesÎÎÎÎÎÎÎÎÎÎ





Switched Tubs (for RON and Prop. DelayImprovement)





http://onsemi.com19

ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS (Continued)



DeviceÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

HC4316A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

HC4851A


HC4852A


# PinsÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

16ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

20ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

20ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DescriptionÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

4 IndependentlyControlled Switches

(Has a SeparateAnalog LowerPower Supply)



Switches(Has Injection Current

Protection)


A 3–Bit AddressSelects VaryingCombinations ofthe 6 Switches

(Has Injection CurrentProtection)



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




1–to–1 Multiplexing2–to–1 Multiplexing4–to–1 Multiplexing8–to–1 Multiplexing





Active–High ON/OFF Control ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Common Address Inputs2–Bit Binary Address3–Bit Binary Address

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Common Switch EnableActive–Low EnableActive–High Enable





Separate Analog and Control Reference Power SuppliesÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Switched Tubs (for RON and Prop. Delay Improvement)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎnjection Current Protection




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SHIFT REGISTERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC164AHC165A


8–Bit Serial–Input/Parallel–Output Shift Register8–Bit Serial– or Parallel–Input/Serial–Output Shift Register


LS164LS165


*4021ÎÎÎÎÎÎÎÎÎÎ

LSLS

ÎÎÎÎÎÎ

1416ÎÎÎÎÎ


HC589A

HC595A


8–Bit Serial– or Parallel–Input/Serial–Output Shift Registerwith 3–State Output

8–Bit Serial–Input/Serial– or Parallel–Output Shift Registerwith Latched 3–State Outputs





16

16



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceÎÎÎÎÎÎÎÎÎ

HC164AÎÎÎÎÎÎÎÎÎÎÎÎ

HC165AÎÎÎÎÎÎÎÎÎÎÎÎ

HC589AÎÎÎÎÎÎÎÎÎ

HC595A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

# Pins ÎÎÎÎÎÎ

14 ÎÎÎÎÎÎÎÎ

16 ÎÎÎÎÎÎÎÎ

16 ÎÎÎÎÎÎ

16


4–Bit Register8–Bit Register

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


Serial Data InputParallel Data Inputs

ÎÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Serial Output OnlyParallel OutputsInverting OutputNoninverting Output





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Serial Shift/Parallel Load ControlShifts One Direction OnlyShifts Both Directions






Positive–Transition ClockingActive–High Clock Enable

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


Input Data EnableÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Latch with Active–High Latch Clock


ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Latch with Active–High Latch Clock


ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


3–State OutputsActive–Low Output Enable

ÎÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ


Active–Low Reset ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

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COUNTERSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC161A

HC163AHC390A


Presettable 4–Bit Binary Counter with Asynchronous ResetPresettable 4–Bit Binary Counter with Synchronous ResetDual 4–Stage Binary Ripple Counter with ÷ 2 and ÷ 5

Sections


LS161,LS161A

LS161,LS161A



LS

LS


16

161616


HC393AHC4020AHC4040AHC4060A


Dual 4–Stage Binary Ripple Counter14–Stage Binary Ripple Counter12–Stage Binary Ripple Counter14–Stage Binary Ripple Counter with Oscillator


LS393ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

*4520402040404060


LSCMOSCMOSCMOS


14161616



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDevice

ÎÎÎÎÎÎ

HC161AÎÎÎÎÎÎ

HC163AÎÎÎÎÎÎ

HC390AÎÎÎÎÎÎ

HC393AÎÎÎÎÎÎÎÎ

HC4020AÎÎÎÎÎÎ

HC4040AÎÎÎÎÎÎ

HC4060AÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ# PinsÎÎÎÎÎÎ16ÎÎÎÎÎÎ16ÎÎÎÎÎÎ16ÎÎÎÎÎÎ14ÎÎÎÎÎÎÎÎ16

ÎÎÎÎÎÎ16ÎÎÎÎÎÎ16ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Single DeviceDual Device

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Ripple CounterNumber of Ripple Counter Internal StagesNumber of Stages with Available Outputs




44


44


1412


1212


1410


Count Up ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

4–Bit Binary CounterBCD CounterDecimal Counter

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ



Separate ÷ 2 SectionSeparate ÷ 5 Section

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOn–Chip Oscillator Capability ÎÎÎ




Positive–Transition ClockingNegative–Transition ClockingActive–High Clock EnableActive–Low Clock Enable









Active–High Count Enable ÎÎÎÎÎÎ

ÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎActive–High Reset ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ


4–Bit Binary Preset Data InputsBCD Preset Data InputsActive–Low Load Preset









Carry Output ÎÎÎÎÎÎ

ÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎ implies the device has two such enables

http://onsemi.com22

MISCELLANEOUS DEVICESÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DeviceNumberMC74


Function



LSTTLDevice

74



CMOSDevice

MC1XXXXor CDXXXX




Numberof

Pins


HC4046AHC4538A


Phase–Locked LoopDual Precision Monostable Multivibrator

(Retriggerable, Resettable)



40464538,4528


CMOSCMOS


1616

http://onsemi.com23

CHAPTER 2Design Considerations

Introduction 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precautions 24. . . . . . . . . . . . . . . . . . . . . . . . Power Supply Sizing 28. . . . . . . . . . . . . . . . . . . . . . . . . Inputs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOS Latch Up 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Power Dissipation 40. . . . . . . . . . . . . . . . . . Thermal Management 41. . . . . . . . . . . . . . . . . . . . . . . Capacitive Loading Effects onPropagation Delay 43. . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Effects on DC and ACParameters 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Effects on Drive Currentand Propagation Delay 44. . . . . . . . . . . . . . . . . . . . . . . Decoupling Capacitors 45. . . . . . . . . . . . . . . . . . . . . . . Interfacing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Parametric Values 48. . . . . . . . . . . . . . . . . . . . Reduction of ElectromagneticInterference (EMI) 49. . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Circuit Guidelines 49. . . . . . . . . . . . . . . . . . . . . Schmitt–Trigger Devices 50. . . . . . . . . . . . . . . . . . . . . Oscillator Design with High–Speed CMOS 51. . . . . . Printed Circuit Board Layout 52. . . . . . . . . . . . . . . . . . Definitions and Glossary of Terms 53. . . . . . . . . . . . . Applications Assistance Form 56. . . . . . . . . . . . . . . . .

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INTRODUCTION

CMOS devices have been used for many years inapplications where the primary concerns were low powerconsumption, wide power–supply range, and high noiseimmunity. However, metal–gate CMOS (MC14000 series)is too slow for many applications. Applications requiringhigh–speed devices, such as microprocessor memorydecoding, had to go to the faster families such as LSTTL.This meant sacrificing the best qualities of CMOS. The nextstep in the logic evolution was to introduce a family ofdevices that were fast enough for such applications, whileretaining the advantages of CMOS. The results of thischange can be seen in 1 where HSCMOS devices arecompared to standard (metal–gate) CMOS, LSTTL, andALS.

The ON Semiconductor CMOS evolutionary processshown in Figure 1 indicates that one advantage of thesilicon–gate process is device size. The High–Speed CMOS(HSCMOS) device is about half the size of the metal–gatepredecessor, yielding significant chip area savings. Thesilicon–gate process allows smaller gate or channel lengths

due to the self–aligning gate feature. This process uses thegate to define the channel during processing, eliminatingregistration errors and, therefore, the need for gate overlaps.The elimination of the gate overlap significantly lowers thegate capacitance, resulting in higher speed capability. Thesmaller gate length also results in higher drive capability perunit gate width, ensuring more efficient use of chip area.Immunity enhancements to electrostatic discharge (ESD)damage and latch up are ongoing. Precautions should still betaken, however, to guard against electrostatic discharge andlatch up.

ON Semiconductors’s High–Speed CMOS family has abroad range of functions from basic gates, flip–flops, andcounters to bus–compatible devices. The family is made upof devices that are identical in pinout and are functionallyequivalent to LSTTL devices, as well as the most popularmetal–gate devices not available in TTL. Thus, the designerhas an excellent alternative to existing families withouthaving to become familiar with a new set of device numbers.

METAL GATE CMOSMETALOXIDEP+ N+ P+ P+ P+N+ N+ N+

120 µm

P– N–

65 µm

POLYMETAL

PSGOXIDE

HIGH–SPEEDSILICON–GATEHSCMOS

P–

N–

N+P

P+ P+N+

N

Figure 1. CMOS Evolution

HANDLING PRECAUTIONS

High–Speed CMOS devices, like all MOS devices, havean insulated gate that is subject to voltage breakdown. Thegate oxide for HSCMOS devices breaks down at agate–source potential of about 100 volts. Some device inputsare protected by a resistor–diode network (Figure 2). Newinput protection structure deletes the poly resistor (Figure 3)Using the test setup shown in Figure 4, the inputs typicallywithstand a > 2 kV discharge.

SILICON–GATE

CMOSINPUT

∼ 150 Ω

POLY

VCC

D1 ∼ 50 Ω

D2TO CIRCUIT

GND

Figure 2. Input Protection Network

SILICON–GATE

CMOSINPUT

∼ 190 Ω

Diffused

VCC

TO CIRCUIT

VCC

Figure 3. New Input Protection Network

VCCOR

GROUND

10 M 1.5 k

HIGH VOLTAGEDC SOURCE

TO INPUTUNDER TEST

100 pF VZAP

Figure 4. Electrostatic Discharge Test Circuit

http://onsemi.com25

Table 1. Logic Family Comparisons

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

General Characteristics (1) (All Maximum Ratings)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



TTL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎ

ÎÎÎÎÎÎSymbol ÎÎÎÎ

ÎÎÎÎLS ÎÎÎÎÎÎÎÎÎÎ

ALS ÎÎÎÎÎÎÎÎÎÎ

MC14000ÎÎÎÎÎÎÎÎÎÎ

Hi–SpeedÎÎÎÎÎÎ

Unit


Operating Voltage Range ÎÎÎÎÎÎÎÎÎÎÎÎ

VCC/EE/DD ÎÎÎÎÎÎÎÎ

5 ± 5%ÎÎÎÎÎÎÎÎÎÎ

5 ± 5% ÎÎÎÎÎÎÎÎÎÎ

3.0 to 18ÎÎÎÎÎÎÎÎÎÎ

2.0 to 6.0ÎÎÎÎÎÎ

V


Operating Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎ

TA ÎÎÎÎÎÎÎÎ

0 to + 70ÎÎÎÎÎÎÎÎÎÎ

0 to + 70ÎÎÎÎÎÎÎÎÎÎ

– 40 to + 85ÎÎÎÎÎÎÎÎÎÎ

– 55 to + 125ÎÎÎÎÎÎ

C


Input Voltage (limits) ÎÎÎÎÎÎÎÎÎÎÎÎ

VIH min ÎÎÎÎÎÎÎÎ

2.0 ÎÎÎÎÎÎÎÎÎÎ



3.54 ÎÎÎÎÎÎ

V



VIL max ÎÎÎÎÎÎÎÎ




1.04 ÎÎÎÎÎÎ

V


Output Voltage (limits) ÎÎÎÎÎÎÎÎÎÎÎÎ

VOH min ÎÎÎÎÎÎÎÎ



VDD – 0.05ÎÎÎÎÎÎÎÎÎÎ

VCC – 0.1ÎÎÎÎÎÎ

V



VOL max ÎÎÎÎÎÎÎÎ




0.1 ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎÎÎIINH ÎÎÎÎ20 ÎÎÎÎÎ20 ÎÎÎÎÎ± 0 3 ÎÎÎÎÎ± 1 0 ÎÎÎµAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎIINL

ÎÎÎÎÎÎÎÎ– 400

ÎÎÎÎÎÎÎÎÎÎ– 200


± 0.3 ÎÎÎÎÎÎÎÎÎÎ

± 1.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Output Current @ VO (limit)unless otherwise specified


IOHÎÎÎÎÎÎÎÎÎÎÎÎ

– 0.4ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

– 0.4ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

– 2.1 @ 2.5 VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

– 4.0 @VCC – 0.8 V

ÎÎÎÎÎÎÎÎÎ

mA



IOL ÎÎÎÎÎÎÎÎ



0.44 @ 0.4 VÎÎÎÎÎÎÎÎÎÎ

4.0 @ 0.4 VÎÎÎÎÎÎ

mA


DC Noise Margin Low/High ÎÎÎÎÎÎÎÎÎÎÎÎ

DCM ÎÎÎÎÎÎÎÎ

0.3/0.7ÎÎÎÎÎÎÎÎÎÎ

0.3/0.7 ÎÎÎÎÎÎÎÎÎÎ


0.90/1.354ÎÎÎÎÎÎ

V


DC Fanout ÎÎÎÎÎÎÎÎÎÎÎÎ

— ÎÎÎÎÎÎÎÎ



50(1)2 ÎÎÎÎÎÎÎÎÎÎ

50(10)2 ÎÎÎÎÎÎ

—


Speed/Power Characteristics (1) (All Typical Ratings)




TTL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎ

ÎÎÎÎÎÎSymbol ÎÎÎÎ

ÎÎÎÎLS ÎÎÎÎÎÎÎÎÎÎ

ALS ÎÎÎÎÎÎÎÎÎÎ



Unit


Quiescent Supply Current/Gate ÎÎÎÎÎÎÎÎÎÎÎÎ

IG ÎÎÎÎÎÎÎÎ




0.0005 ÎÎÎÎÎÎ

mA


Power/Gate (Quiescent) ÎÎÎÎÎÎÎÎÎÎÎÎ

PG ÎÎÎÎÎÎÎÎ




0.001 ÎÎÎÎÎÎ

mW


Propagation Delay ÎÎÎÎÎÎÎÎÎÎÎÎ

tp ÎÎÎÎÎÎÎÎ




8.0 ÎÎÎÎÎÎ

ns


Speed Power Product ÎÎÎÎÎÎÎÎÎÎÎÎ





0.01 ÎÎÎÎÎÎ

pJÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Frequency (D–F/F)

ÎÎÎÎÎÎÎÎÎÎÎÎfmax

ÎÎÎÎÎÎÎÎ33

ÎÎÎÎÎÎÎÎÎÎ35

ÎÎÎÎÎÎÎÎÎÎ4.0


ÎÎÎÎÎÎMHzÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎClock Frequency (Counter)ÎÎÎÎÎÎÎÎÎÎÎÎfmax

ÎÎÎÎÎÎÎÎ40




ÎÎÎÎÎÎMHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay (1)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


TTLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic

ÎÎÎÎÎÎÎÎ

LSÎÎÎÎÎÎÎÎÎÎ

ALSÎÎÎÎÎÎÎÎÎÎ



UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGate, NOR or NAND: Product No.

ÎÎÎÎÎÎÎÎSN74LS00

ÎÎÎÎÎÎÎÎÎÎSN74ALS00

ÎÎÎÎÎÎÎÎÎÎMC14001B

ÎÎÎÎÎÎÎÎÎÎ74HC00

ÎÎÎÎÎÎ—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH/tPHL(5) Typical

ÎÎÎÎÎÎÎÎ

(10)3ÎÎÎÎÎÎÎÎÎÎ


25ÎÎÎÎÎÎÎÎÎÎ

(8)3 10ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MaximumÎÎÎÎÎÎÎÎ




(15)3 20ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFlip–Flop, D–type: Product No.

ÎÎÎÎÎÎÎÎ

SN74LS74ÎÎÎÎÎÎÎÎÎÎ

SN74ALS74ÎÎÎÎÎÎÎÎÎÎ

MC14013BÎÎÎÎÎÎÎÎÎÎ

74HC74ÎÎÎÎÎÎ

—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tPLH/tPHL(5) (Clock to Q) TypicalÎÎÎÎÎÎÎÎ




(23)2 25ÎÎÎÎÎÎ






(30)3 32ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCounter: Product No. ÎÎÎÎ

ÎÎÎÎSN74LS163ÎÎÎÎÎ

ÎÎÎÎÎSN74ALS163ÎÎÎÎÎ

ÎÎÎÎÎMC14163BÎÎÎÎÎ

ÎÎÎÎÎ74HC163ÎÎÎ

ÎÎÎ—


tPLH/tPHL(5) (Clock to Q) TypicalÎÎÎÎÎÎÎÎ

(18)3 ÎÎÎÎÎÎÎÎÎÎ



(20)3 22 ÎÎÎÎÎÎ






(27)3 29 ÎÎÎÎÎÎNOTES:

1. Specifications are shown for the following conditions:a) VDD (CMOS) = 5.0 V ± 10% for dc tests, 5.0 V for ac tests; VCC (TTL) = 5.0 V ± 5% for dc tests, 5.0 V for ac testsb) Basic Gates: LS00 or equivalentc) TA = 25Cd) CL = 50 pF (ALS, HC), 15 pF (LS, 14000 and Hi–Speed)e) Commercial grade product

2. ( ) fanout to LSTTL3. ( ) CL = 15 pF4. DC input voltage specifications are proportional to supply voltage over operating range.5. The number specified is the larger of tPLH and tPHL for each device.

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The input protection network consists of large ESDprotection diodes, a diffused resistor, and two small“dummy” transistors. Outputs have a similar ESDprotection network except for the series resistor. Althoughthe on–chip protection circuitry guards against ESDdamage, additional protection may be necessary once thechip is placed in circuit. Both an external series resistor andground and VCC diodes, similar to the input protectionstructure, are recommended if there is a potential of ESD,voltage transients, etc. Several monolithic diode arrays areavailable from ON Semiconductor, such as the MAD130(dual 10 diode array) or the MAD1104 (dual 8 diode array).These diodes, in chip form, not only provide the necessaryprotection, but also save board space as opposed to usingdiscrete diodes.

Static damaged devices behave in various ways,depending on the severity of the damage. The most severelydamaged pins are the easiest to detect. An ESD–damagedpin that has been completely destroyed may exhibit alow–impedance path to VCC or GND. Another commonfailure mode is a fused or open circuit. The effect of bothfailure modes is that the device no longer properly respondsto input signals. Less severe cases are more difficult to detectbecause they show up as intermittent failures or as degradedperformance. Generally, another effect of static damage isincreased chip leakage currents (ICC).

Although the input network does offer significantprotection, these devices are not immune to large staticvoltage discharges that can be generated while handling. Forexample, static voltages generated by a person walkingacross a waxed floor have been measured in the 4 to 15 kVrange (depending on humidity, surface conditions, etc.).Therefore, the following precautions should be observed.

1. Wrist straps and equipment logs should be maintainedand audited on a regular basis. Wrist strapsmalfunction and may go unnoticed. Also, equipmentgets moved from time to time and grounds may not bereconnected properly.

2. Do not exceed the Maximum Ratings specified by thedata sheet.

3. All unused device inputs should be connected to VCCor GND.

4. All low impedance equipment (pulse generators, etc.)should be connected to CMOS inputs only after theCMOS device is powered up. Similarly, this type ofequipment should be disconnected before power isturned off.

5. Circuit boards containing CMOS devices are merelyextensions of the devices, and the same handlingprecautions apply. Contacting edge connectors wireddirectly to device inputs can cause damage. Plasticwrapping should be avoided. When externalconnectors to a PC board are connected to an input oroutput of a CMOS device, a resistor should be used inseries with the input or output. This resistor helps limitaccidental damage if the PC board is removed andbrought into contact with static generating materials.The limiting factor for the series resistor is the addeddelay. The delay is caused by the time constant formedby the series resistor and input capacitance. Note thatthe maximum input rise and fall times should not beexceeded. In Figure 5, two possible networks areshown using a series resistor to reduce ESD damage.For convenience, an equation is given for addedpropagation delay and rise time effects due to seriesresistance size.

Advantage: Requires minimal area

Disadvantage: R1 > R2 for the same level ofprotection; therefore, rise andfall times, propagation delays,and output drives are severelyaffected.

Advantage: R2 < R1 for the same level ofprotection. Impact on ac and dccharacteristics is minimized.

Disadvantage: More board area, higher initialcost.

where:R=the maximum allowable series resistance in ohmst= the maximum tolerable propagation delay or rise time int= secondsC= the board capacitance plus the driven inputC= capacitance in faradsk= 0.7 for propagation delay calculationsk= 2.3 for rise time calculations

TO OFF–BOARDCONNECTION

R1CMOSINPUT

OROUTPUT

TO OFF–BOARDCONNECTION

CMOSINPUT

OROUTPUT

R2

VCC

D1

D2

GND

Propagation Delay and Rise Time vs. Series Resistance

R

tC ·k

NOTE: These networks are useful for protecting the following:A digital inputs and outputs C 3–state outputsB analog inputs and outputs D bidirectional (I/O) ports

Figure 5. Networks for Minimizing ESD and Reducing CMOS Latch Up Susceptibility

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6. All CMOS devices should be stored or transported inmaterials that are antistatic or conductive. CMOSdevices must not be inserted into conventional plastic“snow”, Styrofoam, or plastic trays, but should be leftin their original container until ready for use.

7. All CMOS devices should be placed on a groundedbench surface and operators should groundthemselves prior to handling devices, because aworker can be statically charged with respect to thebench surface. Wrist straps in contact with skin areessential and should be tested daily. See Figure 6 foran example of a typical work station.

8. Nylon or other static generating materials should notcome in contact with CMOS devices.

9. If automatic handlers are being used, high levels ofstatic electricity may be generated by the movementof the device, the belts, or the boards. Reduce staticbuildup by using ionized air blowers, anti–staticsprays, and room humidifiers. All conductive parts ofmachines which come into contact with the top,bottom, or sides of IC packages must be grounded toearth ground.

10. Cold chambers using CO2 for cooling should beequipped with baffles, and the CMOS devices must becontained on or in conductive material.

11. When lead straightening or hand soldering isnecessary, provide ground straps for the apparatusused and be sure that soldering iron tips are grounded.

12. The following steps should be observed during wavesolder operations:a. The solder pot and conductive conveyor system of

the wave soldering machine must be grounded toearth ground.

b. The loading and unloading work benches shouldhave conductive tops grounded to earth ground.

c. Operators must comply with precautionspreviously explained.

d. Completed assemblies should be placed inantistatic or conductive containers prior to beingmoved to subsequent stations.

13. The following steps should be observed duringboard–cleaning operations:a. Vapor degreasers and baskets must be grounded to

earth ground.

b. Brush or spray cleaning should not be used.c. Assemblies should be placed into the vapor

degreaser immediately upon removal from theantistatic or conductive container.

d. Cleaned assemblies should be placed in antistaticor conductive containers immediately afterremoval from the cleaning basket.

e. High velocity air movement or application ofsolvents and coatings should be employed onlywhen a static eliminator using ionized air isdirected at the printed circuit board.

14. The use of static detection meters for production linesurveillance is highly recommended.

15. Equipment specifications should alert users to thepresence of CMOS devices and requirefamiliarization with this specification prior toperforming any kind of maintenance or replacementof devices or modules.

16. Do not insert or remove CMOS devices from testsockets with power applied. Check all power suppliesto be used for testing devices to be certain there are novoltage transients present.

17. Double check test equipment setup for proper polarityof VCC and GND before conducting parametric orfunctional testing.

18. Do not recycle shipping rails. Repeated use causesdeterioration of their antistatic coating. Exception:carbon rails (black color) may be recycled to someextent. This type of rail is conductive and antistatic.

RECOMMENDED READING

“Requirements for Handling Electrostatic–DischargeSensitive (ESDS) Devices” EIA Standard EIA–625

Available by writing to:Global Engineering Documents15 Inverness Way EastEnglewood, Colorado 80112

Or by calling:1–800–854–7179 in the USA or CANADA or(303) 397–7956 International

S. Cherniak, “A Review of Transients and Their Means ofSuppression”, Application Note–843, ON SemiconductorProducts Inc., 1982.

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NOTES:1. 1/16 inch conductive sheet stock covering bench-top work

area.2. Ground strap.3. Wrist strap In contact with skin.4. Static neutralizer. (ionized air blower directed at work.

Primarily for use in areas where direct grounding isimpractical.

5. Room humidifier. Primarily for use in areas where therelative humidity is less than 45%. Caution: buildingheating and cooling systems usually dry the air causingthe relative humidity inside a building to be less thanoutside humidity.

R = 1 M

1

2

3

4

5

Figure 6. Typical Manufacturing Work Station

POWER SUPPLY SIZING

CMOS devices have low power requirements and theability to operate over a wide range of supply voltages.These two characteristics allow CMOS designs to beimplemented using inexpensive power supplies withoutcooling fans. In addition, batteries may be used as either aprimary power source or as a backup.

The maximum recommended power supply voltage forHC devices is 6.0 V and 5.5 V for HCT devices. Figure 7offers some insight as to how this specification was derived.In the figure, VS is the maximum power supply voltage andIS is the sustaining current for the latch–up mode. The valueof VS was chosen so that the secondary breakdown effectmay be avoided. The low–current junction avalanche regionis between 10 and 14 volts at TA = 25C.

ICC

IS

VS VCC

LATCHUP MODE

SECONDARYBREAKDOWN

LOW CURRENTJUNCTION

AVALANCHE

DATA SHEET MAXIMUM SUPPLY RATING

Figure 7. Secondary Breakdown CharacteristicsIn an ideal system design, the power supply should be

designed to deliver only enough current to ensure proper

operation of all devices. The obvious benefit of this type ofdesign is cost savings.

BATTERY SYSTEMSHSCMOS devices can be used with battery or battery

backup systems. A few precautions should be taken whendesigning battery–operated systems.

1. The recommended power supply voltages should beobserved. For battery backup systems such as the onein Figure 8, the battery voltage must be at least2.7 volts (2 volts for the minimum power supplyvoltage and 0.7 volts to account for the voltage dropacross the series diode).

2. Inputs that might go above the battery backup voltageshould use the HC4049 or HC4050 buffers (Figure 8).If line power is interrupted, CMOS System A andBuffer A lose power. However, CMOS System B andBuffer B remain active due to the battery backup.Buffer A protects System A from System B byblocking active inputs while the circuit is not poweredup. Also, if the power supply voltage drops below thebattery voltage, Buffer A acts as a level translator forthe outputs from System B. Buffer B acts to protectSystem B from any overvoltages which might exist.Both buffers may be replaced with current–limitingresistors, however power consumption is increasedand propagation delays are lengthened.

3. Outputs that are subject to voltage levels above VCCor below GND should be protected with a seriesresistor and/or clamping diodes to limit the current toan acceptable level.

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POWER SUPPLY

BATTERY TRICKLERECHARGE

CMOSSYSTEM

Figure 8. Battery Backup System

POWER SUPPLY

LINE POWER ONLYSYSTEM

CMOSSYSTEM

HC4049HC4050

BATTERY BACKUPSYSTEM

HC4049HC4050

BATTERY TRICKLERECHARGE

CMOSSYSTEM

A B

Figure 9. Battery Backup Interface

CPD POWER CALCULATIONPower consumption for HSCMOS is dependent on the

power–supply voltage, frequency of operation, internalcapacitance, and load. The power consumption may becalculated for each package by summing the quiescentpower consumption, ICC • VCC, and the switching powerrequired by each device within the package. For largesystems, the most timely method is to bread–board thecircuit and measure the current required under a variety ofconditions.

The device dynamic power requirements can becalculated by the equation:

PD = (CL + CPD) VCC2f

where: PD = power dissipated in µW

CL = total load capacitance present at the output in pF

CPD = a measure of internal capacitances, calledpower dissipation capacitance, given in pF

VCC = supply voltage in volts

f = frequency in MHz

If the devices are tested at a sufficiently high frequency,the dc supply current contributes a negligible amount to theoverall power consumption and can therefore be ignored.For this reason, the power consumption is measured at

1 MHz and the following formula is used to determine thedevice’s CPD value:

ICC (dynamic)CPD =

VCC • f – CL

The resulting power dissipation is calculated using CPD asfollows under no–load conditions.

(HC) PD = CPDVCC2f + VCCICC(HCT) PD = CPDVCC2f + VCCICC + ∆ICCVCC

(δ1 + δ2 + … + δn)

where the previously undefined variable, δn is the duty cycleof each input applied at TTL/NMOS levels.

The power dissipation for analog switches switchingdigital signals is the following:

(HC) PD = CPDVCC2fin + (CS + CL)VCC2fout + VCCICCwhere: CS = digital switch capacitance, and

fout = output frequency

In order to determine the CPD of a single section of a device(i.e., one of four gates, or one of two flip–flops in a package),ON Semiconductor uses the following procedures asdefined by JEDEC. Note: “biased” as used below means“tied to VCC or GND.”

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Gates: Switch one input while the remaininginput(s) are biased so that the output(s)switch.

Latches: Switch the enable and data inputs such thatthe latch toggles.

Flip–Flops: Switch the clock pin while changing thedata pin(s) such that the output(s) changewith each clock cycle.

Decoders/ Switch one address pin which changes twoDemultiplexers: outputs.

Data Selectors/ Switch one address input with the corre-Multiplexers: sponding data inputs at opposite logic

levels so that the output switches.

Analog Switch one address/select pin whichSwitches: changes two switches. The switch

inputs/outputs should be left open. Fordigital applications where the switchinputs/outputs change between VCC andGND, the respective switch capacitanceshould be added to the load capacitance.

Counters: Switch the clock pin with the other inputsbiased so that the device counts.

Shift Switch the clock while alternating theinput

Registers: so that the device shifts alternating 1s and0s through the register.

Transceivers: Switch only one data input. Placetransceivers in a single direction.

Monostables: The pulse obtained with a resistor and noexternal capacitor is repeatedly switched.

Parity Switch one input.Generators:

Encoders: Switch the lowest priority output.

Display Switch one input so that approximatelyone–

Drivers: half of the outputs change state.

ALUs/Adders: Switch the least significant bit. Theremaining inputs are biased so that thedevice is alternately adding 0000 (binary)or 0001 (binary) to 1111 (binary).

On HSCMOS data sheets, CPD is a typical value and isgiven either for the package or for the individual device (i.e.,gates, flip–flops, etc.) within the package. An example ofcalculating the package power requirement is given usingthe 74HC00, as shown in Figure 10.

From the data sheet:

ICC = 2 µA at room temperature (per package)

CPD = 22 pF per gate

PD = (CPD + CL)VCC2f + VCCICC

PD1 = (22 pF + 50 pF)(5 V)2(1 kHz) 1.8 µW

PD2 = (22 pF + 50 pF)(5 V)2(1 MHz) 1800 µW

PD3 = (22 pF) (5 V)2(0 Hz) = 0 µW

PD4 = (22 pF)(5 V)2(0 Hz) = 0 µW

PD(total) = VCCICC + PD1 + PD2 + PD3 + PD4

= 10 µW + 1.8 µW + 1800 µW + 0 µW

= 1812 µW

VCC = 5 V

f = 1 kHz

f = 1 MHz

50 pF

1

2

3

4

50 pF

Figure 10. Power Consumption Calculation Example

As seen by this example, the power dissipated by CMOSdevices is dependent on frequency. When operating at veryhigh frequencies, HSCMOS devices can consume as muchpower as LSTTL devices, as shown in Figure 11. The powersavings of HSCMOS is realized when used in a systemwhere only a few of the devices are actually switching at thesystem frequency. The power consumption savings comesfrom the fact that for CMOS, only the devices that areswitching consume significant power.

VCC = 5 Vdc

100 m5

210 m

5

21 m

5

2100 µ

5

2

10 µ

10 k2 5

100 k2 5

1 M2 5

10 M2 5

100 M2 5

1 G7 7 7 7 7

FREQUENCY @ 50% DUTY CYCLE (Hz)

POW

ER (W

ATTS

)

MC7400

SN74LS00

SN74ALS00

MC74HC00

Figure 11. Power Consumption Vs. Input Frequencyfor TTL, LSTTL, ALs, and HSCMOS

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INPUTS

A basic knowledge of input and output structures isessential to the HSCMOS designer. This section deals withthe various input characteristics and application rulesregarding their use. Output characteristics are discussed inthe section titled Outputs.

All standard HC, HCU and HCT inputs, while in therecommended operating range (GND Vin VCC), can bemodeled as shown in Figure 12. For input voltages in thisrange, diodes D1 and D2 are modeled as resistorsrepresenting the high–impedance of reverse biased diodes.The maximum input current is 1 µA, worst case overtemperature, when the inputs are at VCC or GND, and VCC= 6 V.

VCC

R1

10 pF

R1 = R2 = HIGH Z

R2

Figure 12. Input Model for GND Vin VCC

When CMOS inputs are left open–circuited, the inputsmay be biased at or near the typical CMOS switchpoint of0.45 VCC for HC devices or 1.3 V for HCT devices. At thisswitchpoint, both the P–channel and the N–channeltransistors are conducting, causing excess current drain. Dueto the high gain of the buffered devices (see Figure 13), thedevice can go into oscillation from any noise in the system,resulting in even higher current drain.

Vin, INPUT VOLTAGE (V)

V

,O

UTP

UT

VOLT

AGE

(V)

out

5

4

3

2

1

0 1 2 3 4 5

HCT HC

Figure 13. Typical Transfer Characteristicsfor Buffered Devices

For these reasons, all unused HC/HCT inputs should beconnected either to VCC or GND. For applications withinputs going to edge connectors, a 100 kΩ resistor to GNDshould be used, as well as a series resistor (RS) for staticprotection and current limiting (see Handling Precautions,

this chapter, for series resistor consideration). The resistorsshould be configured as in Figure 14.

RS

100 k

FROMEDGE

CONNECTOR

HSCMOSDEVICE

Figure 14. External Protection

For inputs outside of the recommended operating range,the CMOS input is modeled as in Figure 15 and Figure 16.

Current flows through diode D1 or D2 whenever the inputvoltage exceeds VCC or drops below GND enough toforward bias either D1 or D2. The device inputs areguaranteed to withstand from GND – 0.5 V to VCC + 0.5 Vand a maximum current of 20 mA. If this maximum ratingis exceeded, the device could go into a latch–up condition.(See CMOS Latch Up, this chapter.) Voltage should neverbe applied to any input or output pin before power has beenapplied to the device’s power pins. Bias on input or outputpins should be removed before removing the power.However, if the input current is limited to less than 20 mA,and this current only lasts for a brief period of time (< 100ms), no damage to the device occurs.

Another specification that should be noted is themaximum input rise (tr) and fall (tf) times. Figure 17 showsthe results of exceeding the maximum rise and fall timesrecommended by ON Semiconductor or contained inJEDEC Standard No. 7A. The reason for the oscillation onthe output is that as the voltage passes through the switchingthreshold region with a slow rise time, any noise that is onthe input line is amplified, and is passed through to theoutput. This oscillation may have a low enough frequencyto cause succeeding stages to switch, giving unexpectedresults. If input rise or fall times are expected to exceed themaximum specified rise or fall times, Schmitt–triggereddevices such as ON Semiconductor’s HC14A and HC132Aare recommended.

OUTPUTS

All HSCMOS outputs, with the exception of theHCU04A, are buffered to ensure consistent output voltageand current specifications across the family. All bufferedoutputs have guaranteed output voltages of VOL = 0.1 V andVOH = VCC – 0.1 V for Iout 20 µA ( 20 HSCMOSloads).The output drives for standard drive devices are suchthat 74HC/HCT devices can drive ten LSTTL loads andmaintain a VOL 0.4 V and VOH VCC – 0.8 V across thefull temperature range; bus–driver devices can drive fifteenLSTTL loads under the same conditions.

The outputs of all HSCMOS devices are limited toexternally forced output voltages of – 0.5 Vout VCC+ 0.5 V. For externally forced voltages outside this range a

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latch up condition could be triggered. (See CMOS LatchUp, this chapter.)

The maximum rated output current given on theindividual data sheets is 25 mA for standard outputs and 35mA for bus drivers. The output short circuit currents of thesedevices typically exceed these limits. The outputs can,however, be shorted for short periods of time for logictesting, if the maximum package power dissipation is notviolated. (See individual data sheets for maximum powerdissipation ratings.)

For applications that require driving high capacitive loadswhere fast propagation delays are needed (e.g., drivingpower MOSFETS), devices within the same package may be

paralleled. Paralleling devices in different packages mayresult in devices switching at different points on the inputvoltage waveform, creating output short circuits andyielding undesirable output voltage waveforms.

As a design aid, output characteristic curves are givenfor both P–channel source and N–channel sink currents.The curves given include expected minimum curves forTA = 25C, 85C, and 125C, as well as typical values forTA = 25C. For temperatures < 25C, use the 25C curves.These curves, Figure 18 through Figure 29, are intended asdesign aids, not as guarantees. Unused output pins should beopen–circuited (floating).

Figure 15. Input Model for V in > VCC or Vin < GND

150

Vin

Vout

D1

D23 pF 2 pF

Figure 16. Input Model for New ESD Enhanced Circuits

D1

D23 pF 2 pF

Figure 17. Maximum Rise Time Violation

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STANDARD OUTPUT CHARACTERISTICS

N–CHANNEL SINK CURRENT P–CHANNEL SOURCE CURRENT

Figure 18. V GS = 2.0 V Figure 19. V GS = – 2.0 V

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

Vout, OUTPUT VOLTAGE (V)

I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

TYPICALTA = 25C

EXPECTED MINIMUM *, TA = 25–125C

TYPICALTA = 25C


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0

– 25

– 20

–15

–10

– 5

0



TYPICALTA = 25C TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUM CURVES*

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 4.0 3.5 3.0 0

– 25

– 20

–15

–10

– 5

0


2.5 2.0 1.5 1.0 0.5

TYPICALTA = 25C

TA = 25C

TA = 85C

TA = 125C


I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out


I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out


25

20

15

10

5

00 1.0 2.0 3.0 4.0 5.0 6.0 6.0 5.0 4.0 3.0 0

– 25

– 20

–15

–10

– 5

0


2.0 1.0

TYPICALTA = 25C

TA = 25C TA = 85C

TA = 125C


TYPICALTA = 25C

TA = 25C TA = 85C

TA = 125C


I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

*The expected minimum curves are not guarantees, but are design aids.

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BUS–DRIVER OUTPUT CHARACTERISTICS

N–CHANNEL SINK CURRENT P–CHANNEL SOURCE CURRENT


I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out


I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

TYPICALTA = 25C


TYPICALTA = 25C


25

20

15

10

5

00.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0

– 25

– 20

–15

–10

– 5

0


30

35

0

– 30

– 35


TYPICALTA = 25C TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUMS*


25

20

15

10

5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

4.5 4.0 3.5 3.0 0

– 25

– 20

–15

–10

– 5

0


2.5 2.0 1.5 1.0 0.5

TYPICALTA = 25C

TA = 25C TA = 85C

TA = 125C

EXPECTED MINIMUMS*

I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

30

35

– 30

– 35



25

20

15

10

5

00 2.0 3.0 4.0 5.0 6.0

I

, OU

TPU

T SI

NK

CU

RR

ENT

(mA)

out

6.0 5.0 4.0 3.0 0

– 25

– 20

–15

–10

– 5

0


2.0 1.0

TYPICALTA = 25C

TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUMS*

TYPICALTA = 25C

TA = 25C

TA = 85C

TA = 125C

EXPECTED MINIMUMS*

I

, OU

TPU

T SO

UR

CE

CU

RR

ENT

(mA)

out

30

35

1.0

– 30

– 35


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3–STATE OUTPUTSSome HC/HCT devices have outputs that can be placed

into a high–impedance state. These 3–state output devicesare very useful for gang connecting to a common line or bus.When enabled, these output pins can be considered asordinary output pins; as such, all specifications andprecautions of standard output pins should be followed.When disabled (high–impedance state), these outputs can bemodeled as in Figure 30. Output leakage current (10 µAworst case over temperature) as well as 3–state outputcapacitance must be considered in any bus design.

When power is interrupted to a 3–state device, the busvoltage is forced to between GND and VCC + 0.7 Vregardless of the previous output state.

R1

VCC

R1 = R2 = HIGH Z

OUTPUT

15 pFR2

INTERNALCIRCUITRY

Figure 30. Model for Disabled Outputs

OPEN–DRAIN OUTPUTSON Semiconductor provides several devices that are

designed only to sink current to GND. These open–drainoutput devices are fabricated using only an N–channeltransistor and a diode to VCC (Figure 31). The purpose of thediode is to provide ESD protection. Open–drain outputs canbe modeled as shown in Figure 32.

VCC

INTERNALCIRCUITRY

OUTPUT

Figure 31. Open–Drain Output

VCC

LOW Z

HIGH Z

OUTPUT

10 pF

HIGH Z

Figure 32. Model of Open–Drain Output

INPUT/OUTPUT PINSSome HC/HCT devices contain pins that serve both as

inputs and outputs of digital logic. These pins are referred toas digital I/O pins. The logic level applied to a control pindetermines whether these I/O pins are selected as inputs oroutputs.

When I/O pins are selected as outputs, these pins may beconsidered as standard CMOS outputs. When selected asinputs, except for an increase in input leakage current andinput capacitance, these pins should be considered asstandard CMOS inputs. These increases come from the factthat a digital I/O pin is actually a combination of an input anda 3–state output tied together (see Figure 33).

As stated earlier, all HC/HCT inputs must be connected toan appropriate logic level. This could pose a problem if anI/O pin is selected as an input while connected to animproperly terminated bus.

ON Semiconductor recommends terminatingHC/HCT–type buses with resistors to VCC or GND ofbetween 1 kΩ to 1 MΩ in value. The choice of resistor valueis a trade–off between speed and power consumption (seeBus Termination, this chapter).

Some ON Semiconductor devices have analog I/O pins.These analog I/O pins should not be confused with digitalI/O pins. Analog I/O pins may be modeled as in Figure 34.These devices can be used to pass analog signals, as well asdigital signals, in the same manner as mechanical switches.

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I/O

INTERNALCIRCUITRY

Figure 33. Typical Digital I/O Pin

GND OR VEEGND OR VEE

Ron

VCC VCC

HIGH Z

HIGH Z

ANALOGI/O

ANALOGO/I

Figure 34. Analog I/O Pin

BUS TERMINATIONBecause buses tend to operate in harsh, noisy

environments, most bus lines are terminated via a resistor toVCC or ground. This low impedance to VCC or ground(depending on preference of a pull–up or pull–down logiclevel) reduces bus noise pickup. In certain cases a bus linemay be released (put in a high–impedance state) by disablingall the 3–state bus drivers (see Figure 35). In this conditionall HC/HCT inputs on the bus would be allowed to float. ACMOS input or 1/0 pin (when selected as an input) shouldnever be allowed to float. (This is one reason why an HCTdevice may not be a drop–in replacement of an LSTTLdevice.) A floating CMOS input can put the device into thelinear region of operation. In this region excessive currentcan flow and the possibility of logic errors due to oscillationmay occur (see Inputs, this chapter). Note that when a busis properly terminated with pull–up resistors, HC devices,instead of HCT devices, can be driven by an NMOS orLSTTL bus driver. HC devices are preferred over HCTdevices in bus applications because of their higher low levelinput noise margin. (With a 5 V supply the typical HC switchpoint is 2.3 V while the switch point of HCT is only 1.3 V.)

Some popular LSTTL bus termination designs may notwork for HSCMOS devices. The outputs of HSCMOS may

not be able to drive the low value of termination used bysome buses. (This is another reason why an HCT device maynot be a drop in replacement for an LSTTL device.)However, because low power operation is one of the mainreasons for using CMOS, an optimized CMOS bustermination is usually advantageous.

BUS

ENABLE INPUT(HIGH = 3–STATE)

ENABLE INPUT(LOW = 3–STATE)

Figure 35. Typical Bus Line with 3–State Bus Drivers

The choice of termination resistances is a trade–offbetween speed and power consumption. The speed of thebus is a function of the RC time constant of the terminationresistor and the parasitic capacitance associated with thebus. Power consumption is a function of whether a pull–upor pull–down resistor is used and the output state of thedevice that has control of the bus (see Figure 36). The lowerthe termination resistor the faster the bus operates, but morepower is consumed. A large value resistor wastes less power,but slows the bus down. ON Semiconductor recommends atermination resistor value between 1 kΩ and 1 MΩ. Analternative to a passive resistor termination would be anactive–type termination (see Figure 37). This typetermination holds the last logic level on the bus until a drivercan once again take control of the bus. An active terminationhas the advantage of consuming a minimal amount of power.Most HC/HCT bus drivers do not have built–in hysteresis.Therefore, heavily loaded buses can slow down rise and fallsignals and exceed the input rise/fall time defined in JEDECStandard No. 7A. In this event, devices withSchmitt–triggered inputs should be used to condition theseslow signals.

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(a) USING A PULL-UP RESISTOR (b) USING A PULL-DOWN RESISTOR

VCC

VCC

VCC

(L)

I R

BUS

BUS

(H)

I

R

Figure 36.

BUS LINES ENABLE

Figure 37. Using Active Termination (HC125)

TRANSMISSION LINE TERMINATIONWhen data is transmitted over long distances, the line on

which the data travels can be considered a transmission line.(Long distance is relative to the data rate being transmitted.)Examples of transmission lines include high–speed buses,long PCB lines, coaxial and ribbon cables. All transmissionlines should be properly terminated into a low–impedancetermination. A low–impedance termination helps eliminatenoise, ringing, overshoot, and crosstalk problems. Also alow–impedance termination reduces signal degradationbecause the small values of parasitic line capacitance andinductance have lesser effect on a low–impedance line.

The value of the termination resistor becomes a trade–offbetween power consumption, data rate speeds, andtransmission line distance. The lower the resistor value, thefaster data can be presented to the receiving device, but themore power the resistor consumes. The higher the resistorvalue, the longer it will take to charge and discharge thetransmission line through the termination resistor (T = R •C).

Transmission line distance becomes more critical as datarates increase. As data rates increase, incident (andreflective) waves begin to resemble that of RF transmissionline theory. However, due to the nonlinearity of CMOSdigital logic, conventional RF transmission theory is notapplicable.

HC devices are preferred over HCT devices due to the factthat HC devices have higher switch points than HCTdevices. This higher switch point allows HC devices toachieve better incident wave switching on lower impedancelines.

HC/HCT may not have enough drive capability tointerface with some of the more popular LSTTLtransmission lines. (Possible reason why an HCT devicemay not be a drop–in replacement of an equivalent TTLdevice.) This does not pose a major problem since havinglarger value termination resistors is desirable for CMOStype transmission lines.

By increasing the termination resistance value, the CMOSadvantage of low power consumption can be realized. ONSemiconductor recommends a minimum terminationresistor value as shown in Figure 38. The terminationresistor should be as close to the receiving unit as possible.Another method of terminating the line driver, as well as thereceiving unit, is shown in Figure 39. Note that the resistorvalues in Figure 39 are twice the resistor value of Figure 38;this gives a net equivalent termination value of Figure 38.Even higher values of resistors may be used for eithertermination method. This reduces power consumption, butat the expense of speed and possible signal degradation.

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VCC

R1 = 1.5 kR1 = 1.0 k

HSCMOS(LINE DRIVER)

HSCMOS(RECEIVER)

R1

R2

Figure 38. Termination Resistors at the Receiver

VCCVCC

R1 = R3 = 3.0 kR2 = R4 = 2 k

HSCMOS HSCMOS

R1 R3

R2 R4

Figure 39. Termination Resistors atBoth the Line Driver and Receiver

CMOS LATCH UP

Typically, HSCMOS devices do not latch up with currentsof 75 mA forced into or out of the inputs or 300 mA for theoutputs under worst case conditions (TA = 125C and VCC= 6 V). Under dc conditions for the inputs, the inputprotection network typically fails, due to grossly exceedingthe maximum input voltage rating of – 0.5 to VCC + 0.5 Vbefore latch–up currents are reached. For most designs, latchup will not be a problem, but the designer should be awareof it, what causes it, and how it can be prevented.

Figure 40 shows the layout of a typical CMOS inverterand Figure 41 shows the parasitic bipolar devices that areformed. The circuit formed by the parasitic transistors andresistors is the basic configuration of a silicon controlledrectifier, or SCR. In the latch–up condition, transistors Q1and Q2 are turned on, each providing the base currentnecessary for the other to remain in saturation, therebylatching the device on. Unlike a conventional SCR, wherethe device is turned on by applying a voltage to the base ofthe NPN transistor, the parasitic SCR is turned on byapplying a voltage to the emitter of either transistor. The twoemitters that trigger the SCR are the same point, the CMOSoutput. Therefore, to latch up the CMOS device, the outputvoltage must be greater than VCC + 0.5 V or less than – 0.5

V and have sufficient current to trigger the SCR. Thelatch–up mechanism is similar for the inputs.

Once a CMOS device is latched up, if the supply currentis not limited, the device can be destroyed or its reliabilitycan be degraded. Ways to prevent such an occurrence arelisted below.

1. Industrial controllers driving relays or motors is anenvironment in which latch up is a potential problem.Also, the ringing due to inductance of longtransmission lines in an industrial setting couldprovide enough energy to latch up CMOS devices.Opto–isolators, such as ON Semiconductor’sMOC3011, are recommended to reduce chances oflatch up. See the ON Semiconductor Master SelectionGuide for a complete listing of ON Semiconductoropto–isolators.

2. Ensure that inputs and outputs are limited to themaximum rated values.

– 1.5 Vin VCC +1.5 V referenced to GND or– 0.5 Vin VCC +0.5 V referenced to GND

– 0.5 Vout VCC +0.5 V referenced to GND

|Iin| 20 mA

|Iout| 25 mA for standard outputs

|Iout| 35 mA for bus–driver outputs

3. If voltage transients of sufficient energy to latch up thedevice are expected on the inputs or outputs, externalprotection diodes can be used to clamp the voltage.Another method of protection is to use a series resistorto limit the expected worst case current to themaximum ratings value. See Handling Precautionsfor other possible protection circuits and a discussionof ESD prevention.

4. Sequence power supplies so that the inputs or outputsof HSCMOS devices are not active before the supplypins are powered up (e.g., recessed edge connectorsand/or series resistors may be used in plug–in boardapplications).

5. Voltage regulating and filtering should be used inboard design and layout to ensure that power supplylines are free of excessive noise.

6. Limit the available power supply current to thedevices that are subject to latch–up conditions. Thiscan be accomplished with the power–supply filteringnetwork or with a current–limiting regulator.

RECOMMENDED READINGPaul Mannone, “Careful Design Methods Prevent CMOSLatch–Up”, EDN, January 26, 1984.

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ÇÇÇ ÇÇ

VCC VCC

P–CHANNEL N–CHANNELINPUT

OUTPUTP–CHANNELOUTPUT

N–CHANNELOUTPUT

GND

FIELD OXIDE FIELD OXIDE FIELD OXIDEN+ P+ P+ N+ N+ P+

P – WELLN – SUBSTRATE

Figure 40. CMOS Wafer Cross Section

VCC

VCC

P–CHANNEL OUTPUT P – WELL RESISTANCEQ1

P+

P+

N–

P–

N–CHANNEL OUTPUTN – SUBSTRATE RESISTANCE

P–

N+N+N–

Q2

GND

GND

Figure 41. Latch–Up Circuit Schematic

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MAXIMUM POWER DISSIPATION

The maximum power dissipation for ON SemiconductorHSCMOS packages is 750 mW for both ceramic and plasticDIPs and 500 mW for SOIC packages. The deratings are –10 mW/C from 65C for plastic DIPs, and – 7 mW/C from65C for SOIC packages. This is illustrated in Figure 42.

– 40 0 40 80 120

100

200

300

400

500

600

800

P D, M

AXIM

UM

PAC

KAG

E PO

WER

DIS

SIPA

TIO

N (m

W)

TA, AMBIENT TEMPERATURE (°C)

700PLASTIC

DIP

TSSOPPACKAGE

SOICPACKAGE

Figure 42. Maximum Package PowerDissipation versus Temperature

Internal heat generation in HSCMOS devices comes fromtwo sources, namely, the quiescent power and dynamicpower consumption.

In the quiescent state, either the P–channel or N–channeltransistor in each complementary pair is off except for smallsource–to–drain leakage due to the inputs being either atVCC or ground. Also, there are the small leakage currentsflowing in the reverse–biased input protection diodes andthe parasitic diodes on the chip. The specification whichtakes all leakage into account is called Maximum QuiescentSupply Current (per package), or ICC, and is shown on alldata sheets.

The three factors which directly affect the value ofquiescent power dissipation are supply voltage, devicecomplexity, and temperature. On the data sheets, ICC isspecified only at VCC = 6.0 V because this is the worst–casesupply voltage condition. Also, larger or more complexdevices consume more quiescent power because thesedevices contain a proportionally greater reverse–biaseddiode junction area and more off (leaky) FETs.

Finally, as can be seen from the data sheets, temperatureincreases cause ICC increases. This is because at highertemperatures, leakage currents increase.

HC QUIESCENT POWER DISSIPATIONWhen HC device inputs are virtually at VCC or GND

potential (as in a totally CMOS system), quiescent powerdissipation is minimized. The equation for HC quiescentpower dissipation is given by:

PD = VCCICC

Worst–case ICC occurs at VCC = 6.0 V. The value of ICCat VCC = 6.0 V, as specified in the data sheets, is used for allpower supply voltages from 2 to 6 V.

HCT QUIESCENT POWER DISSIPATIONAlthough HCT devices belong to the CMOS family, their

input voltage specifications are identical to those of LSTTL.HCT parts can therefore be either judiciously substituted foror mixed with LS devices in a system.

TTL output voltages are VOL = 0.4 V (max) andVOH = 2.4 to 2.7 V (min).

Slightly higher ICC current exists when an HCT device isdriven with VOL = 0.4 V (max) because this voltage is highenough to partially turn on the N–channel transistor.However, when being driven with a TTL VOH, HCT devicesexhibit large additional current flow (∆ICC) as specified onHCT device data sheets. ∆ICC current is caused by theoff–rail input voltage turning on both the P and N channelsof the input buffer. This condition offers a relatively lowimpedance path from VCC to GND. Therefore, the HCTquiescent power dissipation is dependent on the number ofinputs applied at the TTL VIH logic voltage level.

The equation for HCT quiescent power dissipation isgiven by:

PD = ICCVCC + η∆ICCVCC

where η = the number of inputs at the TTL VIH level.

HC AND HCT DYNAMIC POWER DISSIPATIONDynamic power dissipation is calculated in the same way

for both HC and HCT devices. The three major factorswhich directly affect the magnitude of dynamic powerdissipation are load capacitance, internal capacitance, andswitching transient currents.

The dynamic power dissipation due to capacitive loads isgiven by the following equation:

PD = CLVCC2f

where PD = power in µW, CL = capacitive load in pF,VCC = supply voltage in volts, and f = output frequencydriving the load capacitor in MHz.

All CMOS devices have internal parasitic capacitancesthat have the same effect as external load capacitors. Themagnitude of this internal no–load power dissipationcapacitance, CPD, is specified as a typical value.

Finally, switching transient currents affect the dynamicpower dissipation. As each gate switches, there is a shortperiod of time in which both N– and P–channel transistorsare partially on, creating a low–impedance path from VCCto ground. As switching frequency increases, the powerdissipation due to this effect also increases.

The dynamic power dissipation due to CPD and switchingtransient currents is given by the following equation:

PD = CPDVCC2f

Therefore, the total dynamic power dissipation is givenby:

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PD = (CL + CPD)VCC2f

Total power dissipation for HC and HCT devices is merelya summation of the dynamic and quiescent powerdissipation elements. When being driven by CMOS logicvoltage levels (rail to rail), the total power dissipation forboth HC and HCT devices is given by the equation:

PD = VCCICC + (CL + CPD)VCC2f

When being driven by LSTTL logic voltage levels, thetotal power dissipation for HCT devices is given by theequation:

PD =VCCICC + VCC∆ICC(δ, + δ2 + … + δn)

+ (CL + CPD)VCC2f

where δn = duty cycle of LSTTL output applied to each inputof an HCT device.

THERMAL MANAGEMENTCircuit performance and long-term circuit reliability are

affected by die temperature. Normally, both are improved bykeeping the IC junction temperatures low.

Electrical power dissipated in any integrated circuit is asource of heat. This heat source increases the temperature ofthe die relative to some reference point, normally theambient temperature of 25°C in still air. The temperatureincrease, then, depends on the amount of power dissipatedin the circuit and on the net thermal resistance between theheat source and the reference point. See page 29 for thecalculation of CMOS power consumption.

The temperature at the junction is a function of thepackaging and mounting system’s ability to remove heatgenerated in the circuit — from the junction region to theambient environment. The basic formula for convertingpower dissipation to estimated junction temperature is:

TJ = TA + PD(θJC + θCA) ( 1 )

or

TJ = TA + PD(θJA) ( 2 )

where

TJ = maximum junction temperature

TA = maximum ambient temperature

PD = calculated maximum power dissipation including effects of external loads (see Power Dissipation on page 40).

θJC = average thermal resistance, junction to case

θCA = average thermal resistance, case to ambient

θJA = average thermal resistance, junction to ambient

This ON Semiconductor recommended formula has beenapproved by RADC and DESC for calculating a “practical”maximum operating junction temperature forMIL-M-38510 (JAN) devices.

Only two terms on the right side of equation ( 1 ) can bevaried by the user — the ambient temperature, and thedevice case-to-ambient thermal resistance, θCA. (To someextent the device power dissipation can also be controlled,but under recommended use the VCC supply and loadingdictate a fixed power dissipation.) Both system air flow andthe package mounting technique affect the θCA thermalresistance term. θJC is essentially independent of air flowand external mounting method, but is sensitive to packagematerial, die bonding method, and die area.

For applications where the case is held at essentially afixed temperature by mounting on a large or temperature-controlled heat sink, the estimated junction temperature iscalculated by:

TJ = TC + PD(θJC) ( 3 )

where TC = maximum case temperature and the otherparameters are as previously defined.

The maximum and average θJC resistance values forstandard IC packages are given in 2.

Table 2. Thermal Resistance Values for Standard I/C Packages

Thermal Resistance In Still Air

Package Description

No. Body Body Body Die Die Area Flag AreaθJC (°C/Watt)

No.Leads

BodyStyle

BodyMaterial

BodyW × L

DieBonds

Die Area(Sq. Mils)

Flag Area(Sg. Mils) Avg. Max.

14 DIL Epoxy 1/4″ × 3/4″ Epoxy 4096 6,400 38 6116 DIL Epoxy 1/4″ × 3/4″ Epoxy 4096 12,100 34 5420 DIL Epoxy 0.35″ × 0.35″ Epoxy 4096 14,400 N/A N/A

NOTES:1. All plastic packages use copper lead frames.2. Body style DIL is “Dual-In-Line.”3. Standard Mounting Method: Dual-In-Line Socket or P/C board with no contact between bottom of package and socket or P/C board.

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AIR FLOWThe effect of air flow over the packages on θJA (due to a

decrease in θCA) reduces the temperature rise of thepackage, therefore permitting a corresponding increase inpower dissipation without exceeding the maximumpermissible operating junction temperature.

Even though different device types mounted on a printedcircuit board may each have different power dissipations, allwill have the same input and output levels provided that eachis subject to identical air flow and the same ambient airtemperature. This eases design, since the only change inlevels between devices is due to the increase in ambienttemperatures as the air passes over the devices, ordifferences in ambient temperature between two devices.

The majority of users employ some form of air-flowcooling. As air passes over each device on a printed circuitboard, it absorbs heat from each package. This heat gradientfrom the first package to the last package is a function of theair flow rate and individual package dissipations. 3 providesgradient data at power levels of 200 mW, 250 mW, 300 mW,and 400 mW with an air flow rate of 500 Ifpm. These figuresshow the proportionate increase in the junction temperatureof each dual in-line package as the air passes over eachdevice. For higher rates of air flow the change in junctiontemperature from package to package down the airstreamwill be lower due to greater cooling.

3. Thermal Gradient of Junction Temperature(16-Pin Dual-In-Line Package)

Power Dissipation(mW)

Junction Temperature Gradient(°C/Package)

200 0.4

250 0.5

300 0.63

400 0.88

Devices mounted on 0.062″ PC board with Z axis spacing of 0.5″.Air flow is 500 lfpm along the Z axis.

4 is graphically illustrated in Figure 43 which shows thatthe reliability for plastic and ceramic devices is the sameuntil elevated junction temperatures induce intermetallicfailures in plastic devices. Early and mid-life failure rates ofplastic devices are not effected by this intermetallicmechanism.

PROCEDUREAfter the desired system failure rate has been established

for failure mechanisms other than intermetallics, each

device in the system should be evaluated for maximumjunction temperature. Knowing the maximum junctiontemperature, refer to 4 or Equation ( 1 ) on page 41 todetermine the continuous operating time required to 0.1%bond failures due to intermetallic formation. At this time,system reliability departs from the desired value as indicatedin Figure 43.

Air flow is one method of thermal management whichshould be considered for system longevity. Other commonlyused methods include heat sinks for higher powered devices,refrigerated air flow and lower density board stuffing. SinceθCA is entirely dependent on the application, it is theresponsibility of the designer to determine its value. This canbe achieved by various techniques including simulation,modeling, actual measurement, etc.

The material presented here emphasizes the need toconsider thermal management as an integral part of systemdesign and also the tools to determine if the managementmethods being considered are adequate to produce thedesired system reliability.

4. Device Junction Temperature versusTime to 0.1% Bond Failures

JunctionTemperature °C Time, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

1

1 10 100 1000

TIME, YEARS

NO

RM

ALIZ

ED F

AILU

RE

RAT

E

T J=

80C°

T J=

90C°

T J=

100

C°

T J=

110

C°

T J=

130

C°

T J=

120

C°

FAILURE RATE OF PLASTIC = CERAMICUNTIL INTERMETALLICS OCCUR

Figure 43. Failure Rate versus TimeJunction Temperature

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CAPACITIVE LOADING EFFECTSON PROPAGATION DELAY

In addition to temperature and power–supply effects,capacitive loading effects should be taken into account. Theadditional propagation delay may be calculated if the shortcircuit current for the device is known. Expected minimumnumbers may be determined from 5.

From the equation

Cdvci =

dt

this approximation follows:

I =C∆V

∆t

so

∆t =C∆V

I

or

∆t =I

C(0.5 VCC)

because the propagation delay is measured to the 50% pointof the output waveform (typically 0.5 VCC).

This equation gives the general form of the additionalpropagation delay. To calculate the propagation delay of adevice for a particular load capacitance, CL, the followingequation may be used.

tPT = tP + 0.5 VCC (CL – 50 pF) / IOS

where tPT = total propagation delay

tp = specified propagation delay with 50 pF load

CL = actual load capacitance

IOS = short circuit current (5)

An example is given here for tPHL of the 74HC00 driving a150 pF load.

VCC = 4.5 V

tPHL (50 pF) = 18 ns

CL = 150 pF

IOS = 17.3 mA

tPHL (150 pF) = 18 ns +(0.5)(4.5 V)(150 pF – 50 pF)

17.3 mA

= 18 ns + 13 ns

= 31 ns

Another example for CL = 0 pF and all other parameters thesame.

tPHL (0 pF) = 18 ns +(0.5)(4.5 V)(0 pF – 50 pF)

17.3 mA

= 18 ns + (– 6.5 ns)

tPHL = 11.5 ns

This method gives the expected propagation delay and isintended as a design aid, not as a guarantee.

Table 5. Expected Minimum Short Circuit Currents*


ÎÎÎÎÎÎÎÎ


Standard Drivers ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Bus Drivers ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎParameter ÎÎÎÎ

ÎÎÎÎVCCÎÎÎÎÎÎÎÎ

25CÎÎÎÎÎÎÎÎ

85C ÎÎÎÎÎÎÎÎ

125C ÎÎÎÎÎÎ

25CÎÎÎÎÎÎÎÎ

85CÎÎÎÎÎÎÎÎ

125C ÎÎÎÎÎÎ

Unit


Output Short Circuit Source Current ÎÎÎÎÎÎÎÎÎÎÎÎ

2.04.56.0


1.8918.535.2


1.8315.028.0


1.8013.424.6

ÎÎÎÎÎÎÎÎÎ

3.7537.070.6


3.6430.056.1


3.6026.649.2

ÎÎÎÎÎÎÎÎÎ

mA


Output Short Circuit Sink Current ÎÎÎÎÎÎÎÎÎÎÎÎ

2.04.56.0


1.5517.333.4


1.5514.026.5


1.5512.523.2

ÎÎÎÎÎÎÎÎÎ

2.4527.252.6


2.4522.141.7


2.4319.636.5

ÎÎÎÎÎÎÎÎÎ

mA

*These values are intended as design aids, not as guarantees.

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TEMPERATURE EFFECTS ONDC AND AC PARAMETERS

One of the inherent advantages of CMOS devices is thatcharacteristics of the N– and P–channel transistors, such asdrive current, channel resistance, propagation delay, andoutput transition time, track each other over a widetemperature range. Figure 44 shows the temperaturerelationships for these parameters. To illustrate the effects oftemperature on noise margin, Figure 45 shows the typicaltransfer characteristics for devices with buffered inputs andoutputs. Note that the typical switch point is at 45% of thesupply voltage and is minimally affected by temperature.

The graphs in this section are intended to be design aids,not guarantees.

–50 0 50 100 1500.5

1.0

1.5

TYPI

CAL

I OH,

tPL

H, t

PHL,

t TLH

THL

C, t

, R,

NO

RM

ALIZ

ED T

O 2

5 C

VAL

UE


IOH, IOLRC, tPLH, tPHL, tTLH, tTHL

°

Figure 44. Characteristics of Drive Current,Channel Resistance, and AC Parameters

Over Temperature

0 1.0 2.0 3.0 4.0 5.00

1.0

2.0

3.0

4.0

5.0

V out, O

UTP

UT

VOLT

AGE

(V)

Vin, INPUT VOLTAGE (V)

VCC = 5 Vdc

TA = –55°C

VIL

TA = 125°C

TA = 25°CVIH

Figure 45. Temperature Effects on the HCTransfer Characteristics

SUPPLY VOLTAGE EFFECTS ON DRIVECURRENT AND PROPAGATION DELAY

The transconductive gain, lout/Vin, of MOSFETs isproportional to the gate voltage minus the threshold voltage,VG – VT. The gate voltage at the input of the final stage ofbuffered devices is approximately the power supply voltage,VCC or GND. Because VG = VCC or GND, the output drivecurrent is proportional to the supply voltage. Propagationdelays for CMOS devices are also affected by the powersupply voltage, because most of the delay is due to chargingand discharging internal capacitances. Figure 46 andFigure 47 show the typical variation of current drive andpropagation delay, normalized to VCC = 4.5 V for 2.0 VCC 6.0 V. These curves may be used with the tables oneach data sheet to arrive at parametric values over thevoltage range.

2.0 3.0 4.0 5.0 6.00.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

(NO

RM

ALIZ

ED T

O 4

.5 V

NU

MBE

R)

I OH,

I OL,

TYP

ICAL

OU

TPU

T D

RIV

E C

UR

REN

T

VCC, POWER SUPPLY VOLTAGE (V)

Figure 46. Drive Current versus V CC

2.0 3.0 4.0 5.0 6.0

VCC, POWER SUPPLY VOLTAGE (V)

1.0

2.0

3.0

(NO

RM

ALIZ

ED T

O 4

.5 V

NU

MBE

R)

t PLH

, tPH

L, T

YPIC

AL P

RO

PAG

ATIO

N D

ELAY

CL = 50 pF

Figure 47. Propagation Delay versus V CC

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DECOUPLING CAPACITORS

The switching waveforms shown in Figure 48 andFigure 49 show the current spikes introduced to the powersupply and ground lines. This effect is shown for a loadcapacitance of less than 5 pF and for 50 pF. For ideal powersupply lines with no series impedance, the spikes wouldpose no problem. However, actual power supply and groundlines do possess series impedance, giving rise to noiseproblems. For this reason, care should be taken in boardlayouts, ensuring low impedance paths to and from logicdevices.

To absorb switching spikes, the following HSCMOSdevices should be bypassed with good quality 0.022 µF to0.1 µF decoupling capacitors:

1. Bypass every device driving a bus with all outputsswitching simultaneously.

2. Bypass all synchronous counters.3. Bypass devices used as oscillator elements.4. Bypass Schmitt–trigger devices with slow input rise

and fall times. The slower the rise and fall time, thelarger the bypass capacitor. Lab experimentation issuggested.

Bypass capacitors should be distributed over the circuitboard. In addition, boards could be decoupled with a 1 µFcapacitor.

BUFFERED DEVICE: INPUT tr, tf ≤ 500 ns, CL < 5 pF

I GN

DI C

CV

out

Figure 48. Switching Currents for C L < 5 pF

BUFFERED DEVICE: INPUT tr, tf ≤ 500 ns, CL < 5 pF

I GN

DI C

CV

out

Figure 49. Switching Currents for C L = 50 pF

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INTERFACING

HSCMOS devices have a wide operating voltage range(VCC = 2 to 6 V) and sufficient current drive to interface withmost other logic families available today. In this section,various interface schemes are given to aid the designer (seeFigure 50 through Figure 55). The various types of CMOSdevices with their input/output levels and comments aregiven in 6.

ON Semiconductor presently has available severalCMOS memories and microprocessors (see 7) which aredesigned to directly interface with High–Speed CMOS.With these devices now available, the designer has anattractive alternative to LSTTL/NMOS, and a totalHSCMOS system is now possible. (See SG102, CMOSSystem IC Selection Guide, for more information.)

Device designators are as follows:

HC This is a high–speed CMOS device with CMOS input switchinglevels and buffered CMOS outputs. The numbering of deviceswith this designator follows the LSTTL numbering sequence.These devices are functional and pinout equivalents of LSTTLdevices (e.g., HC00A, HC245A, etc.). Exceptions to this aredevices that are functional and pinout equivalents to metal–gateCMOS devices (e.g., HC4066, HC4538A, etc.).

HCU This is an unbuffered high–speed CMOS device with only onestage between the input and output. Because this is an unbuffereddevice, input and output levels may differ from buffered devices.At present, the family contains only one unbuffered device, theHCU04A.

HCT This is a high–speed CMOS device with an LSTTL–to–CMOSinput buffer stage. These devices are designed to interface withLSTTL outputs operating at VCC = 5 V ± 10%. HCT devices havefully buffered CMOS outputs that directly drive HSCMOS orLSTTL devices.

VCC

GNDHC OR HCT

DEVICEDIRECT

INTERFACELSTTL

DEVICE

Figure 50. HC to LSTTL Interfacing

VCC

GNDLSTTL

DEVICEDIRECT

INTERFACEHCT

DEVICE

Figure 51. LSTTL to HCT Interfacing

VCC

GNDHC

DEVICEPULL-UP

RESISTORLSTTL

DEVICE

Figure 52. LSTTL to HC Interfacing

5 V

GNDHC

DEVICEHC4049

ORHC4050

LSTTLDEVICE

3 V

GND

Figure 53. LSTTL to Low–Voltage HSCMOS

VDD = 3 –15 V* VCC = 2 – 6 V

GNDHC

DEVICEMC14049UB/14050BSTANDARD

CMOS

*VOH must be greater than VIH of low voltage Device;VDD = 3–18 V may be used if interfacing to 14049UB/14050B.

Figure 54. High Voltage CMOS to HSCMOS

HSCMOS/ STANDARD CMOS

STANDARD CMOS/HSCMOS

MC14504B

VCC/VDD VDD/VCC

LEVELSHIFTER

GND

GND

Figure 55. Up/Down Level Shifting Usingthe MC14504B

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Table 6. Interfacing GuideÎÎÎÎÎÎÎÎÎÎÎÎDevice

ÎÎÎÎÎÎÎÎÎÎÎÎInput Level

ÎÎÎÎÎÎÎÎÎÎOutput Level

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCommentsÎÎÎÎÎÎ

ÎÎÎÎÎÎHCXXXÎÎÎÎÎÎÎÎÎÎÎÎCMOS

ÎÎÎÎÎÎÎÎÎÎCMOS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLSTTL Functional and Pinout Equivalent DevicesÎÎÎÎÎÎ

ÎÎÎÎÎÎHC4XXX


CMOSÎÎÎÎÎÎÎÎÎÎ

CMOSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS Functional and Pinout Equivalent DevicesÎÎÎÎÎÎÎÎÎÎÎÎ

HCUXXÎÎÎÎÎÎÎÎÎÎÎÎ

CMOSÎÎÎÎÎÎÎÎÎÎ


Used in Linear ApplicationsÎÎÎÎÎÎÎÎÎÎÎÎ

HCTXXXÎÎÎÎÎÎÎÎÎÎÎÎ

TTLÎÎÎÎÎÎÎÎÎÎ


HSCMOS Device with TTL–to–CMOS Input BufferingÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14049UBMC14050B


– 0.5 Vin 18 VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Metal–Gate CMOS High–to–Low Level Translators, CMOS SwitchingLevels


MC14504B ÎÎÎÎÎÎÎÎÎÎÎÎ

CMOS or TTL ÎÎÎÎÎÎÎÎÎÎ

CMOS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Metal–Gate CMOS High–to–Low or Low–to–High Level Translator

Table 7. CMOS Memories and Microprocessors


CMOSMemories


CMOS Microprocessors

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MCM6147MCM61L47MCM68HC34

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC68HC01 MC146805G2MC68HC03 MC146805H2MC68HC11A8 MC1468705F2MC68HC11D4 MC1468705G2MC68HC811A2 MC68HC05C4MC68HC811D4 MC68HSC05C4MC68HC04P3 MC68HC05C8MC146805E2 MC68HC805C4MC146805F2 MC68HC000

RECOMMENDED READINGS. Craig, “Using High–Speed CMOS Logic for

Microprocessor Interfacing”, Application Note–868, ONSemiconductor Products Inc., 1982.

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TYPICAL PARAMETRIC VALUES

Given a fixed voltage and temperature, the electricalcharacteristics of High–Speed CMOS devices dependprimarily on design, layout, and processing variationsinherent in semiconductor fabrication.

A preliminary evaluation of each device type essentiallyguarantees that the design and layout of the device conformsto the criteria and standards set forth in the design goals.With very few exceptions, device electrical parameters,once established, do not vary due to design and layout.

Of much more concern is processing variation. A digitalprocessing line is allowed to deviate over a fairly broadprocessing range. This allows the manufacturer to incurreduced processing costs. These reduced processing costsare passed on to the consumer in the form of lower deviceprices.

Processing variation is the range from worst case to bestcase processing and is defined as the process window. Thiswindow is established with the aid of statistical processcontrol (SPC). With SPC, when a processing parameterapproaches the process window limit, that parameter isadjusted toward the middle of the window. This keepsprocess variations within a predetermined tolerance.

ON Semiconductor characterizes each device type overthis process window. Each device type is characterized byallowing experimental lots to be processed using worst caseand best case processing. The worst case processed lotsusually determine the minimum or maximum guaranteedlimit. (Whether the limit is a guaranteed minimum ormaximum depends on the particular parameter beingmeasured.)

In production, these limits are guaranteed by probe andfinal test and therefore appear independent of process

variation to the end user. However, this does not hold true forthe mean value of the total devices processed. The meanvalue, commonly referred to as a typical value, shifts overprocessing and therefore varies from lot to lot or even waferto wafer within a lot.

As with all processing or manufacturing, the total devicesbeing produced fit the normal distribution or bell curve ofFigure 56. In order to guarantee a valid typical value, atypical number plus a tolerance, would have to be specifiedand tested (see Figure 57). However, this would greatlyincrease processing costs which would have to be absorbedby the consumer.

In some cases, the device’s actual values are so small thatthe resolution of the automatic test equipment determinesthe guaranteed limit. An example of this is quiescent supplycurrent and input leakage current.

Most manufacturers provide typical numbers by one oftwo methods. The first method is to simply double or halve,depending on the parameter, the guaranteed limit todetermine a typical number. This would theoretically put allprocessed lots in the middle of the process window. Anotherapproach to typical numbers is to use a typical value that isderived from the aforementioned experimental lots.However, neither method accurately reflects the mean valueof devices any one consumer can expect to receive.

Therefore, the use of typical parametric numbers fordesign purposes does not constitute sound engineeringdesign practice. Worst case analysis dictates the use ofguaranteed minimum or maximum values. The onlypossible exception would be when no guaranteed value isgiven. In this case a typical value may be used as a ballparkfigure.

REJECTREGION

REJECTREGION

MINLIMIT

MAXLIMIT

(a) (b)

REJECTREGION

MINVALUE REJECT

REGION

MAXVALUE

MEAN (TYP)VALUE

Figure 56.

Figure 57.

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REDUCTION OF ELECTROMAGNETICINTERFERENCE (EMI)

Electromagnetic interference (EMI) and radio frequencyinterference (RFI) are phenomena inherent in all electricalsystems covering the entire frequency spectrum. Althoughthe characteristics have been well documented, EMIremains difficult to deal with due to numerous variables.EMI should be considered at the beginning of a design, andtaken into account during all stages, including productionand beyond.

These entities must be present for EMI to be a factor: (1)a source of EMI, (2) a transmission medium for EMI, and (3)a receiver of EMI. Several sources include relays, FMtransmitters, local oscillators in receivers, power lines,engine ignitions, arc welders, and lighting. EMItransmission paths include ground connections, cables, andthe space between conductors. Some receivers of EMI areradar receivers, computers, and television receivers.

For microprocessor based equipment, the source ofemissions is usually a current loop on a PC board. The chipsand their associated loop areas also function as receivers ofEMI. The fact is that PC boards which radiate high levels ofEMI are also more likely to act as receivers of EMI.

All logic gates are potential transmitters and receivers ofemissions. Noise immunity and noise margin are twocriterion which measure a gate’s immunity to noise whichcould be caused by EMI. CMOS technology, as opposed tothe other commonly used logic families, offers the best valuefor noise margin, and is therefore an excellent choice whenconsidering EMI.

The electric and magnetic fields associated with ICs areproportional to the current used, the current loop area, andthe switching transition times. CMOS technology ispreferred due to smaller currents. Also, the current loop areacan be reduced by the use of surface mount packages.

In a system where several pieces of equipment areconnected by cables, at least five coupling paths should betaken into account to reduce EMI. They are: (1) commonground impedance coupling (a common impedance isshared between an EMI source and receiver), (2)common–mode, field–to–cable coupling (electromagneticfields enter the loop found by two pieces of equipment, thecable connecting them, and the ground plane), (3)differential–mode, field–to–cable coupling(electromagnetic fields enter the loop formed by two piecesof equipment and the cable connecting them), (4) crosstalkcoupling (signals in one transmission line are coupled intoanother transmission line), and (5) a conductive paththrough power lines.

Shielding is a means of reducing EMI. Some of the morecommonly used shields against EMI and RFI contain

stainless steel fiber–filled polycarbonate, aluminumflake–filled polycarbonate/ABS coated with nickel andcopper electrolysis plating or cathode sputtering, nickelcoated graphite fiber, and polyester SMC with carbon–fiberveil. Several manufacturers who make conductivecompounds and additives are listed below.

SHIELDING MANUFACTURERSGeneral Electric Co., Plastics Group, Pittsfield, MA

Mobay Chemical Corp., Pittsburgh, PA

Wilson–Fiberfil International, Evansville, IN

American Cyanamid Co., Wayne, NJ

Fillite U.S.A., Inc., Huntington, WV

Transnet Corp., Columbus, OH

ON Semiconductor does not recommend, or in any waywarrant the manufacturers listed here. Additionally, noclaim is made that this list is by any means complete.

RECOMMENDED READINGD. White, K. Atkinson, and J. Osburn, “Taming EMI inMicroprocessor Systems”, IEEE Spectrum, Vol. 22,Number 12, Dec. 1985.D. White and M. Mardiguian, EMI Control Methodologyand Procedures, 1985.H. Denny, Grounding for the Control of EMI.M. Mardiguian, How to Control Electrical Noise.D. White, Shielding Design Methodology and Procedures.For more information on this subject, contact:

Interference Control TechnologiesDon White Consultants, Inc., SubsidiaryState Route 625P.O. Box DGainesville, VA 22065

HYBRID CIRCUIT GUIDELINES

High–Speed CMOS devices, when purchased in chip(die) form, are useful in hybrid circuits. Most high–speeddevices are fabricated with P wells and N substrates.Therefore, the substrates should be tied to VCC (+ supply).

Several devices however, are fabricated with N wells andP substrates. In this case, the substrates should be tied toGND. The best solution to alleviate confusion about thesubstrate is the use of nonconductive or insulativesubstrates. This averts the necessity of tying the substrate offto either VCC or GND.

For more information on hybrid technology, contact:

International Society for Hybrid MicroelectronicsP.O. Box 3255Montgomery, AL 36109

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SCHMITT–TRIGGER DEVICES

Schmitt–trigger devices exhibit the effect of hysteresis.Hysteresis is characterized by two different switchingthreshold levels, one for positive–going input transitionsand the other for negative–going input transitions.

Schmitt triggers offer superior noise immunity whencompared to standard gates and inverters. Applications forSchmitt triggers include line receivers, sine to square waveconverters, noise filters, and oscillators. ON Semiconductoroffers six versatile Schmitt–trigger devices in theHigh–Speed CMOS logic family (see 8).

The typical voltage transfer characteristics of a standardCMOS inverter and a CMOS Schmitt–trigger inverter arecompared in Figure 58 and Figure 59. The singular transferthreshold of the standard inverter is replaced by two distinctthresholds in a Schmitt–trigger inverter. During apositive–going transition of Vin, the output begins to go lowafter the VT+ threshold is reached. During a negative–goingVin transition, Vout begins to go high after the VT– thresholdis reached. The difference between VT+ and VT– is definedas VH, the hysteresis voltage.

As a direct result of hysteresis, Schmitt–trigger circuitsprovide excellent noise immunity and the ability to square

up signals with long rise and fall times. Positive–going inputnoise excursions must rise above the VT+ threshold beforethey affect the output. Similarly, negative–going input noiseexcursions must drop below the VT– threshold before theyaffect the output.

The HC132A can be used as a direct replacement for theHC00A NAND gate, which does not have Schmitt–triggercapability. The HC132A has the same pin assignment as theHC00A. Schmitt–trigger logic elements act as standardlogic elements in the absence of noise or slow rise and falltimes, making direct substitution possible.

Versatility and low cost are attractive features of CMOSSchmitt triggers. With six Schmitt triggers per HC14Apackage, one trigger can be used for a noise eliminationapplication while the other five function as standardinverters. Similarly, each of the four triggers in the HC132Acan be used as either Schmitt triggers or NAND gates orsome combination of both.

Table 8. Schmitt–Trigger Devices


HC14AHCT14AHC132A


Hex Schmitt–Trigger InverterHex Schmitt–Trigger Inverter with LSTTL InputsQuad 2–Input NAND Gate with Schmitt–Trigger

Inputs

VCC

Vout

0 Vin VCC

Figure 58. Standard Inverter Transfer Characteristic

VH

VCC

Vout

0 Vin VCC

VT– VT+

Figure 59. Schmitt–Trigger Inverter Transfer Characteristic

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OSCILLATOR DESIGN WITH HIGH–SPEED CMOS

Oscillator design is a fundamental requirement of manysystems and several types are discussed in this section. Ingeneral, an oscillator is comprised of two parts: an activenetwork and a feedback network. The active network isusually in the form of an amplifier, or an unbuffered inverter,such as the HCU04. The feedback network is mainlycomprised of resistors, capacitors, and depending upon theapplication, a quartz crystal or ceramic resonator.

Buffered inverters are never recommended in oscillatorapplications due to their high gain and added propagationdelay. For this reason ON Semiconductor manufactures theHCU04A, which is an unbuffered hex inverter.

Oscillators for use in digital systems fall into two generalcategories, RC oscillators and crystal or ceramic resonatoroscillators. Crystal oscillators have the best performance,but are more costly, especially for nonstandard frequencies.RC oscillators are more useful in applications wherestability and accuracy are not of prime importance. Wherehigh performance at low frequencies is desired, ceramicresonators are sometimes used.

RC OSCILLATORSThe circuit in Figure 60 shows a basic RC oscillator using

the HCU04A. When the input voltage of the first inverterreaches the threshold voltage, the outputs of the twoinverters change state, and the charging current of thecapacitor changes direction. The frequency at which thiscircuit oscillates depends upon R1 and C. The equation tocalculate these component values is given in Figure 60.

1/6 HCU04A 1/6 HCU04A BUFFER

R2 R1 C 2R1 R2 10 R1C 100 pF1 k R1 1 M

fOSC1

2.3 R1•C

Vout

Figure 60. RC Oscillator

Certain constraints must be met while designing this typeof oscillator. Stray capacitance and inductance must be keptto a minimum by placing the passive components as close tothe chip as possible. Also, at higher frequencies, theHCU04A’s propagation delay becomes a dominant effectand affects the cycle time. A polystyrene capacitor isrecommended for optimum performance.

CRYSTAL OSCILLATORSCrystal oscillators provide the required stability and

accuracy which is necessary in many applications. Thecrystal can be modeled as shown in Figure 62.

The power dissipated in a crystal is referred to as the drivelevel and is specified in mW. At low drive levels, theresonant resistance of the crystal can be so large as to causestart–up problems. To overcome this problem, the amplifier(inverter) should provide enough amplification, but not toomuch as to overdrive the crystal.

Figure 61 shows a Pierce crystal oscillator circuit, whichis a popular configuration with CMOS.

OSCout2OSCin

Rf

1/6 HCU04A 1/6 HCU04A

OSCout1

BUFFER

R1

C1 C2

Figure 61. Pierce Crystal Oscillator Circuit

Choosing R1Power is dissipated in the effective series resistance of the

crystal. The drive level specified by the crystal manufactureris the maximum stress that a crystal can withstand withoutdamage or excessive shift in frequency. R1 limits the drivelevel.

Values are supplied by the crystal manufacturer(parallel resonant crystal)

1 2 1 2 1 2Re Xe

Rs Ls Cs

Co

Figure 62. Equivalent Crystal Networks

To verify that the maximum dc supply voltage does notoverdrive the crystal, monitor the output frequency at OSCOut 2. The frequency should increase very slightly as the dc

supply voltage is increased. An overdriven crystal decreasesin frequency or becomes unstable with an increase in supplyvoltage. The operating supply voltage must be reduced or RI

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must be increased in value if the overdriven condition exists.The user should note that the oscillator start–up time isproportional to the value of R1.

Selecting R fThe feedback resistor (Rf) typically ranges up to 20 MD.

Rf determines the gain and bandwidth of the amplifier.Proper bandwidth ensures oscillation at the correctfrequency plus roll–off to minimize gain at undesirablefrequencies, such as the first overtone. Rf must be largeenough so as not to affect the phase of the feedback networkin an appreciable manner.

RECOMMENDED READINGD. Babin, “Designing Crystal Oscillators”, MachineDesign, March 7, 1985.D. Babin, “Guidelines for Crystal Oscillator Design”,Machine Design, April 25, 1985.

PRINTED CIRCUIT BOARD LAYOUT

Noise generators on the power supply lines should bedecoupled. The two major sources of noise on the powersupply lines are peak current in output stages duringswitching and the charging and discharging of parasiticcapacitances.

A good power distribution network is essential beforedecoupling can provide any noise reduction. Avoid usingjumpers for ground and power connections; the inductancethey introduce into the lines permits coupling betweenoutputs. Therefore, use of PC boards with premanufacturedground connections is advised to connect the device pins toground.

However, the optimum solution is to use multi–layer PCboards where different layers are used for the supply railsand interconnections. Even with double–sided boards,placing the power and ground lines on opposite sides of theboard whenever possible is recommended. The multi–wireboard is a less expensive approach than the multi–layer PCboard, while retaining the same noise reductioncharacteristics. As a rule of thumb, there should be severalground pins per connector to give good ground distribution.

The precautions for ground lines also apply to VCC lines:1) separate power stabilization for each board; 2) isolatenoise sources; and 3) avoid the use of large, single voltageregulators.

After all of these precautions, decoupling is an addedmeasure to reduce supply noise. See the DecouplingCapacitors section.

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HC vs. HCT

ON Semiconductor’s High–Speed CMOS is intended togive the designer an alternative to LSTTL. HSCMOS, withthe faster speed advantage over metal–gate CMOS(MC14000 series) and the lower power consumptionadvantage over LSTTL, is an optimum choice for newmidrange designs. With the advent of high–speed CMOSmicroprocessors and memories, the ability to design a 100%CMOS system is now possible.

HCT devices offer a short–term solution to theTTL/NMOS–to–CMOS interface problem. To achieve thisinterface capability, some CMOS advantages had to becompromised. These compromises include powerconsumption, operating voltage range, and noise immunity.

In most cases HCT devices are drop–in replacements ofTTL devices with significant advantages over the TTLdevices. However, in some cases, an equivalent HCT devicemay not replace a TTL device without some form of circuitmodification.

The wise designer uses HCT devices to perform logiclevel conversions only. In new designs, the designer wantsall the advantages of a true CMOS system and designs usingonly HC devices.

GLOSSARY OF TERMS

Cin Input Capacitance — The parasitic capacitanceassociated with a given input pin.

CL Load Capacitance — The capacitor value whichloads each output during testing and/or evaluation.This capacitance is assumed to be attached to eachoutput in a system. This includes all wiring and straycapacitance.

Cout Output Capacitance — The capacitance associatedwith a three–state output in the high–impedance state.

CPD Power Dissipation Capacitance — Used todetermine device dynamic power dissipation, i.e., PD= CPDVCC2f + VCCICC. See POWER SUPPLYSIZING for a discussion of CPD.

fmax Maximum Clock Frequency — The maximumclocking frequency attainable with the followinginput and output conditions being met:

Input Conditions — (HC) tr = tf = 6 ns, voltageswing from GND to VCC with 50% duty cycle. (HCT)tr = tf = 6 ns, voltage swing from GND to 3.0 V with50% duty cycle.

Output Conditions — (HC and HCT) waveformmust swing from 10% of (VOH – VOL) to 90% of(VOH – VOL) and be functionally correct under thegiven load condition: CL = 50 pF, all outputs.

VCC Positive Supply Voltage — + dc supply voltage(referenced to GND). The voltage range over whichICs are functional.

Vin Input Voltage — DC input voltage (referenced toGND).

Vout Output Voltage — DC output voltage (referenced toGND).

VIH Minimum High Level Input Voltage — The worstcase voltage that is recognized by a device as theHIGH state.

VIL Maximum Low Level Input Voltage — The worstcase voltage that is recognized by a device as the LOWstate.

VOH Minimum High Level Output Voltage — The worstcase high–level voltage at an output for a given outputcurrent (lout) and supply voltage (VCC).

VOL Maximum Low Level Output Voltage — The worstcase low–level voltage at an output for a given outputcurrent (lout) and supply voltage (VCC).

VT+ Positive–Going Input Threshold Voltage — Theminimum input voltage of a device with hysteresiswhich is recognized as a high level. (Assumes ramp upfrom previous low level.)

VT– Negative–Going Input Threshold Voltage — Themaximum input voltage of a device with hysteresiswhich is recognized as a low level. (Assumes rampdown from previous high level).

VH Hysteresis Voltage — The difference between VT+and VT– of a given device with hysteresis. A measureof noise rejection.

ICC IC Quiescent Supply Current — The current intothe VCC pin when the device inputs are static at VCC orGND and outputs are not connected.

∆ICCAdditional Quiescent Supply Current — Thecurrent into the VCC pin when one of the device inputsis at 2.4 V with respect to GND and the other inputs arestatic at VCC or GND. The outputs are not connected.

I in Input Current — The current into an input pin withthe respective input forced to VCC or GND. A negativesign indicates current is flowing out of the pin(source). A positive sign or no sign indicates current isflowing into the pin (sink).

lout Output Current — The current out of an output pin.A negative sign indicates current is flowing out of thepin (source). A positive sign or no sign indicatescurrent is flowing into the pin (sink).

I IH Input Current (High) — The input current when theinput voltage is forced to a high level.

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I IL Input Current (Low) — The input current when theinput voltage is forced to a low level.

IOH Output Current (High) — The output current whenthe output voltage is at a high level.

IOL Output Current (Low) — The output current whenthe output voltage is at a low level.

IOZ Three–State Leakage Current — The current into orout of a three–state output in the high–impedance statewith that respective output forced to VCC or GND.

tPLHLow–to–High Propagation Delay (HC) — The timeinterval between the 0.5 VCC level of the controllinginput waveform and the 50% level of the outputwaveform, with the output changing from low level tohigh level. (HCT) — The time interval between the1.3 V level (with respect to GND) of the controllinginput waveform and the 1.3 V level (with respect toGND) of the output waveform, with the outputchanging from low level to high level.

tPHLHigh–to–Low Propagation Delay (HC) — The timeinterval between the 0.5 VCC level of the controllinginput waveform and the 50% level of the outputwaveform, with the output changing from high levelto low level. (HCT) — The time interval between the1.3 V level (with respect to GND) of the controllinginput waveform and the 1.3 V level (with respect toGND) of the output waveform, with the outputchanging from high level to low level.

tPLZ Low–Level to High–Impedance PropagationDelay (Disable Time) — The time interval betweenthe 0.5 VCC level for HC devices (1.3 V with respect toGND for HCT devices) of the controlling inputwaveform and the 10% level of the output waveform,with the output changing from the low level tohigh–impedance (off) state.

tPHZHigh–Level to High–impedance PropagationDelay (Disable Time) — The time interval betweenthe 0.5 VCC level for HC devices (1.3 V with respect toGND for HCT devices) of the controlling inputwaveform and the 90% level of the output waveform,with the output changing from the high level tohigh–impedance (off) state.

tPZL High–Impedance to Low–Level PropagationDelay (Enable Time) — The time interval between0.5 VCC level (HC) or 1.3 V level with respect toGND (HCT) of the controlling input waveform andthe 50% level (HC) or 1.3 V level with respect to GND(HCT) of the output waveform, with the outputchanging from the high–impedance (off) state to a lowlevel.

tPZHHigh–Impedance to High–Level PropagationDelay (Enable Time) — The time interval betweenthe 0.5 VCC level (HC) or 1.3 V level with respectto GND (HCT) of the controlling input waveform andthe 50% level (HC) or 1.3 V level with respect to GND(HCT) of the output waveform, with the outputchanging from the high–impedance (off) state to ahigh level.

tTLH Output Low–to–High Transition Time — The timeinterval between the 10% and 90% voltage levels ofthe rising edge of a switching output.

tTHL Output High–to–Low Transition Time — The timeinterval between the 90% and 10% voltage levels ofthe falling edge of a switching output.

tsu Setup Time — The time interval immediatelypreceeding the active transition of a clock or latchenable input, during which the data to be recognizedmust be maintained (valid) at the input to ensureproper recognition. A negative setup time indicatesthat the data at the input may be applied sometimeafter the active clock or latch transition and still berecognized. For HC devices, the setup time ismeasured from the 50% level of the data waveform tothe 50% level of the clock or latch input waveform.For HCT devices, the setup time is measured from the1.3 V level (with respect to GND) of the datawaveform to the 1.3 V level (with respect to GND) ofthe clock or latch input waveform.

th Hold Time — The time interval immediatelyfollowing the active transition of a clock or latchenable input, during which the data to be recognizedmust be maintained (valid) at the input to ensureproper recognition. A negative hold time indicatesthat the data at the input may be changed prior to theactive clock or latch transition and still be recognized.For HC devices, the hold time is measured from the50% level of the clock or latch input waveform to the50% level of the data waveform. For HCT devices, thehold time is measured from the 1.3 V level (withrespect to GND) of the clock or latch input waveformto the 1.3 V level (with respect to GND) of the datawaveform.

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trec Recovery Time (HC) — The time interval betweenthe 50% level of the transition from active to inactivestate of an asynchronous control input and the 50%level of the active clock or latch enable edge requiredto guarantee proper operation of a device. (HCT) —The time interval between the 1.3 V level (with respectto GND) of the transition from active to inactive stateof an asynchronous control input and the 1.3 V level(with respect to GND) of the active clock or latch edgerequired to guarantee proper operation of a logicdevice.

tw Pulse Width (HC) — The time interval between 50%levels of an input pulse required to guarantee properoperation of a logic device. (HCT) — The timeinterval between 1.3 V levels (with respect to GND) ofan input pulse required to guarantee proper operationof a logic device.

tr Input Rise Time (HC) — The time interval betweenthe 10% and 90% voltage levels on the rising edge ofan input signal. (HCT) — The time interval betweenthe 0.3 V level and 2.7 V level (with respect to GND)on the rising edge of an input signal.

tf Input Fall Time (HC) — The time interval betweenthe 90% and 10% voltage levels on the falling edge ofan input signal. (HCT) — The time interval betweenthe 2.7 V level and 0.3 V level (with respect to GND)on the falling edge of an input signal.

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APPLICATIONS ASSISTANCE FORMIn the event that you have any questions or concerns about the performance of any ON Semiconductor device listed in thiscatalog, please contact your local ON Semiconductor sales office or the ON Semiconductor Help line for assistance. If furtherinformation is required, you can request direct factory assistance.

Please fill out as much of the form as is possible if you are contacting ON Semiconductor for assistance or are sending devicesback to ON Semiconductor for analysis. Your information can greatly improve the accuracy of analysis and can dramaticallyimprove the correlation response and resolution time.

Items 4 thru 8 of the following form contains important questions that can be invaluable in analyzing application or deviceproblems. It can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog with ONSemiconductor representatives.

ON Semiconductor Device Correlation/Component Analysis Request Form— Please fill out entire form and return with devices to ON Semiconductor, R&QA Dept., 5005 E. McDowell, Phoenix, AZ 85008.

1) Name of Person Requesting Correlation:

Phone No: Job Title: Company:

2) Alternate Contact: Phone/Position:

3) Device Type (user part number):

4) Industry Generic Device Type:

5) # of devices tested/sampled:

# of devices in question*:

# returned for correlation:

* In the event of 100% failure, does Customer have other date codes of ON Semiconductor devices that pass inspection?Yes No Please specify passing date code(s) if applicable

If none, does customer have viable alternate vendor(s) for device type?Yes No Alternate vendor’s name

6) Date code(s) and Serial Number(s) of devices returned for correlation — If possible, please provide one or two “good” units(ON Semiconductor’s and/or other vendor) for comparison:

7) Describe USER process that device(s) are questionable in:

Incoming component inspection test system = ?:

Design prototyping:

Board test/burn-in:

Other (please describe):

8) Please describe the device correlation operating parameters as completely as possible for device(s) in question:

> Describe all pin conditions (e.g. floating, high, low, under test, stimulated but not under test, whatever ...), including any inputor output loading conditions (resistors, caps, clamps, driving devices or devices being driven ...). Potentially criticalinformation includes:

Input waveform timing relationshipsInput edge ratesInput Overshoot or Undershoot — Magnitude and DurationOutput Overshoot or Undershoot — Magnitude and Duration

> Photographs, plots or sketches of relevent inputs and outputs with voltages and time divisions clearly identified for allwaveforms are greatly desirable.

> VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications andtest systems. Dynamic characteristics of Ground and VCC during device switching can dramatically effect input and internaloperating levels. Ground & VCC measurements should be made as physically close to the device in question as possible.

> Are there specific circumstances that seem to make the questionable unit(s) worse? Better?

Temperature

VCCInput rise/fall time

Output loading (current/capacitance)

Others

> ATE functional data should include pattern with decoding key and critical parameters such as VCC, input voltages, Func steprate, voltage expected, time to measure.

http://onsemi.com57

CHAPTER 3Data Sheets

Semiconductor Components Industries, LLC, 1999

March, 2000 – Rev. 858 Publication Order Number:

MC74HC00A/D

High–Performance Silicon–Gate CMOS

The MC74HC00A is identical in pinout to the LS00. The deviceinputs are compatible with Standard CMOS outputs; with pullupresistors, they are compatible with LSTTL outputs.• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2 to 6V

• Low Input Current: 1µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 32 FETs or 8 Equivalent Gates

3Y1

1A1

PIN 14 = VCCPIN 7 = GND

LOGIC DIAGRAM

2B1

6Y2

4A2

5B2

8Y3

9A3

10B3

11Y4

12A4

13B4

Y = AB

Pinout: 14–Lead Packages (Top View)

1314 12 11 10 9 8

21 3 4 5 6 7

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GNDDevice Package Shipping

ORDERING INFORMATION

MC74HC00AN PDIP–14 2000 / Box

MC74HC00AD SOIC–14

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55 / Rail

MC74HC00ADR2 SOIC–14 2500 / Reel

MARKINGDIAGRAMS

A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week

MC74HC00ADT TSSOP–14 96 / Rail

MC74HC00ADTR2 TSSOP–14 2500 / Reel

TSSOP–14DT SUFFIXCASE 948G

HC00A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC00ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC00AAWLYWW

L

L

H

H

L

H

L

H

FUNCTION TABLE

Inputs Output

A B

H

H

H

L

Y

MC74HC00A

http://onsemi.com59


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter ÎÎÎÎÎÎÎÎÎÎ

Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ

– 0.5 to + 7.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ

– 0.5 to VCC + 0.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin ÎÎÎÎÎÎÎÎÎÎ

± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

Iout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin ÎÎÎÎÎÎÎÎÎÎ

± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

ICC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins ÎÎÎÎÎÎÎÎÎÎ

± 50 ÎÎÎÎÎÎ

mA


PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†SOIC Package†

TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ

TstgÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature ÎÎÎÎÎÎÎÎÎÎ


CÎÎÎÎÎÎÎÎÎÎÎÎ

TLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 SecondsPlastic DIP, SOIC or TSSOP Package


260

ÎÎÎÎÎÎÎÎÎ

C

*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/C from 65 to 125CSOIC Package: – 7 mW/C from 65 to 125C TSSOP Package: – 6.1 mW/C from 65 to 125C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter ÎÎÎÎÎÎ

Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ

2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vin, VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND) ÎÎÎÎÎÎ

0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types ÎÎÎÎÎÎ

– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns

This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high–impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND (Vin or Vout) VCC.

Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.

MC74HC00A

http://onsemi.com60

DC CHARACTERISTICS (Voltages Referenced to GND)

VCCGuaranteed Limit

Symbol Parameter ConditionVCC

V –55 to 25°C ≤85°C ≤125°C Unit

VIH Minimum High–Level InputVoltage

Vout = 0.1V or VCC –0.1V|Iout| ≤ 20µA

2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V

VIL Maximum Low–Level InputVoltage

Vout = 0.1V or VCC – 0.1V|Iout| ≤ 20µA

2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V

VOH Minimum High–Level OutputVoltage

Vin = VIH or VIL|Iout| ≤ 20µA

2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V

Vin =VIH or VIL |Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA

3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20

VOL Maximum Low–Level OutputVoltage


2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V

Vin = VIH or VIL |Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA

3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40

Iin Maximum Input LeakageCurrent

Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

ICC Maximum Quiescent SupplyCurrent (per Package)

Vin = VCC or GNDIout = 0µA

6.0 1.0 10 40 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL

Maximum Propagation Delay, Input A or B to Output Y(Figures 1 and 2)

2.03.04.56.0

75301513

95401916

110552219

ns

tTLH,tTHL

Maximum Output Transition Time, Any Output(Figures 1 and 2)

2.03.04.56.0

75271513

95321916

110362219

ns

Cin Maximum Input Capacitance 10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the MotorolaHigh–Speed CMOS Data Book (DL129/D).

Typical @ 25 °C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 22 pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theMotorola High–Speed CMOS Data Book (DL129/D).

MC74HC00A

http://onsemi.com61

Figure 1. Switching Waveforms

GND

VCC

OUTPUT Y

INPUTA OR B

CL*

*Includes all probe and jig capacitance

TESTPOINT

90%

50%10%

tTLH

DEVICEUNDERTEST

OUTPUT

Figure 2. Test Circuit

YA

B

Figure 3. Expanded Logic Diagram(1/4 of the Device)

tTHL

90%

50%

10%

tPLH tPHL

tf tr



MC74HC02A/D


The MC74HC02A is identical in pinout to the LS02. The deviceinputs are compatible with standard CMOS outputs; with pullupresistors, they are compatible with LSTTL outputs.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA


• In Compliance with the Requirements Defined by JEDEC StandardNo. 7A


LOGIC DIAGRAM

1Y1

2A1


3B1

Y4

Y = A + B

4Y2

5A2

6B2

10Y3

8A3

9B3

1311

A412

B4

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Y3

A4

B4

Y4

VCC

A3

B3

Y2

B1

A1

Y1

GND

B2

A2

Device Package Shipping




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55 / Rail


MARKINGDIAGRAMS





HC02A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC02ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC02AAWLYWW

FUNCTION TABLE

A

LLHH

Inputs Output

B

LHLH

Y

HLLL

MC74HC02A

http://onsemi.com63


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ


Guaranteed Limit ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test ConditionsÎÎÎÎÎÎÎÎ

VCCVÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎ85CÎÎÎÎÎÎÎÎ

125°CÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–Level InputVoltage


Vout = 0.1 V or VCC – 0.1 V|Iout| 20 µA


2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–Level InputVoltage




2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V


VOHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–Level OutputVoltage


Vin = VIH or VIL|Iout| 20 µA


2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL |Iout| 2.4 mA|Iout| 4.0 mA|Iout| 5.2 mA


3.04.56.0


2.483.985.48


2.343.845.34


2.203.75.2




MC74HC02A

http://onsemi.com64



ÎÎÎÎÎÎ


Guaranteed LimitÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ ÎÎÎ

ÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎ

125°CÎÎÎÎÎÎÎÎÎ

85CÎÎÎÎÎÎÎÎÎÎÎÎ

– 55 to25C


VCCV


Test ConditionsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎÎÎÎÎ

Symbol


VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–Level OutputVoltage




2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

IinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input LeakageCurrent


Vin = VCC or GNDÎÎÎÎÎÎÎÎÎÎÎÎ

6.0ÎÎÎÎÎÎÎÎÎÎÎÎ

± 0.1ÎÎÎÎÎÎÎÎÎ

± 1.0ÎÎÎÎÎÎÎÎÎÎÎÎ


µA


ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent SupplyCurrent (per Package)


Vin = VCC or GND|Iout| = 0 µA


6.0 ÎÎÎÎÎÎÎÎÎÎÎÎ

1.0 ÎÎÎÎÎÎÎÎÎ


40 ÎÎÎÎÎÎÎÎÎ

µA


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


VCCVÎÎÎÎÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎÎ


125CÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


75301513


95401916


110552219


ns


tTLH,tTHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


75301513

ÎÎÎÎÎÎÎÎÎ

95401916


110552219

ÎÎÎÎÎÎÎÎÎ

ns

ÎÎÎÎÎÎÎÎCin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Input Capacitance

ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10

ÎÎÎÎÎÎ10ÎÎÎÎÎÎÎÎ10

ÎÎÎÎÎÎpF


Typical @ 25 °C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)* 22 pF


MC74HC02A

http://onsemi.com65


tf trVCC

GND

90%50%

10%

90%50%

10%

INPUTA OR B

OUTPUT Y

tPHLtPLH

tTLH tTHL *Includes all probe and jig capacitance


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

EXPANDED LOGIC DIAGRAM(1/4 OF THE DEVICE)

Y

A

B



MC74HC03A/D


The MC74HC03A is identical in pinout to the LS03. The deviceinputs are compatible with Standard CMOS outputs; with pullupresistors, they are compatible with LSTTL outputs.

The HC03A NAND gate has, as its outputs, a high–performanceMOS N–Channel transistor. This NAND gate can, therefore, with asuitable pullup resistor, be used in wired–AND applications. Havingthe output characteristic curves given in this data sheet, this device canbe used as an LED driver or in any other application that only requiresa sinking current.• Output Drive Capability: 10 LSTTL Loads With Suitable Pullup

Resistor• Outputs Directly Interface to CMOS, NMOS and TTL






DESIGN GUIDE

Criteria Value Unit

Internal Gate Count* 7.0 ea

Internal Gate Propagation Delay 1.5 ns

Internal Gate Power Dissipation 5.0 µW

Speed Power Product 0.0075 pJ

* Equivalent to a two–input NAND gate

PIN 14 = VCCPIN 7 = GND* Denotes open–drain outputs

LOGIC DIAGRAM

3,6,8,11Y*

1,4,9,12A

2,5,10,13B

OUTPUTPROTECTION

DIODE

VCC


1314 12 11 10 9 8

21 3 4 5 6 7


A1 B1 Y1 A2 B2 Y2 GND





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55 / Rail


MARKINGDIAGRAMS





HC03A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC03ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC03AAWLYWW

L

L

H

H

L

H

L

H

FUNCTION TABLE

Inputs Output

A B

Z

Z

Z

L

Y

Z = High Impedance

MC74HC03A

http://onsemi.com67


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA



Power Dissipation in Still Air Plastic DIP†SOIC Package†

TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ

Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



C


TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



260

ÎÎÎÎÎÎÎÎÎ

C




RECOMMENDED OPERATING CONDITIONSÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

TAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns


VCC Guaranteed Limit

Symbol Parameter ConditionCCV –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA



6.0 1.0 10 40 µA

IOZ Maximum Three–State LeakageCurrent

Output in High–Impedance StateVin = VIL or VIHVout = VCC or GND

6.0 ±0.5 ±5.0 ±10 µA




MC74HC03A

http://onsemi.com68

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLZ,tPZL


2.03.04.56.0

120452420

150603026

180753631

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321916

110362219

ns


Cout Maximum Three–State Output Capacitance(Output in High–Impedance State)

10 10 10 pF



CPD Power Dissipation Capacitance (Per Buffer)* 8.0 pF


MC74HC03A

http://onsemi.com69


CL*


TESTPOINTDEVICE

UNDERTEST

OUTPUT


1kΩ Rpd

VCC

INPUT A90%50%10%

tftr

GND

VCC

OUTPUT Y

tPZL

tTHL

HIGHIMPEDANCE

VOL10%

tPLZ

90%50%10%

VO, OUTPUT VOLTAGE (VOLTS)

0 1 2 3 4 50

5

10

15

20

25

I D, S

INK

CU

RR

ENT

(mA)

Figure 3. Open–Drain Output Characteristics

A1

B1

A2

B2

An

Bn

1/4HC03

1/4HC03

1/4HC03

Y1

Y2

Yn

TYPICALT=25°C

T=25°C

T=85°C

T=125°C

EXPECTED MINIMUM*

VCC=5V


VCC

PULLUPRESISTOR

OUTPUT

OUTPUT = Y1 • Y2 • . . . • Yn= A1B1 • A2B2 • . . . • AnBn

Figure 4. Wired AND

LED1

1/4HC03

LED2

LEDENABLE

VCC+

VR–+

VF–

1/4HC03

VCC

DESIGN EXAMPLECONDITIONS: ID10mA

USING FIGURE NO TAG TYPICALCURVE, at ID=10mA, VDS0.4V

RVCC VF VO

ID

5V 1.7V 0.4V

10mA

USE R = 270Ω

290

Figure 5. LED Driver With Blanking



MC74HC04A/D

High–Performance Silicon–Gate CMOSThe MC74HC04A is identical in pinout to the LS04 and the

MC14069. The device inputs are compatible with Standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.

The device consists of six three–stage inverters.








LOGIC DIAGRAM

Y1A1

A2

A3

A4

A5

A6

Y2

Y3

Y4

Y5

Y6

1

3

5

9

11

13

2

4

6

8

10

12

Y = A


1314 12 11 10 9 8

21 3 4 5 6 7

VCC A6 Y6 A5 Y5 A4 Y4

A1 Y1 A2 Y2 A3 Y3 GND





http://onsemi.com

55 / Rail


MARKINGDIAGRAMS





HC04A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC04ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC04AAWLYWW

L

H

FUNCTION TABLE

Inputs Outputs

A

H

L

Y

MC74HC04A

http://onsemi.com71


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns



MC74HC04A

http://onsemi.com72


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40


Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA



6.0 1.0 10 40 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


2.03.04.56.0

75301513

95401916

110552219

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321916

110362219

ns




CPD Power Dissipation Capacitance (Per Inverter)* 20 pF


MC74HC04A

http://onsemi.com73


GND

VCC

OUTPUT Y

INPUT A

CL*


TESTPOINT

90%

50%10%

tTLH

DEVICEUNDERTEST

OUTPUT


YA

Figure 3. Expanded Logic Diagram(1/6 of the Device Shown)

tTHL

90%

50%

10%

tPLH tPHL

tf tr



MC74HCT04A/D

With LSTTL–Compatible InputsHigh–Performance Silicon–Gate CMOS

The MC74HCT04A may be used as a level converter for interfacingTTL or NMOS outputs to High–Speed CMOS inputs.

The HCT04A is identical in pinout to the LS04.


• TTL/NMOS–Compatible Input Levels


• Operating Voltage Range: 4.5 to 5.5V




LOGIC DIAGRAM

Y1A1

A2

A3

A4

A5

A6

Y2

Y3

Y4

Y5

Y6

1

3

5

9

11

13

2

4

6

8

10

12

Y = A

Pin 14 = VCCPin 7 = GND


1314 12 11 10 9 8

21 3 4 5 6 7





MC74HCT04AN PDIP–14 2000 / Box

MC74HCT04AD SOIC–14

http://onsemi.com

55 / Rail

MC74HCT04ADR2 SOIC–14 2500 / Reel

MARKINGDIAGRAMS


MC74HCT04ADT TSSOP–14 96 / Rail

MC74HCT04ADTR2 TSSOP–14 2500 / Reel


HCT04A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HCT04ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HCT04AAWLYWW

L

H

FUNCTION TABLE

Inputs Outputs

A

H

L

Y

MC74HCT04A

http://onsemi.com75


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ


Storage Temperature Range ÎÎÎÎÎÎÎÎÎÎ






260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: – 10 mW/C from 65 to 125CSOIC Package: – 7 mW/C from 65 to 125CTSSOP Package: – 6.1 mW/C from 65 to 125C



ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ


Operating Temperature Range, All Package Types ÎÎÎÎÎÎ

– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ

tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise/Fall Time (Figure 1) ÎÎÎÎÎÎ

0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns



MC74HCT04A

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VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit


Vout = 0.1V|Iout| ≤ 20µA

4.55.5

2.02.0

2.02.0

2.02.0

V


Vout = VCC – 0.1V|Iout| ≤ 20µA

4.55.5

0.80.8

0.80.8

0.80.8

V


Vin = VIL|Iout| ≤ 20µA

4.55.5

4.45.4

4.45.4

4.45.4

V

Vin = VIL |Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70


Vin = VIH|Iout| ≤ 20µA

4.55.5

0.10.1

0.10.1

0.10.1

V

Vin = VIH |Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40


Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA



5.5 1 10 40 µA

∆ICC Additional Quiescent SupplyCurrent

Vin = 2.4V, Any One InputVi VCC or GND Other Inputs

≥ –55°C 25 to 125°CCurrent Vin = VCC or GND, Other Inputs

Iout = 0µA 5.5 2.9 2.4 mA

1. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Total Supply Current = ICC + Σ∆ICC.

AC CHARACTERISTICS (VCC = 5.0V ±10%, CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit

Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL

Maximum Propagation Delay, Input A to Output Y(Figures 1 and 2)

1517

1921

2226

ns

tTLH,tTHL


15 19 22 ns






MC74HCT04A

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GND

3.0V

OUTPUT Y

INPUT A

CL*


TESTPOINT

90%

1.3V10%

tTLH

DEVICEUNDERTEST

OUTPUT


YA

Figure 3. Expanded Logic Diagram(1/6 of the Device Shown)

tTHL

2.7V

1.3V

0.3V

tPLH tPHL

tf tr



MC74HCU04A/D

High–Performance Silicon–Gate CMOSThe MC74HCU04A is identical in pinout to the LS04 and the

MC14069UB. The device inputs are compatible with standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.

This device consists of six single–stage inverters. These invertersare well suited for use as oscillators, pulse shapers, and in many otherapplications requiring a high–input impedance amplifier. For digitalapplications, the HC04A is recommended.



• Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in OscillatorConfigurations

• Low Input Current: 1 µA




LOGIC DIAGRAM

Y1A1

A2

A3

A4

A5

A6

Y2

Y3

Y4

Y5

Y6

1

3

5

9

11

13

2

4

6

8

10

12

Y = A


FUNCTION TABLE

InputsA

LH

OutputsY

HL Device Package Shipping


MC74HCU04AN PDIP–14 2000 / Box

MC74HCU04AD SOIC–14

http://onsemi.com

55 / Rail

MC74HCU04ADR2 SOIC–14 2500 / Reel

MARKINGDIAGRAMS


MC74HCU04ADT TSSOP–14 96 / Rail

MC74HCU04ADTR2 TSSOP–14 2500 / Reel


HCU04A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HCU04ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HCU04AAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Y5

A5

Y6

A6

VCC

Y4

A4

Y2

A2

Y1

A1

GND

Y3

A3

MC74HCU04A

http://onsemi.com79


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ






Lead Temperature, 1 mm from case for 10 SecondsPlastic DIP, SOIC or TSSOP Package


260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: –10mW/C from 65 to 125CSOIC Package: –7mW/C from 65 to 125CTSSOP Package: – 6.1 mW/C from 65 to 125C



ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ


Input Rise and Fall Time (Figure 1) ÎÎÎÎÎÎ

— ÎÎÎÎ

NoLimitÎÎÎÎÎÎ

ns



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test ConditionsÎÎÎÎÎÎÎÎÎÎÎÎ


– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit





Vout = 0.5 V*|Iout| 20 µA


2.03.04.56.0


1.72.53.64.8


1.72.53.64.8


l.72.53.64.8


V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



Vout = VCC – 0.5 V*|Iout| 20 µA


2.03.04.56.0


0.30.50.81.1

ÎÎÎÎÎÎÎÎÎ

0.30.50.81.1


0.30.50.81.1

ÎÎÎÎÎÎÎÎÎ

V


VOHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



Vin = GND|Iout| 20 µA


2.04.56.0


1.84.05.5


1.84.05.5


1.84.05.5


V




Vin = GND |Iout| 2.4 mA|Iout| 4.0 mA|Iout| 5.2 mA


3.04.56.0


2.363.865.36

ÎÎÎÎÎÎÎÎÎ

2.263.765.26


2.203.705.20


ÎÎÎÎÎÎÎÎ




Vin = VCC|Iout| 20 µA


2.04.56.0


0.20.50.5

ÎÎÎÎÎÎÎÎÎ

0.20.50.5


0.20.50.5

ÎÎÎÎÎÎÎÎÎ

V




Vin = VCC |Iout| 2.4 mA|Iout| 4.0 mA|Iout| 5.2 mA


3.04.56.0


0.320.320.32


0.320.370.37


0.320.400.40




MC74HCU04A

http://onsemi.com80



ÎÎÎÎÎÎ






ÎÎÎÎÎÎ




– 55 to25C


VCCV




SymbolÎÎÎÎÎÎÎÎÎÎÎÎ

Iin









µA





Vin = VCC or GNDIout = 0 µA



1ÎÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎÎÎÎÎ

40ÎÎÎÎÎÎÎÎÎ

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).*For VCC = 2.0 V, Vout = 0.2 V or VCC – 0.2 V.


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)



ÎÎÎÎÎÎÎÎ


Guaranteed Limit ÎÎÎÎÎÎÎÎÎÎÎ


Symbol


Parameter


VCCV


– 55 to25C

ÎÎÎÎÎÎÎÎÎ 85C


125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHL




2.03.04.56.0


70401412


90451815


105502118


ns


tTLH,tTHL




2.03.04.56.0


75271513


95321916


110362219


ns


Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance ÎÎÎÎÎÎÎÎ


10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF

NOTES:1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).




MC74HCU04A

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trVCC

GND

90%50%

10%

90%50%

10%INPUT A

OUTPUT Y

tPHL tPLH

tTHL tTLH *Includes all probe and jig capacitance


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

LOGIC DETAIL(1/6 of Device Shown)

tf

A

VCC

Y

MC74HCU04A

http://onsemi.com82

Crystal Oscillator Stable RC Oscillator

Schmitt Trigger High Input Impedance Single–Stage Amplifierwith a 2 to 6 V Supply Range

Multi–Stage Amplifier LED Driver

For reduced power supply current, use high–efficiency LEDssuch as the Hewlett–Packard HLMP series or equivalent.

R2

1/6 HCU04A

C1

R2 > > R1C1 < C2

Vout

C2

R1

R2 R1

C

1/6 HCU04A1/6 HCU04A1/6 HCU04A

Vout

R2

R1Vin Vout

1/6 HCU04A 1/6 HCU04AR2 > 6R1

VCC

INPUT OUTPUT

1 M

1 M

1/6 HCU04A

VCC

INPUT OUTPUT

1/6 HCU04A 1/6 HCU04A 1/6 HCU04A

+ V

1/6 HCU04A

TYPICAL APPLICATIONS



MC74HC08A/D










3Y1

1A1


LOGIC DIAGRAM

2B1

6Y2

4A2

5B2

8Y3

9A3

10B3

11Y4

12A4

13B4

Y = AB


1314 12 11 10 9 8

21 3 4 5 6 7


A1 B1 Y1 A2 B2 Y2 GND





http://onsemi.com

55 / Rail


MARKINGDIAGRAMS





HC08A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC08ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC08AAWLYWW

L

L

H

H

L

H

L

H

FUNCTION TABLE

Inputs Output

A B

L

L

L

H

Y

MC74HC08A

http://onsemi.com84


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns



MC74HC08A

http://onsemi.com85


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40


Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA



6.0 1.0 10 40 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


2.03.04.56.0

75301513

95401916

110552219

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321916

110362219

ns






MC74HC08A

http://onsemi.com86


OUTPUT Y

INPUTA OR B

CL*


TESTPOINT

90%

50%10%

tTLH

DEVICEUNDERTEST

OUTPUT


YA

B


tTHL

tPLH tPHL

tr tf

GND

VCC90%

50%10%



MC74HC14A/D


The MC74HC14A is identical in pinout to the LS14, LS04 and theHC04. The device inputs are compatible with Standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.

The HC14A is useful to “square up” slow input rise and fall times.Due to hysteresis voltage of the Schmitt trigger, the HC14A findsapplications in noisy environments.• Output Drive Capability: 10 LSTTL Loads







LOGIC DIAGRAM

Y1A1

A2

A3

A4

A5

A6

Y2

Y3

Y4

Y5

Y6

1

3

5

9

11

13

2

4

6

8

10

12

Y = A

Pin 14 = VCCPin 7 = GND


1314 12 11 10 9 8

21 3 4 5 6 7







http://onsemi.com

55 / Rail


MARKINGDIAGRAMS





HC14A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC14ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC14AAWLYWW

L

H

FUNCTION TABLE

Inputs Outputs

A

H

L

Y

MC74HC14A

http://onsemi.com88


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2.0 ÎÎÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vin, VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced toGND)

ÎÎÎÎÎÎ

0 ÎÎÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

TAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package TypesÎÎÎÎÎÎ

– 55ÎÎÎÎÎÎ

+ 125ÎÎÎÎÎÎ

CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise/Fall Time VCC = 2.0 V(Figure 1) VCC = 4.5 V

VCC = 6.0 V


000


No Limit*No Limit*No Limit*


ns

*When Vin = 50% VCC, ICC > 1mA



MC74HC14A

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VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit

VT+ max Maximum Positive–Going InputThreshold Voltage(Figure 3)


2.03.04.56.0

1.502.153.154.20

1.502.153.154.20

1.502.153.154.20

V

VT+ min Minimum Positive–Going InputThreshold Voltage(Figure 3)


2.03.04.56.0

1.01.52.33.0

0.951.452.252.95

0.951.452.252.95

V

VT– max Maximum Negative–Going InputThreshold Voltage(Figure 3)


2.03.04.56.0

0.91.42.02.6

0.951.452.052.65

0.951.452.052.65

V

VT– min Minimum Negative–Going InputThreshold Voltage(Figure 3)


2.03.04.56.0

0.30.50.91.2

0.30.50.91.2

0.30.50.91.2

V

VHmaxNote 2

Maximum Hysteresis Voltage(Figure 3)


2.03.04.56.0

1.201.652.253.00

1.201.652.253.00

1.201.652.253.00

V

VHminNote 2

Minimum Hysteresis Voltage(Figure 3)


2.03.04.56.0

0.200.250.400.50

0.200.250.400.50

0.200.250.400.50

V


Vin ≤ VT– min|Iout| ≤ 20µA

2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V

Vin ≤ VT– min |Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA

3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20


Vin ≥ VT+ max|Iout| ≤ 20µA

2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V

Vin ≥ VT+ max |Iout| ≤ 2.4mA|Iout| ≤ 4.0mA|Iout| ≤ 5.2mA

3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40


Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA



6.0 1.0 10 40 µA

1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the MotorolaHigh–Speed CMOS Data Book (DL129/D).

2. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) – (VT– min).

MC74HC14A

http://onsemi.com90


VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


2.03.04.56.0

75301513

95401916

110552219

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321916

110362219

ns







GND

VCC

OUTPUT Y

INPUT A

CL*


TESTPOINT

90%

50%10%

tTLH

DEVICEUNDERTEST

OUTPUT


tTHL

90%

50%

10%

tPLH tPHL

tf tr

MC74HC14A

http://onsemi.com91

VHtyp

Figure 3. Typical Input Threshold, V T+, VT– versus Power Supply Voltage

Figure 4. Typical Schmitt–Trigger Applications

VCC, POWER SUPPLY VOLTAGE (VOLTS)2 3 4 5 6

1

2

3

4

V T, TYP

ICAL

INPU

T TH

RES

HO

LD V

OLT

AGE

(VO

LTS

VHtyp = (VT+ typ) – (VT– typ)

(VT+)

(VT–)

VH

Vin

Vout

VCC

VT+VT–

GND

VOH

VOL

VH

Vin

Vout

VCC

VT+VT–

GND

VOH

VOL

(a) A Schmitt–Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt–Trigger Offers Maximum Noise Immunity

YA



MC74HCT14A/D


The MC74HCT14A may be used as a level converter for interfacingTTL or NMOS outputs to high–speed CMOS inputs.

The HCT14A is identical in pinout to the LS14.The HCT14A is useful to “square up” slow input rise and fall times.

Due to the hysteresis voltage of the Schmitt trigger, the HCT14A findsapplications in noisy environments.








LOGIC DIAGRAM


Y = A

A11 2

Y1

A23 4

Y2

A35 6

Y3

A49 8

Y4

A511 10

Y5

A613 12

Y6

FUNCTION TABLE

InputA

LH

OutputY

HL





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55 / Rail


MARKINGDIAGRAMS


1

14PDIP–14

N SUFFIXCASE 646

MC74HCT14ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HCT14AAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Y5

A5

Y6

A6

VCC

Y4

A4

Y2

A2

Y1

A1

GND

Y3

A3

MC74HCT14A

http://onsemi.com93


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



750500ÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎTstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎStorage Temperature

ÎÎÎÎÎÎÎÎÎÎ– 65 to + 150

ÎÎÎÎÎÎCÎÎÎÎ

ÎÎÎÎÎÎÎÎ


Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP or SOIC Package)


260

ÎÎÎÎÎÎÎÎÎ

CC

*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions

†Derating — Plastic DIP: – 10 mW/C from 65 to 125CSOIC Package: – 7 mW/C from 65 to 125C





Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ



— ÎÎÎÎ

*ÎÎÎÎÎÎ

ns

*No Limit when Vin 50% VCC, ICC > 1 mA.


DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎ




Temperature Limit ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ

VCC


– 55 to25C


85C


125C

ÎÎÎÎÎÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎParameter ÎÎÎÎÎÎÎÎTest Conditions ÎÎÎ

CCVoltsÎÎÎMinÎÎÎMaxÎÎÎMinÎÎÎMaxÎÎÎMinÎÎÎMaxÎÎUnitÎÎÎÎ

ÎÎÎÎÎÎÎÎ

VT+ maxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Positive–GoingInput Threshold Voltage



ÎÎÎÎÎÎÎÎÎ

4.55.5

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.92.1

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.92.1

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.92.1

ÎÎÎÎÎÎ

V


VT+ minÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Positive–GoingInput Threshold Voltage



ÎÎÎÎÎÎÎÎÎ

4.55.5

ÎÎÎÎÎÎÎÎÎ

1.21.4

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.21.4

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.21.4

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VT– maxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎ

4.55.5ÎÎÎÎÎÎÎÎÎÎÎÎ



1.21.4ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

VT– minÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎÎ

4.55.5

ÎÎÎÎÎÎÎÎÎ

0.50.6

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.50.6

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.50.6

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

VH maxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum HysteresisVoltage



ÎÎÎÎÎÎÎÎÎ

4.55.5ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

1.41.5ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

VH minÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum HysteresisVoltage



ÎÎÎÎÎÎ

4.55.5ÎÎÎÎÎÎ



0.40 4ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

VOHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–LevelOutput Voltage


Vin < VT–min|Iout| 20 µA

ÎÎÎÎÎÎÎÎÎ

4.55.5

ÎÎÎÎÎÎÎÎÎ

4.45.4

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

4.45.4

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

4.45.4

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



Vin < VT–min|Iout| 4.0 mA

ÎÎÎÎÎÎ

4.5ÎÎÎÎÎÎ



3.7ÎÎÎÎÎÎÎÎÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).(continued)



MC74HCT14A

http://onsemi.com94


DC CHARACTERISTICS (Voltages Referenced to GND) – continued

ÎÎÎÎÎÎÎÎ




Temperature Limit ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ

VCC


– 55 to25CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

85CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

125CÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions ÎÎÎÎÎÎ

VCCVoltsÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–LevelOutput Voltage


Vin ≥ VT+max|Iout| 20 µA

ÎÎÎÎÎÎ




0.10.1ÎÎÎÎ

V




Vin ≥ VT+max|Iout| 4.0 mA

ÎÎÎÎÎÎÎÎÎ

4.5ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum InputLeakage Current


Vin = VCC or GND ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

± 1.0ÎÎÎÎÎÎ

µA


ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum QuiescentSupply Current(per package)



ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

40 ÎÎÎÎÎÎ

µA




ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


≥ – 55CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

25C to125C

ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

∆ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Additional QuiescentSupply Current


Vin = 2.4 V, Any One InputVin = VCC or GND, Other Inputslout = 0 µA

ÎÎÎÎÎÎÎÎÎ



2.9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎ

mA


AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ


Guaranteed LimitÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎÎ


– 55 to25C


85C


125C


ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



MinÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎ


tPLH,tPHL


Maximum PropagationDelay, Input A to Output Y(L to H)


VCC = 5.0 V ± 10%CL = 50 pF, Input tr = tf = 6.0 ns


Fig.1 & 2


ÎÎÎÎÎÎÎÎ





48ÎÎÎÎÎÎÎÎ

ns


tTLH,tTHL


Maximum OutputTransition Time.Any Output


VCC = 5.0 V ± 10%CL = 50 pF, Input tr = tf = 6.0 ns


Fig.1 & 2


ÎÎÎÎÎÎÎÎ





22ÎÎÎÎÎÎÎÎ

ns






CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 1. Switching Waveforms Figure 2. Test Circuit

INPUT A

OUTPUT Y

tf tr3 V

GNDtPHLtPLH

tTLH tTHL

2.7 V1.3 V0.3 V

90%1.3 V10%



MC74HC32A/D










3Y1

1A1


LOGIC DIAGRAM

2B1

6Y2

4A2

5B2

8Y3

9A3

10B3

11Y4

12A4

13B4

Y = A+B


1314 12 11 10 9 8

21 3 4 5 6 7


A1 B1 Y1 A2 B2 Y2 GNDDevice Package Shipping




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55 / Rail


MARKINGDIAGRAMS





HC32A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC32ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC32AAWLYWW

L

L

H

H

L

H

L

H

FUNCTION TABLE

Inputs Output

A B

L

H

H

H

Y

MC74HC32A

http://onsemi.com96


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns



MC74HC32A

http://onsemi.com97


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40


Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA



6.0 1.0 10 40 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


2.03.04.56.0

75301513

95401916

110552219

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321916

110362219

ns






MC74HC32A

http://onsemi.com98


OUTPUT Y

INPUTA OR B

CL*


TESTPOINT

90%

50%10%

tTLH

DEVICEUNDERTEST

OUTPUT


Y

A

B


tTHL

tPLH tPHL

tr tf

GND

VCC90%

50%10%



MC74HC74A/D



This device consists of two D flip–flops with individual Set, Reset,and Clock inputs. Information at a D–input is transferred to thecorresponding Q output on the next positive going edge of the clockinput. Both Q and Q outputs are available from each flip–flop. The Setand Reset inputs are asynchronous.








LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

1

2

3

4

13

12

11

10

5

6

9

8

Q1

Q1

Q2

Q2

PIN 14 = VCC PIN 7 = GND

FUNCTION TABLE

Inputs Outputs

Set Reset Clock Data Q Q

L H X X H LH L X X L HL L X X H* H*H H H H LH H L L HH H L X No ChangeH H H X No ChangeH H X No Change

*Both outputs will remain high as long as Set and Reset are low, but the outputstates are unpredictable if Set and Reset go high simultaneously.





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MARKINGDIAGRAMS





HC74A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC74ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC74AAWLYWW

PIN ASSIGNMENT

SET 1

CLOCK 1

DATA 1

RESET 1

11

12

13

14

8

9

105

4

3

2

1

7

6

SET 2

CLOCK 2

DATA 2

RESET 2

VCC

Q2

Q2

GND

Q1

Q1

MC74HC74A

http://onsemi.com100


MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C



Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP, SOIC or TSSOP Package)


260300

ÎÎÎÎÎÎÎÎÎ

C






ParameterÎÎÎÎÎÎ

MinÎÎÎÎ

MaxÎÎÎÎÎÎ




2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V(Figures 1, 2, 3) VCC = 3.0 V

VCC = 4.5 VVCC = 6.0 V


0000

ÎÎÎÎÎÎÎÎ

1000600500400


ns




ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit


ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2

ÎÎÎÎÎÎÎÎÎ



MC74HC74A



ÎÎÎÎÎÎ

Unit


Guaranteed LimitÎÎÎÎÎÎÎÎVCC

V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎ


125CÎÎÎÎÎÎ 85C

ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV


Test ConditionsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4


ÎÎÎÎÎÎÎÎ




Vin = VCC or GND ÎÎÎÎÎÎÎÎÎÎÎÎ


± 0.1 ÎÎÎÎÎÎÎÎÎ



µA

ÎÎÎÎÎÎÎÎ

ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

6.0 ÎÎÎÎÎÎÎÎ

2.0 ÎÎÎÎÎÎ

20 ÎÎÎÎÎÎÎÎ

80 ÎÎÎÎÎÎ

µA



ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


fmax ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)(Figures 1 and 4)


2.03.04.56.0


6.0153035


4.8102428


4.08.02024


MHz


tPLH,tPHL


Maximum Propagation Delay, Clock to Q or Q(Figures 1 and 4)


2.03.04.56.0


100752017


125902521


1501203026


ns


tPLH,tPHL


Maximum Propagation Delay, Set or Reset to Q or Q(Figures 2 and 4)


2.03.04.56.0


105802118


130952622


1601303227


ns


tTLH,tTHL




2.03.04.56.0


75301513


95401916


110552219


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF



CPD Power Dissipation Capacitance (Per Flip–Flop)* 32 pF


MC74HC74A


TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎSymbol




– 55 to25C

ÎÎÎÎÎÎ 85CÎÎÎÎÎÎÎÎ

125CÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock(Figure 3)


2.03.04.56.0


80351614


100452017


120552420


ns


thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data(Figure 3)


2.03.04.56.0


3.03.03.03.0


3.03.03.03.0


3.03.03.03.0


ns


trec ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Set or Reset Inactive to Clock(Figure 2)


2.03.04.56.0


8.08.08.08.0


8.08.08.08.0


8.08.08.08.0


ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock(Figure 1)


2.03.04.56.0


60251210


75301513


90401815


ns



Minimum Pulse Width, Set or Reset(Figure 2)


2.03.04.56.0


60251210


75301513


90401815


ns


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times(Figures 1, 2, 3)


2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns

MC74HC74A


SWITCHING WAVEFORMS

Figure 1.

Figure 2.

50%

50%

50%

50%

VCC

VCC

GND

GND

SET ORRESET

Q OR Q

Q OR Q

CLOCK

tPLH

tPHL

50%

DATA

CLOCK

VCC

VCC

GND

Figure 3.

VALID

GNDtsu th

trec

tw

EXPANDED LOGIC DIAGRAM

SET

DATA

RESET

4, 10

2, 12

1, 13

CLOCK3, 11

5, 9

6, 8

Q

Q


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 4.

1/fmax

CLOCK

Q or Q

tf trVCC

GND

90%50%

10%

90%50%

10%

tPLH tPHL

tTLH tTHL

tw

50%



MC74HCT74A/D


The MC74HCT74A is identical in pinout to the LS74. This devicemay be used as a level converter for interfacing TTL or NMOS outputsto High Speed CMOS inputs.

This device consists of two D flip–flops with individual Set, Reset,and Clock inputs. Information at a D–input is transferred to thecorresponding Q output on the next positive going edge of the clockinput. Both Q and Q outputs are available from each flip–flop. The Setand Reset inputs are asynchronous.


• TTL NMOS Compatible Input Levels






LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

1

2

3

4

13

12

11

10

5

6

9

8

Q1

Q1

Q2

Q2

PIN 14 = VCC PIN 7 = GND


Design Criteria ÎÎÎÎÎÎÎÎ

Value ÎÎÎÎÎÎ

Units


Internal Gate Count* ÎÎÎÎÎÎÎÎ

34 ÎÎÎÎÎÎ

ea.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay

ÎÎÎÎÎÎÎÎ1.5

ÎÎÎÎÎÎnsÎÎÎÎÎÎÎÎÎÎ


Internal Gate Power Dissipation


5.0

ÎÎÎÎÎÎÎÎÎ

µW


Speed Power Product ÎÎÎÎÎÎÎÎ

.0075 ÎÎÎÎÎÎ

pJ

*Equivalent to a two–input NAND gate.Device Package Shipping




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55 / Rail


MARKINGDIAGRAMS


1

14PDIP–14

N SUFFIXCASE 646

MC74HCT74ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HCT74AAWLYWW

FUNCTION TABLE

PIN ASSIGNMENT

Inputs Outputs

Set Reset Clock Data Q Q

L H X X H LH L X X L HL L X X H* H*H H H H LH H L L HH H L X No ChangeH H H X No ChangeH H X No Change

*Both outputs will remain high as long as Set and Reset are low, but the output states are unpredict-able if Set and Reset go high simultaneously.

SET 1

CLOCK 1

DATA 1

RESET 1

11

12

13

14

8

9

105

4

3

2

1

7

6

SET 2

CLOCK 2

DATA 2

RESET 2

VCC

Q2

Q2

GND

Q1

Q1

MC74HCT74A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA






mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ

TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



260ÎÎÎÎÎÎ

C


†Derating — Plastic DIP: –10mW/C from 65 to 125CSOIC Package: –7mW/C from 65 to 125C


RECOMMENDED OPERATING CONDITIONSÎÎÎÎÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎÎÎÎ


VCC


DC Supply Voltage (Referenced to GND)ÎÎÎÎÎÎÎÎÎ

4.5ÎÎÎÎÎÎ


VÎÎÎÎÎÎÎÎVin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ0ÎÎÎÎVCC

ÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎTA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOperating Temperature, All Package Types

ÎÎÎÎÎÎ– 55ÎÎÎÎ+ 125ÎÎÎÎÎÎCÎÎÎÎ

ÎÎÎÎtr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Rise and Fall Time (Figure 1)

ÎÎÎÎÎÎ0ÎÎÎÎ500ÎÎÎÎÎÎns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ

V







4.55.5


0.80.8

ÎÎÎÎÎÎÎÎÎ

0.80.8


0.80.8

ÎÎÎÎÎÎÎÎÎ

V







4.55.5


4.45.4

ÎÎÎÎÎÎÎÎÎ

4.45.4


4.45.4

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL|Iout| 4.0 mA


4.5


3.98

ÎÎÎÎÎÎÎÎÎ

3.84


3.7


ÎÎÎÎ

VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ

V






4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4


ÎÎÎÎÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ








µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


2.0 ÎÎÎÎÎÎ

20 ÎÎÎÎÎÎÎÎ

80 ÎÎÎÎÎÎ

µA

ÎÎÎÎÎÎÎÎ

∆ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Additional Quiescent SupplyCurrent


Vin = 2.4 V, Any One InputVin = VCC or GND Other Inputs

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

≥–55CÎÎÎÎÎÎÎÎÎÎÎÎ

25C to 125CÎÎÎÎÎÎÎÎÎÎ


Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND, Other In utslout = 0 µA

ÎÎÎÎÎÎÎÎ5.5

ÎÎÎÎÎÎÎÎ2.9

ÎÎÎÎÎÎÎÎÎÎÎÎ2.4

ÎÎÎÎÎÎmA




MC74HCT74A


AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol Parameter– 55 to25C 85C 125C Unit


fmax ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

30 ÎÎÎÎÎÎÎÎ

24 ÎÎÎÎÎÎÎÎ

20 ÎÎÎÎÎÎ

MHz


tPLH,tPHL







ns


tPLH,tPHL


Maximum Propagation Delay, Set or Reset to Q or Q(Figures 2 and 4)





ns


tTLH,tTHL







ns


Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF



CPD Power Dissipation Capacitance (Per Enabled Output)* 32 pF



TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎ



Guaranteed Limit ÎÎÎÎÎÎÎÎ



– 55 to25C


85CÎÎÎÎÎÎÎÎÎÎ 125C

ÎÎÎÎÎÎÎÎ

ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Fig.ÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎ

UnitsÎÎÎÎÎÎÎÎ

tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to ClockÎÎÎÎÎÎ

3ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ

thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to DataÎÎÎÎÎÎ

3ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ

trecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Set or Reset Inactive to ClockÎÎÎÎÎÎ

2ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ

twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, ClockÎÎÎÎÎÎ

1ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ


Minimum Pulse Width, Set or ResetÎÎÎÎÎÎ

2ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ

tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall TimesÎÎÎÎÎÎ




500ÎÎÎÎ

ns

MC74HCT74A


SWITCHING WAVEFORMS

1/fmax

Figure 1.

CLOCK

Q OR Q

tftr3 V

GND

2.7 V1.3 V

0.3 V

90%1.3 V

10%

tPLH tPHL

tTLH tTHL

tw

Figure 2.

GNDSET ORRESET

Q OR Q

Q OR Q

CLOCK

tPLH

tPHL

DATA

CLOCK

Figure 3.

VALID

tsu th

trec

tw


SET

DATA

RESET

4, 10

2, 12

1, 13

CLOCK3, 11

5, 9

6, 8

Q

Q


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 4.

3 V

GND

3 V

1.3 V

1.3 V

1.3 V

1.3 V

GND

3 V

GND

3 V

1.3 V

1.3 V



MC74HC86A/D





• Operating Voltage Range: 2 to 6 V





LOGIC DIAGRAM

Y1

Y2

Y3

Y4

A1

B1

A2

B2

A3

B3

A4

B4

1

2

4

5

9

10

12

13

3

6

8

11


Y = A ⊕ B

= AB + AB

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

B3

Y4

A4

B4

VCC

Y3

A3

A2

Y1

B1

A1

GND

Y2

B2





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55 / Rail


MARKINGDIAGRAMS





HC86A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC86ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC86AAWLYWW

FUNCTION TABLE

A

LLHH

Inputs Output

B

LHLH

Y

LHHL

MC74HC86A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48


2.343.845.34


2.203.705.20




MC74HC86A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎ




– 55 to25C


VCCV





VOL






2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎÎÎÎÎ









µA











µA


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t, = tf = 6 ns)



ÎÎÎÎÎÎÎÎ




Symbol


Parameter



– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHL




2.03.04.56.0


100802017


125902521


1501103126


ns


tTLH,tTHL




2.03.04.56.0


75301513


95401916


110552219


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF





MC74HC86A



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 1. Switching Waveforms Figure 2. Test Circuit

OUTPUT Y

INPUTA OR B

90%

50%10%

tTLH tTHL

tPLH tPHL

tr tf

GND

VCC90%50%

10%

A

B

Y

EXPANDED LOGIC DIAGRAM(1/4 of Device)



MC74HC125A/D


The MC74HC125A and MC74HC126A are identical in pinout tothe LS125 and LS126. The device inputs are compatible with standardCMOS outputs; with pullup resistors, they are compatible withLSTTL outputs.

The HC125A and HC126A noninverting buffers are designed to beused with 3–state memory address drivers, clock drivers, and otherbus–oriented systems. The devices have four separate output enablesthat are active–low (HC125A) or active–high (HC126A).







• Chip Complexity: 72 FETs or 18 Equivalent GatesLOGIC DIAGRAM

HC125AActive–Low Output Enables

HC126AActive–High Output Enables

Y1

Y2

Y4

3

6

8

11

13

12

10

9

4

5

1

2A1

OE1

A2

OE2

A3

OE3

A4

OE4


A1

OE1

A2

OE2

A3

OE3

A4

OE4

Y3

Y1

Y2

Y4

Y3

13

12

10

9

4

5

1

2 3

6

8

11

FUNCTION TABLE

HC125A

Inputs Output

A OE Y

H L HL L LX H Z

HC126A

Inputs Output

A OE Y

H H HL H LX L Z



MC74HC12xAN PDIP–14 2000 / Box

MC74HC12xAD SOIC–14

http://onsemi.com

55 / Rail

MC74HC12xADR2 SOIC–14 2500 / Reel

MARKINGDIAGRAMS


MC74HC12xADT TSSOP–14 96 / Rail

MC74HC12xADTR2 TSSOP–14 2500 / Reel


HC12xAALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC12xANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC12xAAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OE3

Y4

A4

OE4

VCC

Y3

A3

OE2

Y1

A1

OE1

GND

Y2

A2

MC74HC125A, MC74HC126A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎVout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Output Voltage (Referenced to GND) ÎÎÎÎÎ– 0.5 to VCC + 0.5ÎÎÎVÎÎÎÎÎÎÎÎIin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Input Current, per Pin

ÎÎÎÎÎÎÎÎÎÎ± 20

ÎÎÎÎÎÎmAÎÎÎÎ

ÎÎÎÎIoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Output Current, per Pin



ÎÎÎÎICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND PinsÎÎÎÎÎÎÎÎÎÎ

± 75ÎÎÎÎÎÎ

mAÎÎÎÎÎÎÎÎÎÎÎÎ

PDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW





ÎÎÎÎÎÎÎÎ




260

ÎÎÎÎÎÎÎÎÎ

C




RECOMMENDED OPERATING CONDITIONSÎÎÎÎÎÎÎÎSymbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎMinÎÎÎÎMaxÎÎÎÎÎÎUnitÎÎÎÎ

ÎÎÎÎVCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)ÎÎÎÎÎÎ

2.0ÎÎÎÎ

6.0ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎÎÎÎÎ

Vin, VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage(Referenced to GND)

ÎÎÎÎÎÎÎÎÎ

0ÎÎÎÎÎÎ

VCCÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit





Vout = VCC – 0.1 V|Iout| 20 µA


2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V





Vout = 0.1 V|Iout| 20 µA


2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V





Vin = VIH|Iout| 20 µA


2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH |Iout| 3.6 mA|Iout| 6.0 mA|Iout| 7.8 mA


3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ




Vin = VIL|Iout| 20 µA


2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIL |Iout| 3.6 mA|Iout| 6.0 mA|Iout| 7.8 mA


3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ






ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA


IOZÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three–StateLeakage Current







± 10 ÎÎÎÎÎÎÎÎÎ

µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHL




2.03.04.56.0


90361815


115452320


135602723


ns


tPLZ,tPHZ


Maximum Propagation Delay, Output Enable to Y(Figures 2 and 4)


2.03.04.56.0


120452420


150603026


180803631


ns


tPZL,tPZH


Maximum Propagation Delay, Output Enable to Y(Figures 2 and 4)


2.03.04.56.0


90361815


115452320


135602723


ns


tTLH,tTHL




2.03.04.56.0


60221210

ÎÎÎÎÎÎÎÎÎ

75281513


90341815

ÎÎÎÎÎÎÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎCin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Input Capacitance

ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10


ÎÎÎÎÎÎpFÎÎÎÎÎ


Cout


Maximum Three–State Output Capacitance(Output in High–Impedance State)


—ÎÎÎÎÎÎÎÎÎÎÎÎ




pF







SWITCHING WAVEFORMS

Figure 1.

Figure 2.

OUTPUT Y

50%

50%

50%

50%90%

10%

VCC

VCC

GND

GND

HIGHIMPEDANCE

VOL

VOH

OUTPUT Y

OUTPUT Y

OE (HC125A)

OE (HC126A)

tPZL tPLZ

tPZH tPHZ


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT




OUTPUT

TEST POINT

CL *

1 kΩ CONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ and tPZH.

DEVICEUNDERTEST

HIGHIMPEDANCE

90%

10%50%

90%50%

10%

VCC

GND

tftr

tPLH tPHL

tTLH tTHL

INPUT A

HC125A(1/4 OF THE DEVICE)

HC126A(1/4 OF THE DEVICE)

OE

A

VCC

Y

OE

A

VCC

Y



MC74HC132A/D

! High–Performance Silicon–Gate CMOS


The HC132A can be used to enhance noise immunity or to square upslowly changing waveforms.








LOGIC DIAGRAM

A1

B1

Y13

2

1


Y = AB

A2

B2

Y26

5

4

A3

B3

Y38

10

9

A4

B4

Y411

13

12

FUNCTION TABLE

Inputs Output

A B Y

L L HL H HH L HH H L





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55 / Rail


MARKINGDIAGRAMS


1

14PDIP–14

N SUFFIXCASE 646

MC74HC132ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC132AAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

B3

Y4

A4

B4

VCC

Y3

A3

A2

Y1

B1

A1

GND

Y2

B2

MC74HC132A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mAÎÎÎÎÎÎÎÎICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Supply Current, VCC and GND Pins



ÎÎÎÎÎÎÎÎ




750500

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C





260

ÎÎÎÎÎÎÎÎÎ

C







ÎÎÎÎVCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2.0ÎÎÎÎ

6.0ÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎÎ

0ÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise and Fall Time (Figure 1) ÎÎÎÎÎÎÎÎÎ

— ÎÎÎÎÎÎ

nolimit*ÎÎÎÎÎÎÎÎÎ

ns

*When Vin 0.5 VCC, ICC >> quiescent current.


ÎÎÎÎÎÎÎÎ







Test ConditionsÎÎÎÎÎÎ


25CÎÎÎÎÎÎÎÎ

– 40C to+ 85CÎÎÎÎÎÎÎÎ

– 55C to + 125CÎÎÎÎÎÎ


VT+ maxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


(Figure 3)




2.04.56.0


1.53.154.2


1.53.154.2


1.53.154.2


V


VT+ minÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


(Figure 3)


Vout = 0.1 V|Iout| 20 µA ÎÎÎ

ÎÎÎÎÎÎ

2.04.56.0


1.02.33.0


0.952.252.95


0.952.252.95

ÎÎÎÎÎÎÎÎÎ

V


VT– maxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Negative–GoingInput Threshold Voltage

(Figure 3)



ÎÎÎÎÎÎÎÎÎ

2.04.56.0


0.92.02.6


0.952.052.65


0.952.052.65

ÎÎÎÎÎÎÎÎÎ

V


VT– minÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Negative–GoingInput Threshold Voltage

(Figure 3)



ÎÎÎÎÎÎÎÎÎ

2.04.56.0


0.30.91.2


0.30.91.2


0.30.91.2

ÎÎÎÎÎÎÎÎÎ

V


VHmaxNote 2


Maximum Hysteresis Voltage(Figure 3)




2.04.56.0


1.22.253.0


1.22.253.0


1.22.253.0


V


VHminNote 2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hysteresis Voltage(Figure 3)



ÎÎÎÎÎÎÎÎÎ

2.04.56.0


0.20.40.5


0.20.40.5


0.20.40.5

ÎÎÎÎÎÎÎÎÎ

V

NOTE: 1. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) + (VT– min).NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).



MC74HC132A



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ





– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit





VinVT– min or VT+ max|Iout| 20 µA


2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V




Vin–VT– min or VT+ max|Iout| 4.0 mA|Iout| 5.2 mA


4.56.0


3.985.48

ÎÎÎÎÎÎÎÎÎ

3.845.34


3.75.2


ÎÎÎÎÎÎÎÎ




Vin ≥VT+ max|Iout| 20 µA


2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V




Vin≥VT+ max |Iout| 4.0 mA|Iout| 5.2 mA


4.56.0


0.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.33


0.40.4


ÎÎÎÎÎÎÎÎ









µA











µA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.04.56.0


1252521

ÎÎÎÎÎÎÎÎÎ

1553126


1903832

ÎÎÎÎÎÎÎÎÎ

ns


tTLH,tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.04.56.0


751513

ÎÎÎÎÎÎÎÎÎ

951916


1102219

ÎÎÎÎÎÎÎÎÎ

ns

ÎÎÎÎÎÎÎÎCin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Input Capacitance

ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10


ÎÎÎÎÎÎpF






trVCC

GND

90%50%

10%

90%50%

10%INPUTA OR B

Y

tPHL tPLH

tTHL tTLH



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

tf

MC74HC132A


Figure 3. Typical Input Threshold, V T+, VT–Versus Power Supply Voltage

Figure 4. Typical Schmitt–Trigger Applications

T, T

YPIC

AL IN

PUT

THR

ESH

OLD

VO

LTAG

E (V

OLT

SV

4

3

2

1

2 3 4 5 6

VCC, POWER SUPPLY VOLTAGE (VOLTS)

VHtyp

VHtyp = (VT + typ) – (VT – typ)

(a) A SCHMITT TRIGGER SQUARES UP INPUTS(a) WITH SLOW RISE AND FALL TIMES

(b) A SCHMITT TRIGGER OFFERS MAXIMUM NOISE(b) IMMUNITY

Vin

Vout

VH

VCC

VT +VT –

GND

VOH

VOL

Vin

VH

Vout

VCC

VT +VT –

GND

VOH

VOL

VCC

VinVout



MC74HC138A/D



The HC138A decodes a three–bit Address to one–of–eightactive–low outputs. This device features three Chip Select inputs, twoactive–low and one active–high to facilitate the demultiplexing,cascading, and chip–selecting functions. The demultiplexing functionis accomplished by using the Address inputs to select the desireddevice output; one of the Chip Selects is used as a data input while theother Chip Selects are held in their active states.• Output Drive Capability: 10 LSTTL Loads







LOGIC DIAGRAM

7Y6

Y5

Y4

Y3Y2Y1

Y0

Y7

9

1011

121314

15

3

2

1

CS1

CS2

A0

A1

A2 ACTIVE–LOWOUTPUTS

ADDRESSINPUTS

CS3

CHIP–SELECTINPUTS 5

4

6PIN 16 = VCCPIN 8 = GND

Inputs Outputs

CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X X H X X X H H H H H H H HX H X X X X H H H H H H H HL X X X X X H H H H H H H H

H L L L L L L H H H H H H HH L L L L H H L H H H H H HH L L L H L H H L H H H H HH L L L H H H H H L H H H H

H L L H L L H H H H L H H HH L L H L H H H H H H L H HH L L H H L H H H H H H L HH L L H H H H H H H H H H L

FUNCTION TABLE

H = high level (steady state); L = low level (steady state); X = don’t care

SO–16D SUFFIX

CASE 751B

http://onsemi.com

TSSOP–16DT SUFFIXCASE 948F

1

16

PDIP–16N SUFFIXCASE 648

1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC138ANAWLYYWW

1

16

HC138AAWLYWW

A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week

HC138AALYW

1

16




MC74HC138AD SOIC–16 48 / Rail




PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A0

CS2

A2

A1

Y7

CS1

CS3

GND

Y3

Y2

Y1

Y0

VCC

Y5

Y4

Y6

MC74HC138A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C





260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: – 10 mW/C from 65 to 125CSOIC Package: – 7 mW/C from 65 to 125C TSSOP Package: – 6.1 .W/C from 65 to 125C





ÎÎÎÎVCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ2.0ÎÎÎÎ6.0ÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎVin, VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ0ÎÎÎÎVCCÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎTAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOperating Temperature, All Package Types



tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


VCC = 6.0 V


000

ÎÎÎÎÎÎÎÎ

1000500400


ns




ÎÎÎÎÎÎÎÎ


Guaranteed LimitÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


–55C to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V


VOH






2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ



MC74HC138A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

–55C to25C

ÎÎÎÎÎÎÎÎ

VCCV










2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎIin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



Vin = VCC or GND ÎÎÎÎÎÎÎÎ


± 0.1 ÎÎÎÎÎÎ

± 1.0ÎÎÎÎÎÎÎÎ

± 1.0ÎÎÎÎÎÎ

µA








4ÎÎÎÎÎÎÎÎÎ



µA


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎ


Symbol


Parameter


VCCV


–55C to25C



125C

ÎÎÎÎÎÎÎÎÎ


tPLH,tPHL




2.03.04.56.0


135902723


1701253429


2051654135


ns


tPLH,tPHL


Maximum Propagation Delay, CS1 to Output Y(Figures 2 and 4)


2.03.04.56.0


110852219


1401002824


1651253328


ns


tPLH,tPHL


Maximum Propagation Delay, CS2 or CS3 to Output Y(Figures 3 and 4)


2.03.04.56.0


120902420


1501203026


1801503631


ns


tTLH,tTHL




2.03.04.56.0


75301513


95401916


110552219


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF



CPD Power Dissipation Capacitance (Per Package)* 55 pF


MC74HC138A


Figure 1.

50%

tPHLtPLH

VCC

GND

Figure 2.

VALID VALID

OUTPUT Y 50%

tftrVCC

GNDtPLH

tTLH

90%50%

10%OUTPUT Y

INPUT CS1

tPHL

90%50%

10%

tTHL

INPUT A

SWITCHING WAVEFORMS

tTHL tTLH

VCC

GND

tr

tPHL tPLH

OUTPUT Y

INPUTCS2, CS3

90%50%

10%

90%50%

10%

Figure 3.

tf



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

PIN DESCRIPTIONS

ADDRESS INPUTSA0, A1, A2 (Pins 1, 2, 3)

Address inputs. These inputs, when the chip is selected,determine which of the eight outputs is active–low.

CONTROL INPUTSCS1, CS2, CS3 (Pins 6, 4, 5)

Chip select inputs. For CS1 at a high level and CS2, CS3at a low level, the chip is selected and the outputs follow the

Address inputs. For any other combination of CS1, CS2, andCS3, the outputs are at a logic high.

OUTPUTSY0 – Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)

Active–low Decoded outputs. These outputs assume alow level when addressed and the chip is selected. Theseoutputs remain high when not addressed or the chip is notselected.

MC74HC138A


A0

A1

A2

CS3

CS2

CS1

1

2

3

4

5

6

15

14

13

12

11

10

9

7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0




MC74HCT138A/D

"!$ #! ! "! High–Performance Silicon–Gate CMOS

The MC74HCT138A is identical in pinout to the LS138. TheHCT138A may be used as a level converter for interfacing TTL orNMOS outputs to High Speed CMOS inputs.

The HCT138A decodes a three–bit Address to one–of–eightactive–lot outputs. This device features three Chip Select inputs, twoactive–low and one active–high to facilitate the demultiplexing,cascading, and chip–selecting functions. The demultiplexing functionis accomplished by using the Address inputs to select the desireddevice output; one of the Chip Selects is used as a data input while theother Chip Selects are held in their active states.


• TTL/NMOS Compatible Input Levels





• Chip Complexity: 122 FETs or 30.5 Equivalent Gates

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HCT138ANAWLYYWW

1

16

HCT138AAWLYWW


HCT138AALYW

1

16




MC74HCT138AD SOIC–16 48 / Rail




MC74HCT138A


LOGIC DIAGRAM

7Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

9

10

11

12

13

14

15

3

2

1

CS1

CS2

A0

A1

A2

ACTIVE–LOWOUTPUTS

ADDRESSINPUTS

CS3

CHIP–SELECTINPUTS 5

4

6


Inputs Outputs

CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X X H X X X H H H H H H H HX H X X X X H H H H H H H HL X X X X X H H H H H H H H

H L L L L L L H H H H H H HH L L L L H H L H H H H H HH L L L H L H H L H H H H HH L L L H H H H H L H H H H

H L L H L L H H H H L H H HH L L H L H H H H H H L H HH L L H H L H H H H H H L HH L L H H H H H H H H H H L

FUNCTION TABLE

H = high level (steady state)L = low level (steady state)X = don’t care

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A0

CS2

A2

A1

Y7

CS1

CS3

GND

Y3

Y2

Y1

Y0

VCC

Y5

Y4

Y6


Design CriteriaÎÎÎÎÎÎÎÎÎÎÎÎ

ValueÎÎÎÎÎÎÎÎÎ

Units



30.5 ÎÎÎÎÎÎ

ea.


Internal Gate Propagation Delay ÎÎÎÎÎÎÎÎ

1.5 ÎÎÎÎÎÎ

ns


Internal Gate Power DissipationÎÎÎÎÎÎÎÎ

5.0ÎÎÎÎÎÎ

µWÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Speed Power ProductÎÎÎÎÎÎÎÎÎÎÎÎ

.0075ÎÎÎÎÎÎÎÎÎ

pJ

*Equivalent to a two–input NAND gate.

MC74HCT138A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C



Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP, TSSOP or SOIC Package)


260

ÎÎÎÎÎÎÎÎÎ

C







Min ÎÎÎÎ

MaxÎÎÎÎÎÎ




4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ









V

ÎÎÎÎÎÎÎÎ

VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ

V







4.55.5


4.45.4

ÎÎÎÎÎÎÎÎÎ

4.45.4


4.45.4

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL|Iout| 4.0 µA


4.5


3.98

ÎÎÎÎÎÎÎÎÎ

3.84


3.7


ÎÎÎÎVOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ

V






4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4


ÎÎÎÎÎÎÎÎ









µA











µA

ÎÎÎÎÎÎÎÎ




Vin = 2.4 V, Any One InputVi = VCC or GND Other Inputs

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

≥ – 55C ÎÎÎÎÎÎÎÎÎÎÎÎ

25C to 125C ÎÎÎÎÎÎÎÎÎÎ



Vin = VCC or GND, Other In utslout = 0 µA ÎÎÎÎ

ÎÎÎÎ5.5 ÎÎÎÎÎÎÎÎ


2.4 ÎÎÎÎÎÎ

mA




MC74HCT138A








SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


– 55 to25CÎÎÎÎÎÎÎÎÎÎÎÎ



Unit


tPLH,tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

30 ÎÎÎÎÎÎÎÎ

38 ÎÎÎÎÎÎÎÎ

45 ÎÎÎÎÎÎ

ns


tPLH,tPHL


Maximum Propagation Delay, CS1 to Output Y(Figures 2 and 4)





ns


tPLH,tPHL


Maximum Output Transition Time, CS2 or CS3 to Output Y(Figures 3 and 4)





ns


tTLH,tTHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

19 ÎÎÎÎÎÎÎÎ

22 ÎÎÎÎÎÎ

ns


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall TimeÎÎÎÎÎÎÎÎ

500ÎÎÎÎÎÎÎÎ

500ÎÎÎÎÎÎÎÎ

500ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎ

CinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input CapacitanceÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ

pF






A0

A1

A2

CS3

CS2

CS1

1

2

3

4

5

6

15

14

13

12

11

10

9

7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

MC74HCT138A


SWITCHING WAVEFORMS

Figure 1.

1.3 V

tPHLtPLH

tTHL tTLH

3 V

GND

Figure 2.

VALID

OUTPUT Y 1.3 V

3 V

GND

tf

tf

tPHL tPLH

OUTPUT Y

INPUTCS2, CS3

90%1.3 V10%

tr3 V

GND

tPLH

tTLH

90%

10%OUTPUT Y

INPUT CS1

tPHL

2.7 V1.3 V

0.3 V

tTHL

INPUT A

Figure 3.

tr


Figure 4.

CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

VALID

1.3 V

2.7 V1.3 V0.3 V

TEST CIRCUIT



MC74HC139A/D



This device consists of two independent 1–of–4 decoders, each ofwhich decodes a two–bit Address to one–of–four active–low outputs.Active–low Selects are provided to facilitate the demultiplexing andcascading functions. The demultiplexing function is accomplished byusing the Address inputs to select the desired device output, andutilizing the Select as a data input.








LOGIC DIAGRAM

A0a

A1a

SELECTa

A0b

A1b

1

SELECTb

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

ACTIVE–LOWOUTPUTS

ADDRESSINPUTS


ACTIVE–LOWOUTPUTS

3

2

ADDRESSINPUTS 13

14

15

4

5

6

7

12

11

10

9

FUNCTION TABLE

Inputs Outputs

Select A1 A0 Y0 Y1 Y2 Y3

H X X H H H HL L L L H H HL L H H L H HL H L H H L HL H H H H H L

X = don’t care

SO–16D SUFFIX

CASE 751B

http://onsemi.com

1

16


1

16

MARKINGDIAGRAMS

1

16

MC74HC139ANAWLYYWW

1

16

HC139AAWLYWW







PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

SELECTa

A1a

A0a

GND

A1b

A0b

SELECTb

VCC

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

MC74HC139A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ




750500ÎÎÎÎÎÎ

mW





ÎÎÎÎÎÎÎÎ




260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.04.56.0


1.53.154.2

ÎÎÎÎÎÎÎÎÎ

1.53.154.2


1.53.154.2

ÎÎÎÎÎÎÎÎÎ

V







2.04.56.0


0.51.351.8

ÎÎÎÎÎÎÎÎÎ

0.51.351.8


0.51.351.8

ÎÎÎÎÎÎÎÎÎ

V







2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V

ÎÎÎÎÎÎÎÎ



Vin = VIH or VIL |Iout| 4.0 mA|Iout| 5.2 mA

ÎÎÎÎÎÎÎÎ


3.985.48ÎÎÎÎÎÎ


3.705.20ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL |Iout| 4.0 mA|Iout| 5.2 mA


4.56.0


0.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.33


0.400.40


ÎÎÎÎÎÎÎÎ









µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


4 ÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

160 ÎÎÎÎÎÎ

µA




MC74HC139A





ÎÎÎÎÎÎÎÎ




SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit


tPLH,tPHL


Maximum Propagation Delay, Select to Output Y(Figures 1 and 3)


2.04.56.0


1152320

ÎÎÎÎÎÎÎÎÎ

1452925


1753530

ÎÎÎÎÎÎÎÎÎ

ns


tPLH,tPHL




2.04.56.0


1152320

ÎÎÎÎÎÎÎÎÎ

1452925


1753530

ÎÎÎÎÎÎÎÎÎ

ns


tTLH,tTHL




2.04.56.0


751513

ÎÎÎÎÎÎÎÎÎ

951916


1102219

ÎÎÎÎÎÎÎÎÎ

ns



ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10


ÎÎÎÎÎÎpF



CPD Power Dissipation Capacitance (Per Decoder)* 55 pF


SWITCHING WAVEFORMS

tTHL tTLH

Figure 1.

VCC

GND

tr

tPHL tPLH

OUTPUT Y

SELECT

90%50%

10%

90%50%10%

Figure 2.

50%

tPHLtPLH

VCC

GND

OUTPUT Y 50%

INPUT A



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

tfVALID VALID

MC74HC139A


PIN DESCRIPTIONS

ADDRESS INPUTSA0a, A1a, A0b, A1b (Pins 2, 3, 14, 13)

Address inputs. These inputs, when the respective 1–of–4decoder is enabled, determine which of its four active–lowoutputs is selected.

CONTROL INPUTSSelect a, Select b (Pins 1, 15)

Active–low select inputs. For a low level on this input, theoutputs for that particular decoder follow the Address

inputs. A high level on this input forces all outputs to a highlevel.

OUTPUTSY0a – Y3a, Y0b – Y3b (Pins 4 – 7, 12, 11, 10, 9)

Active–low outputs. These outputs assume a low levelwhen addressed and the appropriate Select input is active.These outputs remain high when not addressed or theappropriate Select input is inactive.

SELECT

A0

A1

Y0

Y1

Y2

Y3

EXPANDED LOGIC DIAGRAM(1/2 OF DEVICE)



MC74HC157A/D



This device routes 2 nibbles (A or B) to a single port (Y) asdetermined by the Select input. The data is presented at the outputs innoninverted form. A high level on the Output Enable input sets all fourY outputs to a low level.








LOGIC DIAGRAM

2

5

11

14

3

6

10

13

4

7

9

12

1

15

A0

A1

A2

A3

B0

B1

B2

B3

Y0

Y1

Y2

Y3

SELECT

OUTPUTENABLE

DATAOUTPUTS

NIBBLEA INPUTS

NIBBLEB INPUTS


FUNCTION TABLE

Inputs

Output OutputsEnable Select Y0 – Y3

X = don’t careA0 – A3, B0 – B3 = the levels of therespective Data–Word Inputs.

HLL

XLH

LA0–A3B0–B3

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC157ANAWLYYWW

1

16

HC157AAWLYWW


HC157AALYW

1

16








PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

SELECT

Y0

B0

A0

Y1

B1

A1

GND

Y3

B3

A3

OUTPUTENABLE

VCC

B2

A2

Y2

MC74HC157A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎ

0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ


Operating Temperature, All Package TypesÎÎÎÎÎÎ

– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ




VCC = 6.0 V


000

ÎÎÎÎÎÎÎÎ

1000500400


ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions



– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit



Minimum High–Level InputVoltage ÎÎÎÎÎÎÎÎÎ


Vout = VCC – 0.1 V|Iout| 20 µA ÎÎÎÎ

ÎÎÎÎÎÎÎÎ

2.03.04.56.0


1.52.13.154.2

ÎÎÎÎÎÎÎÎÎ

1.52.13.154.2


1.52.13.154.2

ÎÎÎÎÎÎÎÎÎ

V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48


2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ




Vin = VIL|Iout| 20 µA ÎÎÎÎ

ÎÎÎÎÎÎÎÎ

2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC157A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA











µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHL




2.03.04.56.0


105652118


130852622


1601153227


ns


tPLH,tPHL


Maximum Propagation Delay, Select to Output Y(Figures 2 and 4)


2.03.04.56.0


110702219


140902824


1651153328


ns


tPLH,tPHL


Maximum Propagation Delay, Output Enable to Output Y(Figures 3 and 4)


2.03.04.56.0


100602017


125802521


1501103026


ns


tTLH,tTHL




2.03.04.56.0


75271513

ÎÎÎÎÎÎÎÎÎ

95321916


110362219

ÎÎÎÎÎÎÎÎÎ

ns



ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10


ÎÎÎÎÎÎpF





MC74HC157A


PIN DESCRIPTIONS

INPUTSA0, A1, A2, A3 (Pins 2, 5, 11, 14)

Nibble A inputs. The data present on these pins istransferred to the outputs when the Select input is at a lowlevel and the Output Enable input is at a low level. The datais presented to the outputs in noninverted form.

B0, B1, B2, B3 (Pins 3, 6, 10, 13)

Nibble B inputs. The data present on these pins istransferred to the outputs when the Select input is at a highlevel and the Output Enable input is at a low level. The datais presented to the outputs in noninverted form.

OUTPUTSY0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)

Data outputs. The selected input Nibble is presented atthese outputs when the Output Enable input is at a low level.

The data present on these pins is in its noninverted form. Forthe Output Enable input at a high level, the outputs are at alow level.

CONTROL INPUTSSelect (Pin 1)

Nibble select. This input determines the data word to betransferred to the outputs. A low level on this input selectsthe A inputs and a high level selects the B inputs.

Output Enable (Pin 15)

Output Enable input. A low level on this input allows theselected input data to be presented at the outputs. A highlevel on this input sets all outputs to a low level.

SWITCHING WAVEFORMS

INPUT A OR B

Figure 1. HC157A Figure 2. Y versus Select, Noninverted

OUTPUTENABLE

tPLHtPHL

tr tfVCC

GND

tTHL tTLH

10%50%

90%

10%50%

90%

Figure 3. HC157A

OUTPUT Y


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


tr tfVCC

GND

OUTPUT Y

tPHLtPLH

10%50%

90%

10%50%

90%

tTLH tTHL

tr tfVCC

GNDSELECT

OUTPUT Y

tPHLtPLH

tTLH tTHL

10%50%

90%

10%50%

90%

MC74HC157A



4

7

9

12

2

3

5

6

11

10

14

13

15

1

A0

B0

A1

B1

A2

B2

A3

B3

Y0

Y1

Y2

Y3

OUTPUT ENABLE

SELECT

DATAOUTPUTS

NIBBLEOUTPUTS



MC74HC161A/D


The MC74HC161A and HC163A are identical in pinout to theLS161 and LS163. The device inputs are compatible with standardCMOS outputs; with pullup resistors, they are compatible withLSTTL outputs.

The HC161A and HC163A are programmable 4–bit binary counterswith asynchronous and synchronous reset, respectively.









DeviceÎÎÎÎÎÎÎÎÎÎÎÎ

CountModeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Mode

ÎÎÎÎÎÎÎÎ


BinaryÎÎÎÎÎÎÎÎÎÎÎÎ

Asynchronous

ÎÎÎÎÎÎÎÎ


BinaryÎÎÎÎÎÎÎÎÎÎÎÎ

Synchronous

LOGIC DIAGRAM


11

12

13

14 Q0

Q1

Q2

Q3

15 RIPPLECARRY

OUT

BCD ORBINARYOUTPUT

3

4

5

6

P0

P1

P2

P3

2CLOCK

RESET

LOAD

ENABLE P

ENABLE T

COUNTENABLES

PRESETDATA

INPUTS

1

9

7

10 Inputs Output

Clock Reset* Load Enable P Enable T Q

L X X X ResetH L X X Load Preset DataH H H H CountH H L X No CountH H X L No Count

FUNCTION TABLE

*HC163A only. HC161A is an Asynchronous Reset DeviceH = high level, L = low level, X = don’t care

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

RESET

P0

CLOCK

GND

Q1

Q0

RIPPLECARRY OUT

VCC

P1

P2

P3

ENABLE P

Q2

Q3

ENABLE T

LOAD

SO–16D SUFFIX

CASE 751B

http://onsemi.com

1

16


1

16

MARKINGDIAGRAMS

1

16

MC74HC16xANAWLYYWW

1

16

HC16xAAWLYWW




MC74HC16xAN PDIP–16 2000 / Box

MC74HC16xAD SOIC–16 48 / Rail

MC74HC16xADR2 SOIC–16 2500 / Reel




MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ




750500ÎÎÎÎÎÎ

mW





ÎÎÎÎÎÎÎÎ




260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise and Fall Time (Figure 1) VCC = 2.0 VVCC = 3.0 VVCC = 4.5 VVCC = 6.0 V


0000

ÎÎÎÎÎÎÎÎ

1000600500400


ns






ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ







– 55 to25C


125CÎÎÎÎÎÎ







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2








2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4


ÎÎÎÎÎÎÎÎ









µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


4.0 ÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

160 ÎÎÎÎÎÎ

µA






ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ



Fig.ÎÎÎÎÎÎÎÎÎÎÎÎ


– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit


fmax ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)* ÎÎÎÎÎÎÎÎÎ

1, 7ÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.56.0


6153035

ÎÎÎÎÎÎÎÎÎ

5122428


4102024

ÎÎÎÎÎÎÎÎÎ

MHz


tPLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to QÎÎÎÎÎÎÎÎÎÎÎÎ

1, 7ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.56.0


120752016


1601202320


2001502822


ns


tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


1451002218


1851352520


2201503023


ns



Maximum Propagation Delay, Reset to Q (HC161A Only)ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


1451002017


1851352219


2201502521


ns



Maximum Propagation Delay, Enable T to Ripple Carry OutÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


110601614


1501151815


1901402017


ns





2.03.04.56.0


1351001815


1751302016


2101602220


ns



Maximum Propagation Delay, Clock to Ripple Carry Out ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


120752218


1601352722


2001503025


ns





2.03.04.56.0


1451002220


1851352824


2201503528


ns



Maximum Propagation Delay, Reset to Ripple Carry Out(HC161A Only)



2.03.04.56.0


1551202218


1901402622


2301553025


ns


tTLH,tTHL


Maximum Output Transition Time, Any Output ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


75301513


95401916


110552219


ns

ÎÎÎÎÎÎÎÎ

Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance ÎÎÎÎÎÎ

1, 7ÎÎÎÎÎÎÎÎ


10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF

*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Outpropagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.See Applications information in this data sheet.








TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ





– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time,Preset Data Inputs to Clock

ÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


40201512

ÎÎÎÎÎÎÎÎÎ

60302018


80403020

ÎÎÎÎÎÎÎÎÎ

ns


tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time,Load to Clock


5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.56.0


60251512


75302018


90403020


ns



Minimum Setup Time,Reset to Clock (HC163A Only)



2.03.04.56.0


60252017


75302523


90403525


ns



Minimum Setup Time,Enable T or Enable P to Clock



2.03.04.56.0


80352017


95402523


110503525


ns


thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time,Clock to Load or Preset Data Inputs



2.03.04.56.0


3333


3333


3333


ns



Minimum Hold Time,Clock to Reset (HC163A Only)



2.03.04.56.0


3333


3333


3333


ns



Minimum Hold Time,Clock to Enable T or Enable P



2.03.04.56.0


3333


3333


3333


ns


trecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time,Reset Inactive to Clock (HC161A Only)



2.03.04.56.0


80351512


95402017


110502623


ns


trec ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time,Load Inactive to Clock



2.03.04.56.0


80351512


95402017


110502623


ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width,Clock



2.03.04.56.0


60251210


75301513


90401815


ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width,Reset (HC161A Only)



2.03.04.56.0


60251210


75301513


90401815


ns



Maximum Input Rise and Fall Times ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns



FUNCTION DESCRIPTION

The HC161A/163A are programmable 4–bit synchronouscounters that feature parallel Load, synchronous orasynchronous Reset, a Carry Output for cascading andcount–enable controls.

The HC161A and HC163A are binary counters withasynchronous Reset and synchronous Reset, respectively.

INPUTS

Clock (Pin 2)

The internal flip–flops toggle and the output countadvances with the rising edge of the Clock input. In addition,control functions, such as resetting and loading occur withthe rising edge of the Clock input.

Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)

These are the data inputs for programmable counting.Data on these pins may be synchronously loaded into theinternal flip–flops and appear at the counter outputs. P0 (Pin3) is the least–significant bit and P3 (Pin 6) is themost–significant bit.

OUTPUTS

Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)

These are the counter outputs. Q0 (Pin 14) is theleast–significant bit and Q3 (Pin 11) is the most–significantbit.

Ripple Carry Out (Pin 15)

When the counter is in its maximum state 1111, this outputgoes high, providing an external look–ahead carry pulse thatmay be used to enable successive cascaded counters. RippleCarry Out remains high only during the maximum countstate. The logic equation for this output is:

Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3

CONTROL FUNCTIONS

ResettingA low level on the Reset pin (Pin 1) resets the internal

flip–flops and sets the outputs (Q0 through Q3) to a low

level. The HC161A resets asynchronously, and the HC163Aresets with the rising edge of the Clock input (synchronousreset).

Loading

With the rising edge of the Clock, a low level on Load (Pin9) loads the data from the Preset Data input pins (P0, P1, P2,P3) into the internal flip–flops and onto the output pins, Q0through Q3. The count function is disabled as long as Loadis low.

Count Enable/Disable

These devices have two count–enable control pins:Enable P (Pin 7) and Enable T (Pin 10). The devices countwhen these two pins and the Load pin are high. The logicequation is:

Count Enable = Enable P • Enable T • Load

The count is either enabled or disabled by the controlinputs according to Table 1. In general, Enable P is acount–enable control: Enable T is both a count–enable anda Ripple–Carry Output control.

Table 1. Count Enable/Disable

Control Inputs Result at Outputs

Load Enable P Enable T Q0 – Q3 Ripple Carry Out

H H H CountHigh when Q0–Q3

L H H NoCount

High when Q0–Q3are maximum*

X L H NoCount

High when Q0–Q3are maximum*

X X L NoCount

L

*Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.

0 1 2 3 4

5

6

7

89101112

13

14

15

OUTPUT STATE DIAGRAMS

Binary Counters



SWITCHING WAVEFORMS

Figure 1. Figure 2.

Figure 3. Figure 4. HC163A Only

Figure 5. Figure 6.

TEST CIRCUIT

Figure 7.

tr tfVCC

GND

tTHLtTLH

ANYOUTPUT

90%50%

10%

90%50%

10%CLOCK

tPLH tPHL

50%

tPHL

VCC

GND

VCC

GND

ANYOUTPUT

CLOCK

RESET

50%

50%

trec

tr tfVCC

GNDtPHLtPLH

90%50%

10%

90%50%

10%

tTHLtTLH

ENABLE T

RIPPLECARRY

OUTCLOCK

RESET 50%

tsu

VCC

GND50%

INPUTSP0, P1,P2, P3

50%VCC

GND

VCC

GND

GND

50%

50%LOAD

CLOCK

VCC

GND

VCC

GND

ENABLE TOR

ENABLE P50%

50%CLOCK


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

VCC

tw1/fmax

tw

th

VALID

tsu th

tsu th trec

VALID

tsu th

MC

74HC

161A, M

C74H

C163A

http://onsemi.com

146

P0

P1

P2

P3

ENABLE P

ENABLE T

RESET

T0RCCLOADLOADP0

Q0 Q0

Q1

Q2

Q3

RIPPLECARRYOUT

VCC = PIN 16GND = PIN 8

14

The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data fromPreset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) ofthe flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flopon the next rising edge of the clock.

A logic zero on the Reset device input forces the internal clock (C) high and resets the Qoutput of the flip–flop low.

Q0

Q1

Q1

Q2

Q2

Q3

T1RCCLOADLOADP1

T2RCCLOADLOADP2

T3RCCLOADLOADP3

13

12

11

15

3

4

5

6

7

10

1

Figure 8. 4–B

it Binary C

ounter with A

synchronous Reset

(MC

74HC

161A)

R

C

C

LOAD

LOAD

CLOCK

LOAD9

2



Sequence illustrated in waveforms:1. Reset outputs to zero.2. Preset to binary twelve.3. Count to thirteen, fourteen, fifteen, zero, one and two.4. Inhibit.

RESET (HC161A)

RESET (HC163A)

LOAD

P0

P1

P2

P3

CLOCK (HC161A)

CLOCK (HC163A)

ENABLE P

ENABLE T

Q0

Q1

Q2

Q3

RIPPLECARRY

OUT

(ASYNCHRONOUS)

(SYNCHRONOUS)

12 13 14 15 0 1 2

RESET LOAD

COUNTENABLES

OUTPUTS

PRESETDATA

INPUTS

INHIBITCOUNT

Figure 9. Timing Diagram

MC

74HC

161A, M

C74H

C163A

http://onsemi.com

148

P0

P1

P2

P3

ENABLE P

ENABLE T

RESET

T0RCCLOADLOADP0

Q0 Q0

Q1

Q2

Q3

RIPPLECARRYOUT


14

The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data fromPreset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) ofthe flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flopon the next rising edge of the clock.

A logic zero on the Reset device input forces the internal clock (C) high and resets the Qoutput of the flip–flop low.

Q0

Q1

Q1

Q2

Q2

Q3

T1RCCLOADLOADP1

T2RCCLOADLOADP2

T3RCCLOADLOADP3

13

12

11

15

3

4

5

6

7

10

1

9

2

R

C

C

LOAD

LOAD

CLOCK

LOAD

Figure 10. 4–B

it Binary C

ounter with S

ynchronous Reset

(MC

74HC

163A)



INPUTS

OUTPUTS

TOMORE

SIGNIFICANTSTAGES

LOAD

H = COUNTL = DISABLE

H = COUNTL = DISABLE

RESET

CLOCK

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

R Q0 Q1 Q2 Q3

RIPPLECARRY

OUT

LOAD

RESET

CLOCK

ENABLE P

ENABLE T

TYPICAL APPLICATIONS CASCADING

NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend onnumber of stages. This limitation is due to set up times between Enable (Port) and Clock.

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

R Q0 Q1 Q2 Q3

RIPPLECARRY

OUT

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

R Q0 Q1 Q2 Q3

RIPPLECARRY

OUT

INPUTS

OUTPUTS

INPUTS

OUTPUTS

INPUTS INPUTS INPUTS

OUTPUTS OUTPUTS OUTPUTS

TOMORE

SIGNIFICANTSTAGES

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

R Q0 Q1 Q2 Q3

RIPPLECARRY

OUT

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

R Q0 Q1 Q2 Q3

RIPPLECARRY

OUT

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

R Q0 Q1 Q2 Q3

RIPPLECARRY

OUT

Figure 11. N–Bit Synchronous Counters

Figure 12. Nibble Ripple Counter



Figure 13. Modulo–5 Counter

OUTPUT

OPTIONAL BUFFERFOR NOISE REJECTION

OTHERINPUTS

RESET

HC163A

Q0

Q1

Q2

Q3

TYPICAL APPLICATIONS VARYING THE MODULUS

OUTPUT

OPTIONAL BUFFERFOR NOISE REJECTION

OTHERINPUTS

RESET

HC163A

Q0

Q1

Q2

Q3

Figure 14. Modulo–11 Counter

The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due tothe synchronous Reset.



MC74HC164A/D



The MC74HC164A is an 8–bit, serial–input to parallel–output shiftregister. Two serial data inputs, A1 and A2, are provided so that oneinput may be used as a data enable. Data is entered on each rising edgeof the clock. The active–low asynchronous Reset overrides the Clockand Serial Data inputs.








LOGIC DIAGRAM


3QA

4

5

6

10

11

12

13

QBQCQD

QEQFQG

QH

PARALLELDATAOUTPUTS

9RESET

CLOCK8

SERIALDATA

INPUTS

A1

A2

1

2 DATA

FUNCTION TABLE

Inputs Outputs

Reset Clock A1 A2 Q A QB … QHL X X X L L … LH X X No ChangeH H D D QAn … QGnH D H D QAn … QGn

D = data inputQAn – QGn = data shifted from the precedingstage on a rising edge at the clock input.





http://onsemi.com

55 / Rail


MARKINGDIAGRAMS





HC164AALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC164ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC164AAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

QE

QF

QG

QH

VCC

CLOCK

RESET

QB

QA

A2

A1

GND

QD

QC

MC74HC164A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


–55C to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ



MC74HC164A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ





–55C to25C


VCCV





VOL






2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎÎÎÎÎ









µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


4 ÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

160 ÎÎÎÎÎÎ

µA





ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎ


–55C to25C

ÎÎÎÎÎÎ 85CÎÎÎÎÎÎÎÎ 125C

ÎÎÎÎÎÎUnitÎÎÎÎÎ


fmaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


10204050


10203545


10203040


MHz


tPLH,tPHL


Maximum Propagation Delay, Clock to Q(Figures 1 and 4)


2.03.04.56.0


1601003227


2001504034


2502004842


ns


tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to Q(Figures 2 and 4)


2.03.04.56.0


1751003530


2201504437


2602005345


ns


tTLH,tTHL




2.03.04.56.0


75271513


95321916


110362219


ns


CinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


—ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ

pF





MC74HC164A


TIMING REQUIREMENTS (Input tr = tf = 6 ns)



ÎÎÎÎÎÎÎÎ







–55C to25C

ÎÎÎÎÎÎÎÎÎ



Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, A1 or A2 to Clock(Figure 3)


2.03.04.56.0


251575

ÎÎÎÎÎÎÎÎÎ

352086


402596

ÎÎÎÎÎÎÎÎÎ

ns



Minimum Hold Time, Clock to A1 or A2(Figure 3)


2.03.04.56.0


3333


3333


3333


ns


trecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive to Clock(Figure 2)


2.03.04.56.0


3333


3333


3333


ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


50261210


60351512


75452015


ns



Minimum Pulse Width, Reset(Figure 2)


2.03.04.56.0


50261210


60351512


75452015


ns


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times(Figure 1)


2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns


MC74HC164A


PIN DESCRIPTIONS

INPUTS

A1, A2 (Pins 1, 2)

Serial Data Inputs. Data at these inputs determine the datato be entered into the first stage of the shift register. For ahigh level to be entered into the shift register, both A1 andA2 inputs must be high, thereby allowing one input to beused as a data–enable input. When only one serial input isused, the other must be connected to VCC.

Clock (Pin 8)

Shift Register Clock. A positive–going transition on thispin shifts the data at each stage to the next stage. The shift

register is completely static, allowing clock rates down toDC in a continuous or intermittent mode.

OUTPUTS

QA – QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)

Parallel Shift Register Outputs. The shifted data ispresented at these outputs in true, or noninverted, form.

CONTROL INPUT

Reset (Pin 9)

Active–Low, Asynchronous Reset Input. A low voltageapplied to this input resets all internal flip–flops and setsOutputs QA – QH to the low level state.

SWITCHING WAVEFORMS

tfVCC

GND

90%50%

10%tw

tPLH tPHL

CLOCK

Q

tTLH tTHL

Figure 1.

RESET

trec

Figure 2.

tr

1/fmax

90%50%

10%

VCC

GND

VCC

GND

Q

CLOCK 50%

50%

50%

tPHL

tw

A1 OR A2

Figure 3.

VCC

GND

VCC

GND

50%

50%CLOCK

tsu th

VALID


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


MC74HC164A


TIMING DIAGRAM

A1

A2

CLOCK

RESET

8

1

2

9

D

R

Q

3 4 5 6 10 11 12 13

QA QB QC QD QE QF QG QH


D

R

Q D

R

Q D

R

Q D

R

Q D

R

Q D

R

Q D

R

Q

CLOCK

RESET

A1

A2

QA

QB

QC

QD

QE

QF

QG

QH



MC74HC165A/D

! ! ! High–Performance Silicon–Gate CMOS


This device is an 8–bit shift register with complementary outputsfrom the last stage. Data may be loaded into the register either inparallel or in serial form. When the Serial Shift/Parallel Load input islow, the data is loaded asynchronously in parallel. When the SerialShift/Parallel Load input is high, the data is loaded serially on therising edge of either Clock or Clock Inhibit (see the Function Table).

The 2–input NOR clock may be used either by combining twoindependent clock sources or by designating one of the clock inputs toact as a clock inhibit.












http://onsemi.com

55 / Rail


MARKINGDIAGRAMS





HC165AALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC165ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC165AAWLYWW

MC74HC165A


LOGIC DIAGRAM


11

12

13

14

3

4

5

6

10

A

B

C

D

E

F

G

H

SA

PARALLELDATA

INPUTS

SERIALDATAINPUT

SERIAL SHIFT/PARALLEL LOAD

1

2

15CLOCK

CLOCK INHIBIT

9

7

QH

QH

SERIALDATA

OUTPUTS

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

B

C

D

CLOCK INHIBIT

VCC

QH

SA

A

F

E

CLOCK

SERIAL SHIFT/ PARALLEL LOAD

GND

QH

H

G

FUNCTION TABLEInputs Internal Stages Output

Serial Shift/Parallel Load Clock

ClockInhibit SA A – H QA QB QH Operation

L X X X a … h a b h Asynchronous Parallel Load

HH

LL

LH

XX

LH

QAnQAn

QGnQGn

Serial Shift via Clock

HH

LL

LH

XX

LH

QAnQAn

QGnQGn

Serial Shift via Clock Inhibit

HH

XH

HX

XX

XX

No Change Inhibited Clock

H L L X X No Change No Clock

X = don’t care QAn – QGn = Data shifted from the preceding stage

MC74HC165A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 4.5 VVCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000600500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.80


0.50.91.351.80


0.50.91.351.80


V



Minimum High–Level OutputVoltage ÎÎÎÎÎÎÎÎÎ


Vin = VIH or VIL|Iout| 20 µA ÎÎÎÎ

ÎÎÎÎÎÎÎÎ

2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ

V



MC74HC165A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ





– 55 to25C


VCCV










2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎÎÎÎÎ









µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


4 ÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

160 ÎÎÎÎÎÎ

µA





ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


– 55 to25C







2.03.04.56.0


6183035


4.8172428


4152024


MHz


tPLH,tPHL


Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH(Figures 1 and 8)


2.03.04.56.0


150523026


190633833


225654538


ns


tPLH,tPHL


Maximum Propagation Delay, Serial Shift/Parallel Load to QH orQH (Figures 2 and 8)


2.03.04.56.0


175583530


220704437


265725345


ns


tPLH,tPHL


Maximum Propagation Delay, Input H to QH or QH(Figures 3 and 8)


2.03.04.56.0


150523026


190633833


225654538


ns


tTLH,tTHL




2.03.04.56.0


75271513


95321916


110362219


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF





MC74HC165A



ÎÎÎÎÎÎÎÎ




ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



– 55 to25CÎÎÎÎÎÎÎÎ 85C

ÎÎÎÎÎÎ 125CÎÎÎÎÎÎ


tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load(Figure 4)


2.03.04.56.0


75301513


95401916


110552219


ns



Minimum Setup Time, Input SA to Clock (or Clock Inhibit)(Figure 5)


2.03.04.56.0


75301513


95401916


110552219


ns



Minimum Setup Time, Serial Shift/Parallel Load to Clock (or ClockInhibit)

(Figure 6)


2.03.04.56.0


75301513


95401916


110552219


ns


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Clock to Clock Inhibit(Figure 7)


2.03.04.56.0


75301513


95401916


110552219


ns


th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs(Figure 4)


2.03.04.56.0


5555


5555


5555


ns



Minimum Hold Time, Clock (or Clock Inhibit) to Input SA(Figure 5)


2.03.04.56.0


5555


5555


5555


ns



Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/ParallelLoad

(Figure 6)


2.03.04.56.0


5555


5555


5555


ns


trec


Minimum Recovery Time, Clock to Clock Inhibit(Figure 7)


2.03.04.56.0


75301513


95401916


110552219


ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock (or Clock Inhibit)(Figure 1)


2.03.04.56.0


70271513


90321916


100362219


ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse width, Serial Shift/Parallel Load(Figure 2)


2.03.04.56.0


70271513


90321916


100362219


ns


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns


MC74HC165A


PIN DESCRIPTIONS

INPUTS

A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)

Parallel Data inputs. Data on these inputs areasynchronously entered in parallel into the internalflip–flops when the Serial Shift/Parallel Load input is low.

SA (Pin 10)

Serial Data input. When the Serial Shift/Parallel Loadinput is high, data on this pin is serially entered into the firststage of the shift register with the rising edge of the Clock.

CONTROL INPUTS

Serial Shift/Parallel Load (Pin 1)

Data–entry control input. When a high level is applied tothis pin, data at the Serial Data input (SA) are shifted into theregister with the rising edge of the Clock. When a low level

is applied to this pin, data at the Parallel Data inputs areasynchronously loaded into each of the eight internal stages.

Clock, Clock Inhibit (Pins 2, 15)

Clock inputs. These two clock inputs function identically.Either may be used as an active–high clock inhibit.However, to avoid double clocking, the inhibit input shouldgo high only while the clock input is high.

The shift register is completely static, allowing Clockrates down to DC in a continuous or intermittent mode.

OUTPUTS

QH, QH (Pins 9, 7)

Complementary Shift Register outputs. These pins are thenoninverted and inverted outputs of the eighth stage of theshift register.

MC74HC165A


SWITCHING WAVEFORMS

tr tfVCC

GND

90%50%

10%

tPLH tPHL

CLOCKOR CLOCK INHIBIT

90%50%

10%

tTLH tTHL

QH OR QH

Figure 1. Serial–Shift Mode


QH OR QH

50%

tPLH

50%VCC

GNDtPHL

50%

Figure 2. Parallel–Load Mode

tr tf

INPUT H 90%50%

10%

90%50%

10%

VCC

GNDtPHL

tTHLtTLH

tPLH

QH OR QH


50%VCC

GND

thVCC

GND

ASYNCHRONOUS PARALLELLOAD

(LEVEL SENSITIVE)


INPUTS A–H


INPUT SA 50%

50%CLOCK

OR CLOCK INHIBIT

VCC

GND

VCC

GND



CLOCKOR CLOCK INHIBIT

50%

50%

tsu

VCC

GND

VCC

GND

CLOCK 2 INHIBITEDCLOCK INHIBIT

CLOCK

50%

50%

tsu trec

VCC

GND

VCC

GND


Figure 7. Serial–Shift, Clock–Inhibit Mode Figure 8. Test Circuit


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

tw

1/fmax

tw

VALID

tsu

VALID

tsu th

th

MC74HC165A


A B C F G H11 12 13 4 5 6

9 QH

7 QH

SERIAL SHIFT/PARALLEL LOAD 1

SERIAL DATAINPUT SA

10

CLOCK 2

CLOCKINHIBIT

15


CLOCKCLOCK INHIBIT

SASERIAL SHIFT/

PARALLEL LOADA

B

C

D

E

F

G

H

QHQH

H

L

H

L

H

L

H

H

H H

L L

L

H

H

L

L

H

H

L

L

H

H

L

PARALLEL LOAD

PARALLELDATA

INPUTS

TIMING DIAGRAM

D QA

C C

D QB

C C

D QC

C C

D QF

C C

D QG

C C

D QH

C C

CLOCKINHIBITMODE

SERIAL–SHIFT MODE



MC74HC174A/D



This device consists of six D flip–flops with common Clock andReset inputs. Each flip–flop is loaded with a low–to–high transition ofthe Clock input. Reset is asynchronous and active–low.








LOGIC DIAGRAM


3

4

6

11

13

14

2

5

7

10

12

15

D0

D1

D2

D3

D4

D5

Q0

Q1

Q2

Q3

Q4

Q5

CLOCK 9

RESET 1

DATAINPUTS

NONINVERTINGOUTPUTS

FUNCTION TABLE

Inputs Output

Reset Clock D Q

L X X LH H HH L LH L X No ChangeH X No Change

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria

ÎÎÎÎÎÎValueÎÎÎÎÎÎUnitsÎÎÎÎÎÎÎÎÎ


Internal Gate Count*ÎÎÎÎÎÎÎÎÎ


ea.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay ÎÎÎ

ÎÎÎ1.5ÎÎÎÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Power Dissipation ÎÎÎ

ÎÎÎ5.0ÎÎÎÎÎÎ

µW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed Power Product ÎÎÎ

ÎÎÎ.0075ÎÎÎÎÎÎ

pJ


SO–16D SUFFIX

CASE 751B

http://onsemi.com

1

16


1

16

MARKINGDIAGRAMS

1

16

MC74HC174ANAWLYYWW

1

16

HC174AAWLYWW







PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q4

D4

D5

Q5

VCC

CLOCK

Q3

D3

D1

D0

Q0

RESET

GND

Q2

D2

Q1

MC74HC174A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



–0.5 to VCC + 0.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ




750500ÎÎÎÎÎÎ

mW





ÎÎÎÎÎÎÎÎ




260

ÎÎÎÎÎÎÎÎÎ

C







Min ÎÎÎÎ

MaxÎÎÎÎÎÎ




2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise and Fall Time (Figure 1) VCC = 2.0 VVCC = 4.5 VVCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ


ParameterÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



– 55 to25C

ÎÎÎÎÎÎÎÎÎ




VIH






2.04.56.0


1.53.154.2


1.53.154.2


1.53.154.2


V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





2.04.56.0


0.51.351.8

ÎÎÎÎÎÎÎÎÎ

0.51.351.8


0.51.351.8

ÎÎÎÎÎÎÎÎÎ

V


VOHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL|Iout| 4.0 mA|Iout| 5.2 mA


4.56.0


3.985.48


3.845.34


3.75.2


ÎÎÎÎÎÎÎÎ

VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






4.56.0


0.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.33


0.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC174A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎUnit

ÎÎÎÎÎÎÎÎ 125C

ÎÎÎÎÎÎ 85C

ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTest Conditions

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎIin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = VCC or GND

ÎÎÎÎÎÎÎÎ6.0

ÎÎÎÎÎÎÎÎ± 0.1

ÎÎÎÎÎÎ± 1.0ÎÎÎÎÎÎÎÎ± 1.0

ÎÎÎÎÎÎµAÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ









µA

NOTES:1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola

High–Speed CMOS Data Book (DL129/D).2. Total Supply Current = ICC + S∆ICC.



ÎÎÎÎÎÎÎÎ




Symbol


Parameter



– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


fmax ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.04.56.0


6.03035

ÎÎÎÎÎÎÎÎÎ

4.82428


4.02024

ÎÎÎÎÎÎÎÎÎ

MHz


tPLHtPHL




2.04.56.0


1102219

ÎÎÎÎÎÎÎÎÎ

1402824


1653328

ÎÎÎÎÎÎÎÎÎ

ns


tPLHtPHL




2.04.56.0


1102119

ÎÎÎÎÎÎÎÎÎ

1402824


1603227

ÎÎÎÎÎÎÎÎÎ

ns


tTLHtTHL




2.04.56.0


751513

ÎÎÎÎÎÎÎÎÎ

951916


1102219

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎÎÎÎÎVCCÎÎÎÎÎÎÎÎÎÎ

– 55 to 25CÎÎÎÎÎÎÎÎ 85C



ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Fig. ÎÎÎÎÎÎ

CCV ÎÎÎÎÎÎ

Min ÎÎÎÎ

Max ÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock ÎÎÎÎÎÎÎÎÎ


2.04.56.0

ÎÎÎÎÎÎÎÎÎ

50109.0

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

651311

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

751513

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ns


thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data ÎÎÎÎÎÎÎÎÎ


2.04.56.0

ÎÎÎÎÎÎÎÎÎ

5.05.05.0

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

5.05.05.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

5.05.05.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ns


trecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive toClock

ÎÎÎÎÎÎÎÎÎ

2ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

5.05.05.0

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

5.05.05.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

5.05.05.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, ClockÎÎÎÎÎÎÎÎÎ

1ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

751513

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

951916

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1102219

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, ResetÎÎÎÎÎÎÎÎÎÎÎÎ


2.04.56.0


751513

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

951916



1102219



ns


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times ÎÎÎÎÎÎÎÎÎ


2.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns

MC74HC174A


CLOCK 9

D0 3

RESET 1

D1 4

D2 6

D3 11

D4 13

D5 14

CQ

DR

2

5

7

10

12

15

Q0

Q1

Q2

Q3

Q4

Q5


50%VCC

GND

VCC

GND50%

CLOCK

Q

RESET

tPHL

Figure 1.

50%

DATA

CLOCK

VCC

VCC

GND

Figure 2.

VALID

GNDtsu th

1/fmax

CLOCK

Q

tr tfVCC

GND

90%50%

10%

90%50%

10%

tPLH tPHL

tTLH tTHL

tw


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3. Figure 4. Test Circuit

SWITCHING WAVEFORMS

CQ

DR

CQ

DR

CQ

DR

CQ

DR

CQ

DR

tw

trec

50%



MC74HC175A/D



This device consists of four D flip–flops with common Reset andClock inputs, and separate D inputs. Reset (active–low) isasynchronous and occurs when a low level is applied to the Resetinput. Information at a D input is transferred to the corresponding Qoutput on the next positive going edge of the Clock input.







• Chip Complexity 166 FETs or 41.5 Equivalent Gates

LOGIC DIAGRAM


9

4

5

12

13

CLOCK

D0

D1

D2

D3

RESET 1

DATAINPUTS

237610111514

Q0Q0

Q1Q1Q2

Q2Q3Q3

INVERTINGAND

NONINVERTINGOUTPUTS

FUNCTION TABLE

Inputs Outputs

Reset Clock D Q Q

L X X L HH H H LH L L HH L X No Change

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC175ANAWLYYWW

1

16

HC175AAWLYWW


HC175AALYW

1

16








PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

Q3

Q3

VCC

CLOCK

Q2

Q2

D0

Q0

Q0

RESET

GND

Q1

Q1

D1

MC74HC175A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 4.5 VVCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000600500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154 2


V







2.03.04.56.0


0.50.91.351.80


0.50.91.351.80


0.50.91.351.80


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ



MC74HC175A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ





– 55 to25C


VCCV





VOL






2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎÎÎÎÎ









µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter



– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit





2.03.04.56.0


6103035


4.88.02428


462024


MHz


tPLH,tPHL




2.03.04.56.0


150752622


190903228


2251103833


ns


tPHL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to Q or Q(Figures 2 and 4)


2.03.04.56.0


125702219

ÎÎÎÎÎÎÎÎÎ

155852724


1901103430

ÎÎÎÎÎÎÎÎÎ

ns


tTLH,tTHL




2.03.04.56.0


75271513


95321916


110362219


ns



ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10


ÎÎÎÎÎÎpF





MC74HC175A





ÎÎÎÎÎÎÎÎ







– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit





2.03.04.56.0


100452017

ÎÎÎÎÎÎÎÎÎ

125652521


150853026

ÎÎÎÎÎÎÎÎÎ

ns





2.03.04.56.0


5333


5333


5333


ns





2.03.04.56.0


100452017


125652521


150853026


ns





2.03.04.56.0


80451614


100652017


120852420


ns





2.03.04.56.0


80451614


100652017


120852420


ns





2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns


MC74HC175A


SWITCHING WAVEFORMS

Figure 1. Figure 2.

50%

50%

50%

50%

VCC

VCC

GND

GND

RESET

Q

Q

CLOCK

tPLH

tPHL

50%

DATA

CLOCK

VCC

VCC

GND

Figure 3.

GND


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 4.

1/fmax

CLOCK

Q or Q

tf trVCC

GND

90%50%

10%

90%50%

10%

tPLH tPHL

tTLH tTHL

tw

tw

trec

VALID

thtsu

TEST CIRCUIT

MC74HC175A


D Q

C

CR

D0

CLOCK

D1

D2

D3

RESET 1

13

12

5

9

4 2

3

7

6

10

11

15

14

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3


D Q

C

CR

D Q

C

CR

D Q

C

CR



MC74HC240A/D



This octal noninverting buffer/line driver/line receiver is designedto be used with 3–state memory address drivers, clock drivers, andother sub–oriented systems. The device has inverting outputs and twoactive–low output enables.

The HC240A is similar in function to the HC244A.








LOGIC DIAGRAM

DATAINPUTS

A1

A2

A3

A4

B1

B2

B3

B417

15

13

11

8

6

4

2 18

16

14

12

9

7

5

3YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

INVERTINGOUTPUTS

PIN 20 = VCCPIN 10 = GNDOUTPUT

ENABLESENABLE AENABLE B

1

19

FUNCTION TABLEInputs Outputs

Enable A,Enable B A, B YA, YB

L L HL H LH X Z

Z = high impedance

http://onsemi.com

MARKINGDIAGRAMS

1

20


SOIC WIDE–20DW SUFFIXCASE 751D

HC240AAWLYYWW

PDIP–20P SUFFIXCASE 738

1

20

MC74HC240ANAWLYYWW


1

20

1

20

120




MC74HC240ADW SOIC–WIDE 38 / Rail

MC74HC240ADWR2 SOIC–WIDE 1000 / Reel



PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

VCC

B1

YA4

B2

YA3

B3

HC240AALYW

1

20

MC74HC240A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V





Vin = VIH|Iout| 20 µA ÎÎÎÎ

ÎÎÎÎÎÎÎÎ

2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC240A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA











µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHL


Maximum Propagation Delay, A to YA or B to YB(Figures 1 and 3)


2.03.04.56.0


80401614


100502017


120602420


ns


tPLZ,tPHZ


Maximum Propagation Delay, Output Enable to YA or YB(Figures 2 and 4)


2.03.04.56.0


110602219


140702824


165803328


ns


tPZL,tPZH




2.03.04.56.0


110602219


140702824


165803328


ns


tTLH,tTHL




2.03.04.56.0


60231210

ÎÎÎÎÎÎÎÎÎ

75271513


90321815

ÎÎÎÎÎÎÎÎÎ

ns



ÎÎÎÎÎÎÎÎ—

ÎÎÎÎÎÎÎÎ10




Cout


Maximum Three–State Output Capacitance (Output inHigh–Impedance State)






pF



CPD Power Dissipation Capacitance (Per Transceiver Channel)* 32 pF


MC74HC240A


SWITCHING WAVEFORMS

DATA INPUTA OR B

OUTPUTYA OR YB

VCC

GND

tftr

90%50%

10%

90%50%

10%

tPHL tPLH

tTHL tTLH

ENABLE

OUTPUT Y

OUTPUT Y

50%

50%

50%90%

10%

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

Figure 1. Figure 2.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ AND tPZH.

1 kΩ

PIN DESCRIPTIONS

INPUTS

A1, A2, A3, A4, B1, B2, B3, B4(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in inverted formon the corresponding Y outputs, when the outputs areenabled.

CONTROLS

Enable A, Enable B (Pins 1, 19)

Output enables (active–low). When a low level is appliedto these pins, the outputs are enabled and the devices

function as inverters. When a high level is applied, theoutputs assume the high–impedance state.

OUTPUTS

YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of theoutput–enable pins, these outputs are either invertingoutputs or high–impedance outputs.

MC74HC240A


LOGIC DETAIL

DATAINPUT

A OR B

ENABLE AOR ENABLE B

TO THREE OTHERA OR B INVERTERS

ONE OF 8INVERTERS

YAORYB

VCC



MC74HC244A/D



This octal noninverting buffer/line driver/line receiver is designedto be used with 3–state memory address drivers, clock drivers, andother bus–oriented systems. The device has noninverting outputs andtwo active–low output enables.

The HC244A is similar in function to the HC240A.








LOGIC DIAGRAM

DATAINPUTS

A1

A2

A3

A4

B1

B2

B3

B417

15

13

11

8

6

4

2 18

16

14

12

9

7

5

3YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTINGOUTPUTS

PIN 20 = VCCPIN 10 = GNDOUTPUT

ENABLESENABLE AENABLE B

119



L L LL H HH X Z

Z = high impedance

http://onsemi.com

MARKINGDIAGRAMS

1

20



HC244AAWLYYWW


1

20

MC74HC244ANAWLYYWW


1

20

1

20

120








HC244AALYW

1

20

PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

VCC

B1

YA4

B2

YA3

B3

MC74HC244A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ






Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP, SOIC, SSOP or TSSOP Package)


260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V






ÎÎÎÎÎÎÎÎ

2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC244A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA











µA











µA

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the MotorolaHigh–Speed CMOS Data Book (DL129/D).




ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


– 55 to25C

ÎÎÎÎÎÎ85CÎÎÎÎÎÎÎÎ125C



tPLH,tPHL




2.03.04.56.0


96501815


115602320


135702723


ns


tPLZ,tPHZ




2.03.04.56.0


110602219


140702824


165803328


ns


tPZL,tPZH




2.03.04.56.0


110602219


140702824


165803328


ns


tTLH,tTHL




2.03.04.56.0


60231210


75271513


90321815


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



— ÎÎÎÎÎÎÎÎÎÎÎÎ




pF





MC74HC244A


SWITCHING WAVEFORMS

Figure 1. Figure 2.

VCC

GND

tftrDATA INPUT

A OR B

OUTPUTYA OR YB

10%50%90%

10%50%90%

tTLH

tPLH tPHL

tTHL

ENABLEA OR B

OUTPUT Y

OUTPUT Y

50%

50%

50%90%

10%

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

TEST CIRCUITS


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT



1 kΩ

PIN DESCRIPTIONS

INPUTS

A1, A2, A3, A4, B1, B2, B3, B4(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in noninvertedform on the corresponding Y outputs, when the outputs areenabled.

CONTROLS

Enable A, Enable B (Pins 1, 19)

Output enables (active–low). When a low level is appliedto these pins, the outputs are enabled and the devices

function as noninverting buffers. When a high level isapplied, the outputs assume the high impedance state.

OUTPUTS

YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of theoutput–enable pins, these outputs are either noninvertingoutputs or high–impedance outputs.

MC74HC244A


LOGIC DETAIL

DATAINPUT

A OR B

ENABLE A ORENABLE B


ONE OF 8INVERTERS

YAORYB

VCC



MC74HCT244A/D

$ $$ &"$%" "&" &" '$ !$ !%$#High–Performance Silicon–Gate CMOS

The MC74HCT244A is identical in pinout to the LS244. Thisdevice may be used as a level converter for interfacing TTL or NMOSoutputs to High–Speed CMOS inputs. The HCT244A is an octalnoninverting buffer line driver line receiver designed to be used with3–state memory address drivers, clock drivers, and other bus–orientedsystems. The device has non–inverted outputs and two active–lowoutput enables.

The HCT244A is the noninverting version of the HCT240. See alsoHCT241.


• TTL NMOS–Compatible Input Levels






LOGIC DIAGRAM

DATA INPUTS

A1

A2

A3

A4

B1

B2

B3

B417

15

13

11

8

6

4

2 18

16

14

12

9

7

5

3YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTINGOUTPUTS


OUTPUTENABLES

ENABLE AENABLE B

119



L L LL H HH X Z

Z = high impedance, X = don’t care

http://onsemi.com

MARKINGDIAGRAMS

1

20



HCT244AAWLYYWW


1

20

MC74HCT244ANAWLYYWW


1

20

1

20

120




MC74HCT244ADW SOIC–WIDE 38 / Rail

MC74HCT244ADWR2 SOIC–WIDE 1000 / Reel



HCT244AALYW

1

20

PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

VCC

B1

YA4

B2

YA3

B3

MC74HCT244A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



– 0.5 to + 7ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit











V

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ

V







4.55.5


4.45.4

ÎÎÎÎÎÎÎÎÎ

4.45.4


4.45.4

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL|Iout| 6 mA





3.7ÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ





ÎÎÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ

V




Vin = VIH or VIL|Iout| 6 mA


4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4


ÎÎÎÎÎÎÎÎ









µA











µA











µA



MC74HCT244A


ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


≥ –55C ÎÎÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ5.5



ÎÎÎÎÎÎmA

NOTES:1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola

High–Speed CMOS Data Book (DL129/D).2. Total Supply Current = ICC + Σ∆ICC.

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)





ÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎ

– 55 to25CÎÎÎÎÎÎÎÎ 85C

ÎÎÎÎÎÎÎÎ 125C



tPLH,tPHL







ns


tPLZ,tPHZ







ns


tPZL,tPZH







ns




ÎÎÎÎÎÎÎÎ

12 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

18 ÎÎÎÎÎÎ

ns




10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ


CoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






pF





SWITCHING WAVEFORMS

Figure 1. Figure 2.

3 V

GND

tftrINPUT

A OR B

OUTPUTYA OR YB

0.3 V1.3 V2.7 V

10%1.3 V

90%

tTLH

tPLH tPHL

tTHL

ENABLEA OR B

OUTPUT Y

OUTPUT Y

1.3 V

1.3 V

1.3 V90%

10%

tPZL tPLZ

tPZH tPHZ

3 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

MC74HCT244A


TEST CIRCUITS


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 4.


1 kΩ

LOGIC DETAIL

DATA INPUTA OR B

ENABLE A OR ENABLE B


ONE OF 8BUFFERS

YAORYB

VCC



MC74HC245A/D



The HC245A is a 3–state noninverting transceiver that is used for2–way asynchronous communication between data buses. The devicehas an active–low Output Enable pin, which is used to place the I/Oports into high–impedance states. The Direction control determineswhether data flows from A to B or from B to A.








LOGIC DIAGRAM

ADATAPORT

A8

A7

A6

A5

A3

A4

A2

A1

9

8

7

6

5

4

3

2

DIRECTION

OUTPUT ENABLE

1

19

PIN 10 = GNDPIN 20 = VCC

18

17

16

15

14

13

12

11

B1

B2

B3

B4

B5

B6

B7

B8

BDATAPORT

FUNCTION TABLE

Control Inputs

OutputEnable Direction Operation

L L Data Transmitted from Bus B to Bus A

L H Data Transmitted from Bus A to Bus B

H X Buses Isolated (High–Impedance State)

X = don’t care

http://onsemi.com

MARKINGDIAGRAMS

1

20



HC245AAWLYYWW


1

20

MC74HC245ANAWLYYWW

1

20

120






PIN ASSIGNMENT

A5

A3

A2

A1

DIRECTION

GND

A8

A7

A6

A4 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

B3

B2

B1

OUTPUT ENABLE

VCC

B8

B7

B6

B5

B4

MC74HC245A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎVI/O ÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Output Voltage (Referenced to GND) ÎÎÎÎÎ– 0.5 to VCC + 0.5ÎÎÎVÎÎÎÎÎÎÎÎIin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Input Current, per Pin



ÎÎÎÎII/OÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per PinÎÎÎÎÎÎÎÎÎÎ

± 35ÎÎÎÎÎÎ

mAÎÎÎÎÎÎÎÎ

ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


± 75ÎÎÎÎÎÎ





750500

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎ

C







Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8

ÎÎÎÎÎÎÎÎÎ

0.50.91.351.8


0.50.91.351.8

ÎÎÎÎÎÎÎÎÎ

V







2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC245A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA











µA











µA

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the MotorolaHigh–Speed CMOS Data Book (DL129/D).




ÎÎÎÎÎÎÎÎ







– 55 to25C

ÎÎÎÎÎÎÎÎÎ 85CÎÎÎÎÎÎÎÎÎÎÎÎ


Unit


tPLH,tPHL


Maximum Propagation Delay, A to B, B to A(Figures 1 and 3)


2.03.04.56.0


75551513


95701916


110802219


ns


tPLZ,tPHZ


Maximum Propagation Delay, Direction or Output Enable to A or B(Figures 2 and 4)


2.03.04.56.0


110902219

ÎÎÎÎÎÎÎÎÎ

1401102824


1651303328

ÎÎÎÎÎÎÎÎÎ

ns


tPZL,tPZH


Maximum Propagation Delay, Output Enable to A or B(Figures 2 and 4)


2.03.04.56.0


110902219


1401102824


1651303328


ns


tTLH,tTHL




2.03.04.56.0


60231210


75271513


90321815


ns



Maximum Input Capacitance (Pin 1 or Pin 19)ÎÎÎÎÎÎÎÎ

—ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ



Maximum Three–State I/O Capacitance(I/O in High–Impedance State)






pF



CPD Power Dissipation Capacitance (Per Transceiver Channel)* 40 pF


MC74HC245A


SWITCHING WAVEFORMS

VCC

GND

tftrINPUT

A OR B

OUTPUTB OR A

10%50%90%

10%50%90%

tTLH

tPLH tPHL

tTHL

Figure 1.

OUTPUTENABLE

A OR B

A OR B

50%

50%

50%90%

10%

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

VCC

GND50%

Figure 2.

DIRECTION

TEST CIRCUITS


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 4.


1 kΩ

MC74HC245A



ADATAPORT

BDATAPORT

OUTPUT ENABLE

DIRECTION

A1

A2

A3

A4

A5

A6

A7

A8

2

3

4

5

6

7

8

9

19

1

B1

B2

B3

B4

B5

B6

B7

B8

18

17

16

15

14

13

12

11



MC74HCT245A/D

! !! #!" # $! ! "! High–Performance Silicon–Gate CMOS

The MC74HCT245A is identical in pinout to the LS245. Thisdevice may be used as a level converter for interfacing TTL or NMOSoutputs to High Speed CMOS inputs.

The MC74HCT245A is a 3–state noninverting transceiver that isused for 2–way asynchronous communication between data buses.The device has an active–low Output Enable pin, which is used toplace the I/O ports into high–impedance states. The Direction controldetermines whether data flows from A to B or from B to A.• Output Drive Capability: 15 LSTTL Loads







LOGIC DIAGRAM

ADATAPORT

A8

A7

A6

A5

A3

A4

A2

A1

9

8

7

6

5

4

3

2

DIRECTION

OUTPUT ENABLE

1

19PIN 20 = VCCPIN 10 = GND

18

17

16

15

14

13

12

11

B1

B2

B3

B4

B5

B6

B7

B8

BDATAPORT


Design Criteria ÎÎÎÎÎÎ

ValueÎÎÎÎÎÎ

Units


Internal Gate Count* ÎÎÎÎÎÎ

76 ÎÎÎÎÎÎ

ea


Internal Gate Propagation Delay ÎÎÎÎÎÎ

1.0ÎÎÎÎÎÎ

ns


Internal Gate Power DissipationÎÎÎÎÎÎ

5.0ÎÎÎÎÎÎ

µWÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Speed Power ProductÎÎÎÎÎÎ

0.005ÎÎÎÎÎÎ

pJ


FUNCTION TABLE

Control Inputs

OutputEnable Direction Operation

L L Data Transmitted from Bus B to Bus A

L H Data Transmitted from Bus A to Bus B

H X Buses Isolated (High–Impedance State)X = Don’t Care

http://onsemi.com

MARKINGDIAGRAMS

1

20



HCT245AAWLYYWW


1

20

MC74HCT245ANAWLYYWW


1

20

1

20

120








HCT245AALYW

1

20

PIN ASSIGNMENT

A5

A3

A2

A1

DIRECTION

GND

A8

A7

A6

A4 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

B3

B2

B1

OUTPUT ENABLE

VCC

B8

B7

B6

B5

B4

MC74HCT245A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions



– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VIH ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ

V







4.55.5


0.80.8

ÎÎÎÎÎÎÎÎÎ

0.80.8


0.80.8

ÎÎÎÎÎÎÎÎÎ

V


VOH ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ









V

ÎÎÎÎÎÎÎÎ



Vin = VIH or VIL|Iout| 6.0 mA ÎÎÎÎ

ÎÎÎÎ4.5 ÎÎÎÎÎÎÎÎ

3.98 ÎÎÎÎÎÎ

3.84ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ






4.55.5


0.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.1


0.10.1

ÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ4.5

ÎÎÎÎÎÎÎÎ0.26

ÎÎÎÎÎÎ0.33ÎÎÎÎÎÎÎÎ0.4


ÎÎÎÎIinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage CurrentÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND, Pins 1 or 19ÎÎÎÎÎÎÎÎ

5.5ÎÎÎÎÎÎÎÎ

± 0.1ÎÎÎÎÎÎ


± 1.0ÎÎÎÎÎÎ

µAÎÎÎÎÎÎÎÎÎÎÎÎ










µA


IOZ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



Output in High–Impedance StateVin = VIL or VIHVout = VCC or GND, I/O Pins






µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


≥ –55CÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ


Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



5.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



mA




MC74HCT245A













Unit



Maximum Propagation Delay, A to B or B to A(Figures 1 and 3)

ÎÎÎÎÎÎÎÎ

22 ÎÎÎÎÎÎÎÎ

28 ÎÎÎÎÎÎÎÎ

33 ÎÎÎÎÎÎ

ns


tPLZ,tPHZ


Maximum Propagation Delay, Direction or Output Enable to A or B(Figures 2 and 4)





ns


tPZL,tPZH


Maximum Propagation Delay, Output Enable to A or 8(Figures 2 and 4)





ns



Maximum Output Transition Time. any Output(Figures 1 and 3)

ÎÎÎÎÎÎÎÎ

12 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

18 ÎÎÎÎÎÎ

ns



Maximum Input Capacitance (Pin 1 or 19)ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ


CoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three–State I/O Capacitance, (I/O in High–ImpedanceState)





pF





MC74HCT245A


SWITCHING WAVEFORMS

3.0 V

GND

tftrINPUT

A OR B

OUTPUTB OR A

0.3 V1.3 V2.7 V

10%1.3 V

90%

tTLH

tPLH tPHL

tTHL

Figure 1.

OUTPUTENABLE

A OR B

A OR B

1.3 V

1.3 V

1.3 V90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

3.0 V

GND1.3 V 1.3 V

Figure 2.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT



1 kΩ

DIRECTION

MC74HCT245A



ADATAPORT B

DATAPORT

OUTPUT ENABLE

DIRECTION

A1

A2

A3

A4

A5

A6

A7

A8

2

3

4

5

6

7

8

9

19

1

B1

B2

B3

B4

B5

B6

B7

B8

18

17

16

15

14

13

12

11



MC74HC273A/D



This device consists of eight D flip–flops with common Clock andReset inputs. Each flip–flop is loaded with a low–to–high transition ofthe Clock input. Reset is asynchronous and active low.








LOGIC DIAGRAM

DATAINPUTS

D0

11CLOCK

D1

D2

D3

D4

D5

D6

D718

17

14

13

8

7

4

3

1RESET

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2


NONINVERTINGOUTPUTS

FUNCTION TABLEInputs Output

Reset Clock D Q




Value ÎÎÎÎÎÎ

Units



66 ÎÎÎÎÎÎ

ea


Internal Gate Propagation DelayÎÎÎÎÎÎÎÎ

1.5ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


5.0ÎÎÎÎÎÎ

µWÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Speed Power ProductÎÎÎÎÎÎÎÎ

.0075ÎÎÎÎÎÎ

pJ


http://onsemi.com

MARKINGDIAGRAMS

1

20



HC273AAWLYYWW


1

20

MC74HC273ANAWLYYWW


1

20

1

20

120








HC273AALYW

1

20

PIN ASSIGNMENT

Q2

D1

D0

Q0

RESET

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CLOCK

Q4

D4

D5

Q5

MC74HC273A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V






ÎÎÎÎÎÎÎÎ

2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC273A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA











µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit





2.03.04.56.0


6.0153035


5.0102428


4.08.02024


MHz


tPLHtPHL




2.03.04.56.0


145902925


1801203631


2201404438


ns


tPHL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


145902925


1801203631


2201404438


ns


tTLHtTHL




2.03.04.56.0


75271513

ÎÎÎÎÎÎÎÎÎ

95321916


110362219

ÎÎÎÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Input Capacitance

ÎÎÎÎÎÎÎÎ10


ÎÎÎÎÎÎpF





MC74HC273A




ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VCCÎÎÎÎÎÎÎÎÎÎ

– 55 to 25CÎÎÎÎÎÎÎÎÎÎ

85C ÎÎÎÎÎÎÎÎÎÎ 125C ÎÎ


SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter ÎÎÎÎÎÎÎÎ

Fig. ÎÎÎÎÎÎ

VCCVolts ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

Unit



Minimum Setup Time, Data to Clock ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


60231210



75271513



90321815


ÎÎÎÎÎÎÎÎ

ns


th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


3.03.03.03.0



3.03.03.03.0



3.03.03.03.0


ÎÎÎÎÎÎÎÎ

ns


trec ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive toClock



2.03.04.56.0


5.05.05.05.0



5.05.05.05.0



5.05.05.05.0


ÎÎÎÎÎÎÎÎ

ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


60231210



75271513



90321815


ÎÎÎÎÎÎÎÎ

ns



Minimum Pulse Width, Reset ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


60231210



75271513



90321815


ÎÎÎÎÎÎÎÎ

ns


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1000800500400

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1000800500400

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1000800500400

ÎÎÎÎÎÎ

ns

MC74HC273A


SWITCHING WAVEFORMS

Figure 1.

CLOCK

Q

tr tfVCC

GND

90%50%

10%

90%50%

10%

tPLH tPHL

tTLH tTHL

50%

DATA

CLOCK

VCC

Figure 2.

VALID

GND


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3.

tw

1/fmax

VCC

GND

tsu th

50%

RESET

Q

CLOCK

tw

50%

50%

50%

VCC

GND

VCC

GND

tPHL


trec


C

D RQ

D03

2Q0

C

D RQ

D14

5Q1

C

D RQ

D27

6Q2

C

D RQ

D38

9Q3

C

D RQ

D413

12Q4

C

D RQ

D514

15Q5

C

D RQ

D617

16Q6

C

D RQ

D718

19Q7

11

1

DATAINPUTS

NONINVERTINGOUTPUTS



MC74HCT273A/D

! #! !#! !"! High–Performance Silicon–Gate CMOS

The MC74HCT273A may be used as a level converter forinterfacing TTL or NMOS outputs to High–Speed CMOS inputs.

The HCT273A is identical in pinout to the LS273.This device consists of eight D flip–flops with common Clock and

Reset inputs. Each flip–flop is loaded with a low–to–high transition ofthe Clock input. Reset is asynchronous and active low.








LOGIC DIAGRAM

DATAINPUTS

D0

11CLOCK

D1

D2

D3

D4

D5

D6

D718

17

14

13

8

7

4

3

1RESET

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2


NONINVERTINGOUTPUTS

FUNCTION TABLE

Inputs Output

Reset Clock D Q


X = Don’t CareZ = High Impedance

http://onsemi.com

MARKINGDIAGRAMS

1

20



HCT273AAWLYYWW


1

20

MC74HCT273ANAWLYYWW

1

20

120






PIN ASSIGNMENT

Q2

D1

D0

Q0

RESET

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CLOCK

Q4

D4

D5

Q5

MC74HCT273A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA






mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ


Lead Temperature, 1 mm from Case for 10 Seconds(SOIC or Plastic DIP)


260ÎÎÎÎÎÎ

C


†Derating — Plastic DIP: – 10 mW/C from 65 to 125C SOIC Package: – 7 mW/C from 65 to 125C





MinÎÎÎÎ

MaxÎÎÎÎÎÎ




4.5ÎÎÎÎ

5.5ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ


DC Input Voltage, Output Voltage (Referenced to GND)ÎÎÎÎÎÎ

0ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

CÎÎÎÎÎÎÎÎ


Input Rise and Fall Time (Figure 1)ÎÎÎÎÎÎ

0ÎÎÎÎ

500ÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ





– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ

V







4.55.5


0.80.8

ÎÎÎÎÎÎÎÎÎ

0.80.8


0.80.8

ÎÎÎÎÎÎÎÎÎ

V











V

ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

4.5ÎÎÎÎÎÎÎÎ

3.98ÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ






4.55.5


0.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.1


0.10.1

ÎÎÎÎÎÎÎÎÎ

V






4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4







± 0.1 ÎÎÎÎÎÎ


± 1.0ÎÎÎÎÎÎ

µA











µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ≥ –55C

ÎÎÎÎÎÎÎÎÎÎÎÎ25C to 125C


ÎÎÎÎÎÎÎÎ





5.5


2.9


2.4

ÎÎÎÎÎÎÎÎÎ

mA




MC74HCT273A





ÎÎÎÎÎÎÎÎ







– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit


fmax ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle) ÎÎÎÎÎÎÎÎ

1, 4 ÎÎÎÎÎÎÎÎ

30 ÎÎÎÎÎÎ

24 ÎÎÎÎÎÎÎÎ

20 ÎÎÎÎÎÎ

MHz


tPLH,tPHL


Maximum Propagation Delay, Clock to Q ÎÎÎÎÎÎÎÎ

1, 4 ÎÎÎÎÎÎÎÎ

25 ÎÎÎÎÎÎ

28 ÎÎÎÎÎÎÎÎ

35 ÎÎÎÎÎÎ

ns


tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to QÎÎÎÎÎÎÎÎ

2, 4ÎÎÎÎÎÎÎÎ

25ÎÎÎÎÎÎ

28ÎÎÎÎÎÎÎÎ

35ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tTLH,tTHL


Maximum Output Transition Time, Any OutputÎÎÎÎÎÎÎÎÎÎÎÎ

1, 5ÎÎÎÎÎÎÎÎÎÎÎÎ




ns







ÎÎÎÎÎÎÎÎ






– 55 to 25C ÎÎÎÎÎÎÎÎÎÎ

85C ÎÎÎÎÎÎÎÎ 125CÎÎÎ




Fig. ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock ÎÎÎÎÎÎ

3 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ

th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data ÎÎÎÎÎÎ

3 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ

trec ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Set or Reset Inactive to Clock ÎÎÎÎÎÎ

2 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ

tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock ÎÎÎÎÎÎ

1 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ


Minimum Pulse Width, Set or Reset ÎÎÎÎÎÎ

2 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ


Maximum Input Rise and Fall Times ÎÎÎÎÎÎ




500ÎÎÎÎÎÎ

ns

MC74HCT273A


Figure 1.

CLOCK

Q

tr tf3.0 V

GND

2.7 V1.3 V

0.3 V

90%1.3 V

10%

tPLH tPHL

tTLH tTHL

1.3 V

DATA

CLOCK

3.0 V

Figure 2.

VALID

GND


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3.

tw1/fmax

3.0 V

GND

tsu th

1.3 V

RESET

Q

CLOCK

tw

1.3 V

1.3 V

1.3 V

3.0 V

GND

3.0 V

GND

tPHL


trec


C

D RQ

D03

2Q0

C

D RQ

D14

5Q1

C

D RQ

D27

6Q2

C

D RQ

D38

9Q3

C

D RQ

D413

12Q4

C

D RQ

D514

15Q5

C

D RQ

D617

16Q6

C

D RQ

D718

19Q7

11

1

DATAINPUTS

NONINVERTINGOUTPUTS

CLOCK

RESET

SWITCHING WAVEFORMS



MC74HC373A/D



These latches appear transparent to data (i.e., the outputs changeasynchronously) when Latch Enable is high. When Latch Enable goeslow, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, butwhen Output Enable is high, all device outputs are forced to thehigh–impedance state. Thus, data may be latched even when theoutputs are not enabled.

The HC373A is identical in function to the HC573A which has thedata inputs on the opposite side of the package from the outputs tofacilitate PC board layout.

The HC373A is the non–inverting version of the HC533A.








http://onsemi.com

MARKINGDIAGRAMS

1

20



HC373AAWLYYWW


1

20

MC74HC373ANAWLYYWW


1

20

1

20

120








HC373AALYW

1

20

MC74HC373A


LOGIC DIAGRAM

DATAINPUTS

D0

D1

D2

D3

D4

D5

D6

D718

17

14

13

8

7

4

3

1OUTPUT ENABLE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2


NONINVERTINGOUTPUTS

11LATCH ENABLE

FUNCTION TABLEInputs Output

Output LatchEnable Enable D Q

L H H HL H L LL L X No ChangeH X X Z


PIN ASSIGNMENT

Q2

D1

D0

Q0

OUTPUTENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

LATCHENABLE

Q4

D4

D5

Q5



Value ÎÎÎÎÎÎ

Units



46.5 ÎÎÎÎÎÎ

ea



1.5 ÎÎÎÎÎÎ

ns


Internal Gate Power Dissipation ÎÎÎÎÎÎÎÎ

5.0 ÎÎÎÎÎÎ

µW



0.0075 ÎÎÎÎÎÎ

pJ


MC74HC373A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V






ÎÎÎÎÎÎÎÎ

2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC373A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV













µA











µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tPLHtPHL


Maximum Propagation Delay, Input D to Q(Figures 1 and 5)


2.03.04.56.0


125802521


1551103126


1901303832


ns


tPLHtPHL


Maximum Propagation Delay, Latch Enable to Q(Figures 2 and 5)


2.03.04.56.0


140902824


1751203530


2101404236


ns


tPLZtPHZ


Maximum Propagation Delay, Output Enable to Q(Figures 3 and 6)


2.03.04.56.0


1501003026


1901253833


2251504538


ns


tPZLtPZH




2.03.04.56.0


1501003026

ÎÎÎÎÎÎÎÎÎ

1901253833


2251504538

ÎÎÎÎÎÎÎÎÎ

ns


tTLHtTHL




2.03.04.56.0


60231210


75271513


90321815


ns



ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ10











pF





MC74HC373A




ÎÎÎÎÎÎÎÎ










SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Fig.ÎÎÎÎÎÎ


MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input D to Latch Enable ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


25205.05.0



30256.06.0



40308.07.0


ÎÎÎÎÎÎÎÎ

ns


th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Latch Enable to Input D ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


5.05.05.05.0



5.05.05 05.0



5.05.05.05.0


ÎÎÎÎÎÎÎÎ

ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Latch Enable ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


60231210



75271513



90321815


ÎÎÎÎÎÎÎÎ

ns


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0



1000800500400



1000800500400



1000800500400

ÎÎÎÎÎÎÎÎ

ns

SWITCHING WAVEFORMS

Figure 1. Figure 2.

VCC

GND

tftr

INPUT D

Q

10%50%90%

10%50%90%

tTLH

tPLH tPHL

tTHL

VCC

GND50%LATCH ENABLE

tPLH tPHL

Q

tw

50%

Figure 3. Figure 4.

50%

50%

1.3 VQ

tPZL tPLZ

tPZH tPHZ

10%

90%

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

Q

OUTPUTENABLE

50%

INPUT D

LATCH ENABLE

VCC

VCC

GND

GND

VALID

thtsu

50%

MC74HC373A


TEST CIRCUITS


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 5. Figure 6.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUTCONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ AND tPZH.

1 kΩ


D03

D Q

LE

2Q0

11

1

D14

D Q

LE

5Q1

D27

D Q

LE

6Q2

D38

D Q

LE

9Q3

D413

D Q

LE

12Q4

D514

D Q

LE

15Q5

D617

D Q

LE

16Q6

D718

D Q

LE

19Q7



MC74HCT373A/D

! High–Performance Silicon–Gate CMOS


The HCT373A is identical in pinout to the LS373.The eight latches of the HCT373A are transparent D–type latches.

While the Latch Enable is high the Q outputs follow the Data Inputs.When Latch Enable is taken low, data meeting the setup and holdtimes becomes latched.

The Output Enable does not affect the state of the latch, but whenOutput Enable is high, all outputs are forced to the high–impedancestate. Thus, data may be latched even when the outputs are notenabled.

The HCT373A is identical in function to the HCT573A, which hasthe input pins on the opposite side of the package from the output pins.This device is similar in function to the HCT533A, which hasinverting outputs.








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MARKINGDIAGRAMS

1

20



HCT373AAWLYYWW


1

20

MC74HCT373ANAWLYYWW


1

20

1

20

120








PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

VCC

B1

YA4

B2

YA3

B3

HCT373AALYW

1

20

MC74HCT373A


LOGIC DIAGRAM

DATAINPUTS

D0

D1

D2

D3

D4

D5

D6

D718

17

14

13

8

7

4

3

1OUTPUT ENABLE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2


NONINVERTINGOUTPUTS

11LATCH ENABLE

PIN ASSIGNMENT

Q2

D1

D0

Q0

OUTPUTENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

LATCHENABLE

Q4

D4

D5

Q5

FUNCTION TABLE

Inputs Output



X = don’t careZ = high impedance


Design Criteria


Value

ÎÎÎÎÎÎÎÎÎ

Units



49 ÎÎÎÎÎÎ

ea.



1.5 ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power DissipationÎÎÎÎÎÎÎÎÎÎÎÎ



Speed Power Product


.0075

ÎÎÎÎÎÎÎÎÎ

pJ


MC74HCT373A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit











V

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ

V







4.55.5


4.45.4

ÎÎÎÎÎÎÎÎÎ

4.45.4


4.45.4

ÎÎÎÎÎÎÎÎÎ

V










ÎÎÎÎ





ÎÎÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ

V






4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4


ÎÎÎÎÎÎÎÎ









µA











µA











µA



MC74HCT373A


ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


≥ –55C ÎÎÎÎÎÎÎÎÎÎ

25C to 125CÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ



2.4 ÎÎÎÎÎÎ

NOTE: 1. Total Supply Current = ICC + Σ∆ICC.NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit



Symbol


Parameter


– 55 to25C

ÎÎÎÎÎÎÎÎÎÎÎÎ 85C


ÎÎÎÎÎÎÎÎÎ

Unit


tPLH,tPHL







ns




ÎÎÎÎÎÎÎÎ

32 ÎÎÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

48 ÎÎÎÎÎÎ

ns


tPLZ,tPHZ







ns


tPZL,tPZH







ns




ÎÎÎÎÎÎÎÎ

12 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

18 ÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Input Capacitance

ÎÎÎÎÎÎÎÎ10

ÎÎÎÎÎÎÎÎ10

ÎÎÎÎÎÎÎÎ10



Cout







pF



CPD Power Dissipation Capacitance (Per Latch)* 65 pF


TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎ



Guaranteed LimitÎÎÎÎÎÎÎÎÎÎÎ


Symbol


Parameter


– 55 to25C



ÎÎÎÎÎÎÎÎÎ

Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input D to Latch Enable(Figure 4)





ns


th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Latch Enable to Input D(Figure 4)

ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

13 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎ

ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Latch Enable(Figure 2)





ns


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






ns

MC74HCT373A



D03

D Q

LE

2Q0

11

1

LATCHENABLE

OUTPUTENABLE

D14

D Q

LE

5Q1

D27

D Q

LE

6Q2

D38

D Q

LE

9Q3

D413

D Q

LE

12Q4

D514

D Q

LE

15Q5

D617

D Q

LE

16Q6

D718

D Q

LE

19Q7

SWITCHING WAVEFORMS

Figure 1. Figure 2.

3 V

GND

tftr

INPUT D

Q

0.3 V1.3 V2.7 V

10%1.3 V

90%

tTLH

tPLH tPHL

tTHL

3 V

GND1.3 VLATCH ENABLE

tPLH tPHL

Q

tw

1.3 V

1.3 V

1.3 V

1.3 V

1.3 VQ

tPZL tPLZ

tPZH tPHZ

10%

90%

3 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

Figure 3. Figure 4.

Q

OUTPUTENABLE

1.3 V

INPUT D

LATCH ENABLE

3 V

3 V

GND

GND

VALID

thtsu

1.3 V

MC74HCT373A



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 5. Figure 6.


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

TEST CIRCUITS



MC74HC374A/D



Data meeting the setup time is clocked to the outputs with the risingedge of the clock. The Output Enable input does not affect the states ofthe flip–flops, but when Output Enable is high, the outputs are forcedto the high–impedance state; thus, data may be stored even when theoutputs are not enabled.

The HC374A is identical in function to the HC574A which has theinput pins on the opposite side of the package from the output. Thisdevice is similar in function to the HC534A which has invertingoutputs.








LOGIC DIAGRAM

DATAINPUTS

D0

11CLOCK

D1

D2

D3

D4

D5

D6

D718

17

14

13

8

7

4

3

1OUTPUT ENABLE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2


NONINVERTINGOUTPUTS

FUNCTION TABLE

Inputs Output

OutputEnable Clock D Q

L H HL L LL L,H, X No ChangeH X X Z


http://onsemi.com

MARKINGDIAGRAMS

1

20



HC374AAWLYYWW


1

20

MC74HC374ANAWLYYWW


1

20

1

20

120








HC374AALYW

1

20

PIN ASSIGNMENT

Q2

D1

D0

Q0

OUTPUTENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CLOCK

Q4

D4

D5

Q5

MC74HC374A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ







2.03.04.56.0


1.502.103.154.20


1.502.103.154.20


1.502.103.154.20


V







2.03.04.56.0


0.500.901.351.80


0.500.901.351.80


0.500.901.351.80


V







2.04.56.0


1.904.405.90

ÎÎÎÎÎÎÎÎÎ

1.904.405.90


1.904.405.90

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.482.985.48


2.343.845.34


2.203.705.20


V



MC74HC374A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ





– 55 to25C


VCCV





VOL






2.04.56.0


0.100.100.10


0.100.100.10


0.100.100.10


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40

ÎÎÎÎÎÎÎÎÎ

V










µA











µA











µA




ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit



Maximum Clock Frequency (50% Duty Cycle) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.56.0


6153035


5102428


482024


MHz


tPLHtPHL


Maximum Propagation Delay, Input Clock to Q(Figures 1 and 5)


2.03.04.56.0


125802521


1551103126


1901303832


ns


tPLZtPHZ




2.03.04.56.0


1501003026


1901253833


2251504538


ns


tPLZtPHZ




2.03.04.56.0


1501003026


1901253833


2251504538


ns


tTLHtTHL




2.03.04.56.0


75271513


95321916


110362219


ns




ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF


Cout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎ

pF





MC74HC374A




ÎÎÎÎÎÎÎÎ










SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Fig.ÎÎÎÎÎÎ


MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


5040109



65501311



75601513


ÎÎÎÎÎÎÎÎ

ns


th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


5.05.05.05.0



5.05 05.05.0



5.05.05.05.0


ÎÎÎÎÎÎÎÎ

ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock ÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


60231210



75271513



90321815


ÎÎÎÎÎÎÎÎ

ns


tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0



1000800500400



1000800500400



1000800500400

ÎÎÎÎÎÎÎÎ

ns

SWITCHING WAVEFORMS

Figure 1.

tr tfVCC

GND

tTHLtTLH

90%

50%10%

90%50%

10%CLOCK

tPLH tPHL

Q

tW1/fmax

50%

50%

50%

OUTPUTENABLE

Q

tPZL tPLZ

tPZH tPHZ

10%

90%

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

50%

DATA

CLOCK

VCC

VCC

GND

GND

VALID

thtsu

50%

Q

Figure 2.

Figure 3.

MC74HC374A


TEST CIRCUITS

Figure 4.


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

Figure 5.


D03

D Q

C

Q02

D14

D Q

C

Q15

D27

D Q

C

Q26

D38

D Q

C

Q39

D413

D Q

C

Q412

D514

D Q

C

Q515

D617

D Q

C

Q616

D718

D Q

C

Q719

Clock

OutputEnable

11

1



MC74HCT374A/D

" # ! High–Performance Silicon–Gate CMOS


The HCT374A is identical in pinout to the LS374.Data meeting the setup and hold time is clocked to the outputs with

the rising edge of Clock. The Output Enable does not affect the state ofthe flip–flops, but when Output Enable is high, the outputs are forcedto the high–impedance state. Thus, data may be stored even when theoutputs are not enabled.

The HCT374A is identical in function to the HCT574A, which hasthe input pins on the opposite side of the package from the output pins.This device is similar in function to the HCT534A, which hasinverting outputs.








• Improvements over HCT374— Improved Propagation Delays— 50% Lower Quiescent Power— Improved Input Noise and Latchup Immunity

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MARKINGDIAGRAMS

1

20



HCT374AAWLYYWW


1

20

MC74HCT374ANAWLYYWW


1

20

1

20

120








HCT374AALYW

1

20

MC74HCT374A


LOGIC DIAGRAM

DATAINPUTS

D0

11CLOCK

D1

D2

D3

D4

D5

D6

D718

17

14

13

8

7

4

3

1OUTPUT ENABLE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2


NONINVERTINGOUTPUTS

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

OutputEnable Clock D Q



Q2

D1

D0

Q0

OUTPUTENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CLOCK

Q4

D4

D5

Q5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria

ÎÎÎÎÎÎÎÎValue

ÎÎÎÎÎÎUnitsÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎInternal Gate Count*

ÎÎÎÎÎÎÎÎ

69ÎÎÎÎÎÎ

ea.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay

ÎÎÎÎÎÎÎÎ1.5

ÎÎÎÎÎÎnsÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎInternal Gate Power DissipationÎÎÎÎÎÎÎÎ5.0

ÎÎÎÎÎÎµWÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎSpeed Power ProductÎÎÎÎÎÎÎÎ.0075

ÎÎÎÎÎÎpJ


MC74HCT374A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit











V

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ


0.80.8ÎÎÎÎÎÎ

V







4.55.5


4.45.4

ÎÎÎÎÎÎÎÎÎ

4.45.4


4.45.4

ÎÎÎÎÎÎÎÎÎ

V










ÎÎÎÎ





ÎÎÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ


0.10.1ÎÎÎÎÎÎ

V






4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4


ÎÎÎÎÎÎÎÎ









µA











µA











µA



MC74HCT374A


ÎÎÎÎÎÎÎÎ

∆ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



Vin = 2.4 V, Any One InputVin = VCC or GND, Other Inputs


≥ –55CÎÎÎÎÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎ5.5ÎÎÎÎÎÎÎÎÎÎ


2.4ÎÎÎÎÎÎmA

NOTE: 1. Total Supply Current = ICC + Σ∆ICC.NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit



Symbol


Parameter


– 55 to25C



ÎÎÎÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fmaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






MHz




ÎÎÎÎÎÎÎÎ

31 ÎÎÎÎÎÎÎÎ

39 ÎÎÎÎÎÎÎÎ

47 ÎÎÎÎÎÎ

ns


tPLZ,tPHZ







ns


tPZL,tPZH







ns


tTLH,tTHL







ns




10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF


Cout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎ

pF





TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎ





Symbol


Parameter


– 55 to25C



ÎÎÎÎÎÎÎÎÎ

Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






ns


th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ



5.0 ÎÎÎÎÎÎ

ns


twÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






ns








ns

MC74HCT374A


SWITCHING WAVEFORMS

Figure 1.

tr tfVCC

GND

tTHLtTLH

90%1.3 V10%

2.7 V1.3 V

0.3 V

CLOCK

tPLH tPHL

Q

tw1/fmax

1.3 V

1.3 V

1.3 V

OUTPUTENABLE

Q

tPZL tPLZ

tPZH tPHZ

10%

90%

3 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

1.3 V

DATA

CLOCK

3 V

3 V

GND

GND

VALID

thtsu

1.3 V

Figure 2.

Figure 3.

Q

TEST CIRCUITS

Figure 4.


C

D0 D1 D2 D3 D4 D5 D6 D73 4 7 8 13 14 17 18

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q72 5 6 9 12 15 16 19

D Q

CLOCK

OUTPUTENABLE

11

1


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUTCONNECT TO VCC WHENTESTING tPLZ AND tPZLCONNECT TO GND WHENTESTING tPHZ AND tPZH

1 kΩ

Figure 5.

C

D Q

C

D Q

C

D Q

C

D Q

C

D Q

C

D Q

C

D Q



MC74HC390A/D

" ! ÷ ÷ High–Performance Silicon–Gate CMOS


This device consists of two independent 4–bit counters, eachcomposed of a divide–by–two and a divide–by–five section. Thedivide–by–two and divide–by–five counters have separate clockinputs, and can be cascaded to implement various combinations of ÷ 2and/or ÷ 5 up to a ÷ 100 counter.

Flip–flops internal to the counters are triggered by high–to–lowtransitions of the clock input. A separate, asynchronous reset isprovided for each 4–bit counter. State changes of the Q outputs do notoccur simultaneously because of internal ripple delays. Therefore,decoded output signals are subject to decoding spikes and should notbe used as clocks or strobes except when gated with the Clock of theHC390A.• Output Drive Capability: 10 LSTTL Loads





• In Compliance with the Requirements Defined by JEDEC StandardNo 7A


LOGIC DIAGRAM

QA

QBQCQD

1, 15

4, 12

2, 14

3, 13

5, 11

6, 107, 9


CLOCK A

RESET

CLOCK B

÷ 2COUNTER

÷ 5COUNTER

FUNCTION TABLE

Clock

A B Reset Action

X X H Reset÷ 2 and ÷ 5

X L Increment÷ 2

X L Increment÷ 5

SO–16D SUFFIX

CASE 751B

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1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC390ANAWLYYWW

1

16

HC390AAWLYWW


HC390AALYW

1

16








PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

CLOCK Bb

QAb

RESET b

CLOCK Ab

VCC

QDb

QCb

QBb

CLOCK Ba

QAa

RESET a

CLOCK Aa

GND

QDa

QCa

QBa

MC74HC390A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 4.5 VVCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

0000

ÎÎÎÎÎÎ

1000600500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ



MC74HC390A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ





– 55 to25C


VCCV





VOL






2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎÎÎÎÎ









µA











µA


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)ÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit





2.03.04.56.0


10153050


9142845


8122540


MHz


tPLH,tPHL


Maximum Propagation Delay, Clock A to QA(Figures 1 and 3)


2.03.04.56.0


70402420

ÎÎÎÎÎÎÎÎÎ

80453026


90503631

ÎÎÎÎÎÎÎÎÎ

ns


tPLH,tPHL


Maximum Propagation Delay, Clock A to QC(QA connected to Clock B)

(Figures 1 and 3)


2.03.04.56.0


2001605849


2501856562


3002107068


ns


tPLH,tPHL


Maximum Propagation Delay, Clock B to QB(Figures 1 and 3)


2.03.04.56.0


70402622


80453328


90503933


ns


tPLH,tPHL


Maximum Propagation Delay, Clock B to QC(Figures 1 and 3)


2.03.04.56.0


90563731


105704639


1801005648


ns


tPLH,tPHL


Maximum Propagation Delay, Clock B to QD(Figures 1 and 3)


2.03.04.56.0


70402622

ÎÎÎÎÎÎÎÎÎ

80453328


90503933

ÎÎÎÎÎÎÎÎÎ

ns



Maximum Propagation Delay, Reset to any Q(Figures 2 and 3)


2.03.04.56.0


80483026


95653833


110754439


ns


tTLH,tTHL




2.03.04.56.0


75271513


95321915


110362219


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).


CPD Power Dissipation Capacitance (Per Counter)* 35 pF


MC74HC390A





ÎÎÎÎÎÎÎÎ







– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit



Minimum Recovery Time, Reset Inactive to Clock A or Clock B(Figure 2)


2.03.04.56.0


2515109

ÎÎÎÎÎÎÎÎÎ

30201311


40301513

ÎÎÎÎÎÎÎÎÎ

ns



Minimum Pulse Width, Clock A, Clock B(Figure 1)


2.03.04.56.0


75271513


95321915


110362219


ns





2.03.04.56.0


75272018


95322422


110363028


ns


tf, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns


PIN DESCRIPTIONSINPUTSClock A (Pins 1, 15) and Clock B (Pins 4, 15)

Clock A is the clock input to the ÷ 2 counter; Clock B isthe clock input to the ÷ 5 counter. The internal flip–flops aretoggled by high–to–low transitions of the clock input.

CONTROL INPUTSReset (Pins 2, 14)

Asynchronous reset. A high at the Reset input preventscounting, resets the internal flip–flops, and forces QAthrough QD low.

OUTPUTSQA (Pins 3, 13)

Output of the ÷ 2 counter.

QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)

Outputs of the ÷ 5 counter. QD is the most significant bit.QA is the least significant bit when the counter is connectedfor BCD output as in Figure 4. QB is the least significant bitwhen the counter is operating in the bi–quinary mode as inFigure 5.

SWITCHING WAVEFORMS

Q

trtf

tPLH tPHL

tTLH tTHL

VCC

GNDCLOCK

10%50%90%

1/fmax

tw

trec

RESET

Figure 1. Figure 2.

VCC

GND

VCC

GND

10%50%90%

Q

CLOCK

50%

50%

50%

tPHLtw

10%

MC74HC390A


CD

R

Q

Q

0 1 2 3 4 5 6 7 8 9


TIMING DIAGRAM(QA Connected to Clock B)

QA

QB

QC

QD

CLOCK A

RESET

QA

QB

QC

QD

CLOCK A

CLOCK B

RESET

3, 13

5, 11

6, 10

7, 9

1, 15

4, 12

2, 14

CD

R

Q

Q

CD

R

Q

Q

C

DR

Q

0 1 2 3 4 5 6

TEST CIRCUIT


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

Figure 3.

MC74HC390A


APPLICATIONS INFORMATION

Each half of the MC54/74HC390A has independent ÷ 2and ÷ 5 sections (except for the Reset function). The ÷ 2 and÷ 5 counters can be connected to give BCD or bi–quinary(2–5) count sequences. If Output QA is connected to theClock B input (Figure 4), a decade divider with BCD outputis obtained. The function table for the BCD count sequenceis given in Table 1.

To obtain a bi–quinary count sequence, the input signalsconnected to the Clock B input, and output QD is connectedto the Clock A input (Figure 5). QA provides a 50% dutycycle output. The bi–quinary count sequence function tableis given in Table 2.

Table 1. BCD Count Sequence*

Output

Count QD QC QB QA

0 L L L L1 L L L H2 L L H L3 L L H H4 L H L L5 L H L H6 L H H L7 L H H H8 H L L L9 H L L H

*QA connected to Clock B input.

Table 2. Bi–Quinary Count Sequence**

Output

Count QA QD QC QB

0 L L L L1 L L L H2 L L H L3 L L H H4 L H L L8 H L L L9 H L L H10 H L H L11 H L H H12 H H L L

** QD connected to Clock A input.

CONNECTION DIAGRAMS

1, 15 ÷ 2COUNTER

CLOCK A

RESET

Figure 4. BCD Count Figure 5. Bi-Quinary Count

÷ 2COUNTER

÷ 5COUNTER

÷ 5COUNTER

CLOCK B

CLOCK A

RESET

CLOCK B

1, 15 QA

QB

QCQD

3, 13

5, 11

6, 10

7, 9

4, 12

2, 14

QA

QB

QCQD

3, 13

5, 11

6, 10

7, 9

4, 12

2, 14



MC74HC393A/D



This device consists of two independent 4–bit binary ripple counterswith parallel outputs from each counter stage. A ÷ 256 counter can beobtained by cascading the two binary counters.

Internal flip–flops are triggered by high–to–low transitions of theclock input. Reset for the counters is asynchronous and active–high.State changes of the Q outputs do not occur simultaneously because ofinternal ripple delays. Therefore, decoded output signals are subject todecoding spikes and should not be used as clocks or as strobes exceptwhen gated with the Clock of the HC393A.








LOGIC DIAGRAM

Q1

Q2

Q3

Q4

CLOCK

RESET

1, 13

2, 12

3, 11

4, 10

5, 9

6, 8


BINARYCOUNTER

FUNCTION TABLE

Inputs

Clock Reset Outputs

X H LH L No ChangeL L No Change

L No ChangeL Advance to

Next State





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55 / Rail


MARKINGDIAGRAMS





HC393AALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

MC74HC393ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC393AAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

Q2b

Q1b

RESET b

CLOCK b

VCC

Q4b

Q3b

Q2a

Q1a

RESET a

CLOCK a

GND

Q3a

Q4a

MC74HC393A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.




ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise and Fall Time VCC = 2.0 VVCC = 3.0 V

(Figure 1) VCC = 4.5 VVCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

0000

ÎÎÎÎÎÎ

1000600500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.80


0.50.91.351.80


0.50.91.351.80


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ



MC74HC393A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ





– 55 to25C


VCCV





VOL






2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40


ÎÎÎÎÎÎÎÎ









µA











µA





ÎÎÎÎÎÎÎÎ




Symbol


Parameter



– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit





2.03.04.56.0


10153050


9142845


8122540


MHz


tPLH,tPHL


Maximum Propagation Delay, Clock to Q1(Figures 1 and 3)


2.03.04.56.0


70402420


80453026


90503631


ns


tPLH,tPHL




2.03.04.56.0


100563420

ÎÎÎÎÎÎÎÎÎ

105704538


1801005548

ÎÎÎÎÎÎÎÎÎ

ns


tPLH,tPHL




2.03.04.56.0


130804437


1501055547


1801307058


ns


tPLH,tPHL




2.03.04.56.0


1601105244


2501856555


3002108265


ns



Maximum Propagation Delay, Reset to any Q(Figures 2 and 3)


2.03.04.56.0


80483026


95653833


110755043


ns


tTLH,tTHL




2.03.04.56.0


75271513


95321916


110362219


ns




—ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎ

pF



CPD Power Dissipation Capacitance (Per Counter)* 35 pF


MC74HC393A





ÎÎÎÎÎÎÎÎ







– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit





2.03.04.56.0


2515109

ÎÎÎÎÎÎÎÎÎ

30201311


40301513

ÎÎÎÎÎÎÎÎÎ

ns





2.03.04.56.0


75271513


95321915


110362219


ns





2.03.04.56.0


75271513


95321915


110362219


ns





2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns


MC74HC393A


PIN DESCRIPTIONS

INPUTSClock (Pins 1, 13)

Clock input. The internal flip–flops are toggled and thecounter state advances on high–to–low transitions of theclock input.

CONTROL INPUTSReset (Pins 2, 12)

Active–high, asynchronous reset. A separate reset isprovided for each counter. A high at the Reset input preventscounting and forces all four outputs low.

OUTPUTSQ1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)

Parallel binary outputs Q4 is the most significant bit.

SWITCHING WAVEFORMS

tPHL

VCC

GND

VCC

GND

50%

50%

50%

trec

CLOCK

Q

RESET

Figure 1. Figure 2.


Q1

Q2

Q3

Q4

CLOCK

RESET

1, 13

2, 12

3, 11

4, 10

5, 9

6, 8



CL*

TESTPOINT

DEVICEUNDERTEST

OUTPUT

CLOCK

Q

90%90%50%

10%

tf trVCC

GND

tw1/fmax

tPLH tPHL

90%50%

10%

tTLH tTHL

C

D Q

tw

Q

C

D Q

Q

C

D Q

Q

C

D Q

Q

MC74HC393A


0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

CLOCK

RESET

Q1

Q2

Q3

Q4

TIMING DIAGRAM

COUNT SEQUENCE

Outputs

Count Q4 Q3 Q2 Q1

0 L L L L1 L L L H2 L L H L3 L L H H4 L H L L5 L H L H6 L H H L7 L H H H8 H L L L9 H L L H10 H L H L11 H L H H12 H H L L13 H H L H14 H H H L15 H H H H



MC74HC540A/D


The MC74HC540A is identical in pinout to the LS540. The deviceinputs are compatible with Standard CMOS outputs. External pullupresistors make them compatible with LSTTL outputs.

The HC540A is an octal inverting buffer/line driver/line receiverdesigned to be used with 3–state memory address drivers, clockdrivers, and other bus–oriented systems. This device features inputsand outputs on opposite sides of the package and two ANDedactive–low output enables.

The HC540A is similar in function to the HC541A, which hasnon–inverting outputs.








18Y1

2A1

17Y2

3A2

16Y3

4A3

15Y4

5A4

14Y5

6A5

13Y6

7A6

12Y7

8A7

11Y8

9A8

OE1OE2

1

19

OutputEnables

DataInputs

InvertingOutputs


LOGIC DIAGRAM


1920 18 17 16 15 14

21 3 4 5 6 7

VCC

13

8

12

9

11

10

OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND

L

L

H

X

L

L

X

H

L

H

X

X

FUNCTION TABLE

InputsOutput Y

OE1 OE2 A

H

L

Z

Z

Z = High ImpedanceX = Don’t Care

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MARKINGDIAGRAMS

1

20



HC540AAWLYYWW


1

20

MC74HC540ANAWLYYWW

1

20

120






MC74HC540A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA






mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ


Lead Temperature, 1 mm from Case for 10 SecondsPlastic DIP or SOIC Package


260ÎÎÎÎÎÎ

C







MinÎÎÎÎ

MaxÎÎÎÎÎÎ




2.0ÎÎÎÎ

6.0ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ




VCC = 6.0 V


000

ÎÎÎÎÎÎÎÎ

1000500400


ns


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V

Vin = VIL |Iout| ≤ 3.6mA|Iout| ≤ 6.0mA|Iout| ≤ 7.8mA

3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V

Vin = VIH |Iout| ≤ 3.6mA|Iout| ≤ 6.0mA|Iout| ≤ 7.8mA

3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40




MC74HC540A



Guaranteed LimitVCC

VSymbol Unit≤125°C≤85°C–55 to 25°CVCC

VConditionParameter


Output in High Impedance StateVin = VIL or VIHVout = VCC or GND

6.0 ±0.5 ±5.0 ±10.0 µA



6.0 4 40 160 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


2.03.04.56.0

80301815

100402320

120552825

ns

tPLZ,tPHZ


2.03.04.56.0

110452521

140603126

165753831

ns

tPZL,tPZH


2.03.04.56.0

110452521

140603126

165753831

ns

tTLH,tTHL


2.03.04.56.0

60221210

75281513

90341815

ns


Cout Maximum Three–State Output Capacitance (Output in HighImpedance State)

15 15 15 pF





Figure 1.

VCC

GND

INPUT A

OUTPUT Y

tPHL

OE1 or OE2 50%

VCC

GND

OUTPUT Y

tPZL

OUTPUT Y

tPZH

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

10%

90%

tPLZ

tPHZ

50%

50%tPLH

90%

50%

10%

tr

tTHL

tf

tTLH

Figure 2.

SWITCHING WAVEFORMS

90%

50%

10%

50%

MC74HC540A


CL*


TESTPOINT

DEVICEUNDERTEST

OUTPUT

TEST CIRCUITS

Figure 3. Figure 4.

CL*


TESTPOINT

DEVICEUNDERTEST

OUTPUT 1kΩ CONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ and tPZH.

PIN DESCRIPTIONS

INPUTSA1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,

9) — Data input pins. Data on these pins appear in invertedform on the corresponding Y outputs, when the outputs areenabled.

CONTROLSOE1, OE2 (PINS 1, 19) — Output enables (active–low).

When a low voltage is applied to both of these pins, the

outputs are enabled and the device functions as an inverter.When a hgih voltage is applied to either input, the outputsassume the high impedance state.

OUTPUTSY1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,

13, 12, 11) — Device outputs. Depending upon the state ofthe output enable pins, these outputs are either invertingoutputs or high–impedance outputs.

LOGIC DETAIL

One of EightInverters

INPUT A

OE1

OE2

OUTPUT Y

VCC

To 7 OtherInverters



MC74HC541A/D

! ! !High–Performance Silicon–Gate CMOS

The MC74HC541A is identical in pinout to the LS541. The deviceinputs are compatible with Standard CMOS outputs. External pullupresistors make them compatible with LSTTL outputs.

The HC541A is an octal non–inverting buffer/line driver/linereceiver designed to be used with 3–state memory address drivers,clock drivers, and other bus–oriented systems. This device featuresinputs and outputs on opposite sides of the package and two ANDedactive–low output enables.

The HC541A is similar in function to the HC540A, which hasinverting outputs.








18Y1

2A1

17Y2

3A2

16Y3

4A3

15Y4

5A4

14Y5

6A5

13Y6

7A6

12Y7

8A7

11Y8

9A8

OE1OE2

1

19

OutputEnables

DataInputs

Non–InvertingOutputs


LOGIC DIAGRAM


1920 18 17 16 15 14

21 3 4 5 6 7

VCC13

8

12

9

11

10

OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8


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MARKINGDIAGRAMS

1

20



HC541AAWLYYWW


1

20

MC74HC541ANAWLYYWW

1

20

120






L

L

H

X

L

L

X

H

L

H

X

X

FUNCTION TABLE

InputsOutput Y

OE1 OE2 A

L

H

Z

Z


MC74HC541A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA






mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ




260ÎÎÎÎÎÎ

C







MinÎÎÎÎ

MaxÎÎÎÎÎÎ




2.0ÎÎÎÎ

6.0ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ




VCC = 6.0 V


000

ÎÎÎÎÎÎÎÎ

1000500400


ns


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V

Vin = VIL |Iout| ≤ 3.6mA|Iout| ≤ 6.0mA|Iout| ≤ 7.8mA

3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V

Vin = VIH |Iout| ≤ 3.6mA|Iout| ≤ 6.0mA|Iout| ≤ 7.8mA

3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40




MC74HC541A



Guaranteed LimitVCC

VSymbol Unit≤125°C≤85°C–55 to 25°CVCC

VConditionParameter



6.0 ±0.5 ±5.0 ±10.0 µA



6.0 4 40 160 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


2.03.04.56.0

80301815

100402320

120552825

ns

tPLZ,tPHZ


2.03.04.56.0

110452521

140603126

165753831

ns

tPZL,tPZH


2.03.04.56.0

110452521

140603126

165753831

ns

tTLH,tTHL


2.03.04.56.0

60221210

75281513

90341815

ns


Cout Maximum Three–State Output Capacitance (Output in HighImpedance State)

15 15 15 pF





Figure 1.

VCC

GND

INPUT A

OUTPUT Y

tPLH

OE1 or OE2 50%

VCC

GND

OUTPUT Y

tPZL

OUTPUT Y

tPZH

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

10%

90%

tPLZ

tPHZ

50%

50%tPHL

90%

50%

10%

tr

tTLH

tf

tTHL

Figure 2.

SWITCHING WAVEFORMS

90%50%

10%

50%

MC74HC541A


CL*


TESTPOINT

DEVICEUNDERTEST

OUTPUT

TEST CIRCUITS

Figure 3. Figure 4.

CL*


TESTPOINT

DEVICEUNDERTEST


PIN DESCRIPTIONS


9) — Data input pins. Data on these pins appear innon–inverted form on the corresponding Y outputs, whenthe outputs are enabled.



outputs are enabled and the device functions as annon–inverting buffer. When a high voltage is applied toeither input, the outputs assume the high impedance state.


13, 12, 11) — Device outputs. Depending upon the state ofthe output enable pins, these outputs are eithernon–inverting outputs or high–impedance outputs.

VCC

To 7 OtherBuffers

LOGIC DETAIL

One of EightBuffers

INPUT A

OE1

OE2

OUTPUT Y



MC74HCT541A/D

& && "!!($&!'$! $($! ($ &" #& !#'&%High–Performance Silicon–Gate CMOS

The MC74HCT541A is identical in pinout to the LS541. Thisdevice may be used as a level converter for interfacing TTL or NMOSoutputs to high speed CMOS inputs.

The HCT541A is an octal non–inverting buffer/line driver/linereceiver designed to be used with 3–state memory address drivers,clock drivers, and other bus–oriented systems. This device featuresinputs and outputs on opposite sides of the package and two ANDedactive–low output enables.




• Operating Voltage Range: 4.5 to 5.5V




18Y1

2A1

17Y2

3A2

16Y3

4A3

15Y4

5A4

14Y5

6A5

13Y6

7A6

12Y7

8A7

11Y8

9A8

OE1OE2

1

19

OutputEnables

DataInputs

Non–InvertingOutputs


LOGIC DIAGRAM


1920 18 17 16 15 14

21 3 4 5 6 7

VCC

13

8

12

9

11

10

OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8


L

L

H

X

L

L

X

H

L

H

X

X

FUNCTION TABLE

InputsOutput Y

OE1 OE2 A

L

H

Z

Z


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MARKINGDIAGRAMS

1

20



HCT541AAWLYYWW


1

20

MC74HCT541ANAWLYYWW

1

20

120






MC74HCT541A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA






mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ




260ÎÎÎÎÎÎ

C







MinÎÎÎÎ

MaxÎÎÎÎÎÎ




4.5ÎÎÎÎ

5.5ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

CÎÎÎÎÎÎÎÎ


Input Rise/Fall Time (Figure 1)ÎÎÎÎÎÎ

0ÎÎÎÎ

500ÎÎÎÎÎÎ

ns


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



4.55.5

2.02.0

2.02.0

2.02.0

V



4.55.5

0.80.8

0.80.8

0.80.8

V



4.55.5

4.45.4

4.45.4

4.45.4

V

Vin = VIH or VIL |Iout| ≤ 6.0mA 4.5 3.98 3.84 3.70



4.55.5

0.10.1

0.10.1

0.10.1

V

Vin = VIH or VIL |Iout| ≤ 6.0mA 4.5 0.26 0.33 0.40




5.5 ±0.5 ±5.0 ±10.0 µA



5.5 4 40 160 µA

∆ICC Additional Quiescent SupplyCurrent

Vin = 2.4V, Any One InputVi VCC or GND Other Inputs

≥ –55°C 25 to 125°CCurrent Vin = VCC or GND, Other Inputs

Iout = 0µA 5.5 2.9 2.4 mA

1. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).2. Total Supply Current = ICC + Σ∆ICC.



MC74HCT541A


AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL


23 28 32 ns

tPLZ,tPHZ


30 34 38 ns

tPZL,tPZH


30 34 38 ns

tTLH,tTHL


12 15 18 ns


Cout Maximum Three–State Output Capacitance (Output in High ImpedanceState)

15 15 15 pF





Figure 1.

CL*


TESTPOINT

OE1 or OE2 1.3V

3.0V

GND

OUTPUT Y

tPZL

OUTPUT Y

tPZH

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

10%

90%

tPLZ

tPHZ

1.3V

1.3V

Figure 2.

SWITCHING WAVEFORMS

DEVICEUNDERTEST

OUTPUT

TEST CIRCUITS

Figure 3. Figure 4.

CL*


TESTPOINT

DEVICEUNDERTEST


3.0V

GND

INPUT A

OUTPUT Y

tPLH tPHL

90%

1.3V

10%

tr

tTLH

tf

tTHL

90%1.3V

10%

1.3V

MC74HCT541A


PIN DESCRIPTIONS


9) — Data input pins. Data on these pins appear innon–inverted form on the corresponding Y outputs, whenthe outputs are enabled.



outputs are enabled and the device functions as anon–inverting buffer. When a high voltage is applied toeither input, the outputs assume the high impedance state.


13, 12, 11) — Device outputs. Depending upon the state ofthe output enable pins, these outputs are eithernon–inverting outputs or high–impedance outputs.

LOGIC DETAIL

VCC

To 7 OtherBuffers

One of EightBuffers

INPUT A

OE1

OE2

OUTPUT Y



MC74HC573A/D


The MC74HC573A is identical in pinout to the LS573. The devicesare compatible with standard CMOS outputs; with pullup resistors,they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs changeasynchronously) when Latch Enable is high. When Latch Enable goeslow, data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HC373A but has the datainputs on the opposite side of the package from the outputs to facilitatePC board layout.







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MARKINGDIAGRAMS

1

20



HC573AAWLYYWW


1

20

MC74HC573ANAWLYYWW


1

20

1

20

120








HC573AALYW

1

20

MC74HC573A


LOGIC DIAGRAM

DATAINPUTS

D0

D1

D2

D3

D4

D5

D6

D7

LATCH ENABLE

OUTPUT ENABLE

11

1

9

8

7

6

5

4

3

2 19

18

17

16

15

14

13

12

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7


NONINVERTINGOUTPUTS

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUTENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

VCC

LATCHENABLE

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output







Units



54.5 ÎÎÎÎÎÎ

ea.



1.5 ÎÎÎÎÎÎ

ns



5.0ÎÎÎÎÎÎ




pJ


MC74HC573A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C





260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: –10 mW/C from 65 to 125CSOIC Package: –7 mW/C from 65 to 125C TSSOP Package: –6.1 mW/°C from 65 to 125C





Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ





Test Conditions ÎÎÎÎÎÎÎÎ

VCCV ÎÎÎÎÎÎÎÎ

– 55 to25C ÎÎÎ

ÎÎÎ 85CÎÎÎÎÎÎÎÎ

125CÎÎÎÎÎÎ







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8

ÎÎÎÎÎÎÎÎÎ

0.50.91.351 8


0.50.91.351.8

ÎÎÎÎÎÎÎÎÎ

V


VOH






2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V




Vin = VIH or VIL |Iout| ≤ 2.4mA|Iout| 6.0 mA|Iout| 7.8 mA


3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2

ÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).



MC74HC573A



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ





– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit



Maximum Low–Level OutputVoltage ÎÎÎÎÎÎÎÎÎ


Vout = 0.1 V or VCC – 0.1 V|Iout| 20 µA ÎÎÎÎ

ÎÎÎÎÎÎÎÎ

2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL |Iout| ≤ 2.4mA|Iout| 6.0 mA|Iout| 7.8 mA


3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4


ÎÎÎÎÎÎÎÎ









µA



Maximum Three–StateLeakage Current ÎÎÎÎÎÎÎÎÎ





– 0.5 ÎÎÎÎÎÎÎÎÎ

– 5.0ÎÎÎÎÎÎÎÎÎÎÎÎ

– 10 ÎÎÎÎÎÎÎÎÎ

µA

ÎÎÎÎÎÎÎÎ




Vin = VCC or GNDIIoutI = 0 µA

ÎÎÎÎÎÎÎÎ


4.0 ÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

160 ÎÎÎÎÎÎ

µA





ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎSymbol




– 55 to25C


125CÎÎÎÎÎÎ


tPLH,tPHL




2.03.04.56.0


1501003026


1901403833


2251804538


ns


tPLH,tPHL




2.03.04.56.0


1601053227


2001454034


2401904841


ns


tPLZ,tPHZ




2.03.04.56.0


1501003026


1901253833


2251504538


ns


tPZL,tPZH




2.03.04.56.0


1501003026


1901253833


2251504538


ns


tTLH,tTHL




2.03.04.56.0


60271210


75321513


90361815


ns


Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF


Cout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three–State Output Capacitance (Output in High–ImpedanceState)





pF





MC74HC573A




ÎÎÎÎÎÎÎÎ









ÎÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎParameter ÎÎÎFig. ÎÎÎVCCVoltsÎÎÎMin ÎÎÎMaxÎÎÎMin ÎÎÎMax ÎÎÎMin ÎÎÎMax ÎÎUnitÎÎÎÎ


tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input D to Latch EnableÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


5040109.0



65501311



75601513


ÎÎÎÎÎÎÎÎ

ns


thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Latch Enable to Input DÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


5.05.05.05.0



5.05.05.05.0



5.05.05.05.0


ÎÎÎÎÎÎÎÎ

ns



Minimum Pulse Width, Latch EnableÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


75601513



95801916



110902219


ÎÎÎÎÎÎÎÎ

ns


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall TimesÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0



1000800500400



1000800500400



1000800500400

ÎÎÎÎÎÎÎÎ

ns

MC74HC573A


SWITCHING WAVEFORMS

VCC

GND

tftr

INPUT D

Q

10%50%90%

10%50%90%

tTLH

tPLH tPHL

tTHL

OUTPUTENABLE

Q

Q

50%

50%

1.3 V90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

Figure 1. Figure 2.

Figure 3. Figure 4.

VCC

GND

50%

50%LATCH

ENABLE

tPLH tPHL

Q

tw




DLE

QD0

219

Q0

DLE

QD1

318

Q1

DLE

QD2

417

Q2

DLE

QD3

516

Q3

D

LEQ

D46

15Q4

DLE

QD5

714

Q5

D

LEQ

D68

13Q6

D

LEQ

D79

12Q7

LATCH ENABLE

OUTPUT ENABLE

11

1

VCC

GND

VCC

GND50%

50%

VALID

tSU th

INPUT D

LATCHENABLE



MC74HCT573A/D

! " High–Performance Silicon–Gate CMOS

The MC74HCT573A is identical in pinout to the LS573. Thisdevice may be used as a level converter for interfacing TTL or NMOSoutputs to High–Speed CMOS inputs.

These latches appear transparent to data (i.e., the outputs changeasynchronously) when Latch Enable is high. When Latch Enable goeslow, data meeting the setup and hold times becomes latched.

The Output Enable input does not affect the state of the latches, butwhen Output Enable is high, all device outputs are forced to thehigh–impedance state. Thus, data may be latched even when theoutputs are not enabled.

The HCT573A is identical in function to the HCT373A but has theData Inputs on the opposite side of the package from the outputs tofacilitate PC board layout.







• Chip Complexity: 234 FETs or 58.5 Equivalent Gates— Improved Propagation Delays— 50% Lower Quiescent Power

http://onsemi.com

MARKINGDIAGRAMS

1

20



HCT573AAWLYYWW


1

20

MC74HCT573ANAWLYYWW


1

20

1

20

120








HCT573AALYW

1

20

MC74HCT573A


LOGIC DIAGRAM

DATAINPUTS

D0

D1

D2

D3

D4

D5

D6

D7

LATCH ENABLE

OUTPUT ENABLE

11

1

9

8

7

6

5

4

3

2 19

18

17

16

15

14

13

12

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7


NONINVERTINGOUTPUTS

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUTENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

VCC

LATCHENABLE

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output




ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria

ÎÎÎÎÎÎÎÎValue

ÎÎÎÎÎÎUnitsÎÎÎÎÎÎÎÎÎÎ


Internal Gate Count*ÎÎÎÎÎÎÎÎÎÎÎÎ


ea



1.5 ÎÎÎÎÎÎ

ns



5.0 ÎÎÎÎÎÎ

µW



0.0075 ÎÎÎÎÎÎ

pJ


MC74HCT573A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: –10 mW/C from 65 to 125CSOIC Package: –7 mW/C from 65 to 125C TSSOP Package: –6.1 mW/°C from 65 to 125C





MinÎÎÎÎ

MaxÎÎÎÎÎÎ




4.5 ÎÎÎÎ

5.5ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

CÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

500ÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV

ÎÎÎÎÎÎÎÎÎ

– 55 to25C


85C


125C

ÎÎÎÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

4.55.5ÎÎÎÎÎÎ



2.02.0ÎÎÎÎÎÎ

V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





4.55.5

ÎÎÎÎÎÎÎÎÎ

0.80.8


0.80.8


0.80.8

ÎÎÎÎÎÎÎÎÎ

V


VOHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ









V

ÎÎÎÎÎÎÎÎ



Vin = VIH or VIL|Iout| 6.0 mA ÎÎÎÎ

ÎÎÎÎ4.5 ÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





4.55.5

ÎÎÎÎÎÎÎÎÎ

0.10.1


0.10.1


0.10.1

ÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

4.5ÎÎÎÎÎÎ




ÎÎÎÎIinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage CurrentÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin = VCC or GNDÎÎÎÎÎÎÎÎ

5.5ÎÎÎÎÎÎ



± 1.0ÎÎÎÎÎÎ

µAÎÎÎÎÎÎÎÎÎÎÎÎ

IOZÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ









µA





Vin = VCC or GNDIout 0 µA






µA

ÎÎÎÎÎÎÎÎ

∆ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

≥ – 55CÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

25C to 125C ÎÎÎÎÎÎÎÎÎÎ



Vin = VCC or GND, Other In utslout = 0 µA ÎÎÎÎ

ÎÎÎÎ5.5 ÎÎÎÎÎÎ

2.9ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.4 ÎÎÎÎÎÎ

mA




MC74HCT573A













Unit



Maximum Propagation Delay, Input D to Output Q(Figures 1 and 5)

ÎÎÎÎÎÎÎÎ

30 ÎÎÎÎÎÎÎÎ

38 ÎÎÎÎÎÎÎÎ

45 ÎÎÎÎÎÎ

ns


tPLHtPHL







ns


TPLZ,TPHZ







ns


tTZL,tTZHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

28 ÎÎÎÎÎÎÎÎ

35 ÎÎÎÎÎÎÎÎ

42 ÎÎÎÎÎÎ

ns


tTLH,tTHL


Maximum Output Transition Time, any Output(Figures 1 and 5)





ns




10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF


Cout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






pF







ÎÎÎÎÎÎÎÎ






– 55 to 25C ÎÎÎÎÎÎÎÎÎÎ

85C ÎÎÎÎÎÎÎÎ 125CÎÎÎ




Fig. ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input D to Latch Enable ÎÎÎÎÎÎ

4 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ

th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Latch Enable to Input D ÎÎÎÎÎÎ

4 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ


Minimum Pulse Width, Latch Enable ÎÎÎÎÎÎ

2 ÎÎÎÎÎÎ




ns

ÎÎÎÎÎÎÎÎ






500ÎÎÎÎÎÎ

ns

MC74HCT573A


SWITCHING WAVEFORMS

3.0 V

GND

tftr

INPUT D

Q

0.3 V1.3 V2.7 V

10%1.3 V

90%

tTLH

tPLH tPHL

tTHL

OUTPUTENABLE

Q

Q

1.3 V

1.3 V

1.3 V90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

Figure 1. Figure 2.

Figure 3. Figure 4.

3.0 V

GND

1.3 V

1.3 VLATCH

ENABLE

tPLH tPHL

Q

tw




DLE

QD0

219

Q0

DLE

QD1

318

Q1

DLE

QD2

417

Q2

DLE

QD3

516

Q3

D

LEQ

D46

15Q4

DLE

QD5

714

Q5

D

LEQ

D68

13Q6

D

LEQ

D79

12Q7

LATCH ENABLE

OUTPUT ENABLE

11

1

3.0 V

GND

3.0 V

GND1.3 V

1.3 V

VALID

tSU th

INPUT D

LATCHENABLE



MC74HC574A/D



Data meeting the setup time is clocked to the outputs with the risingedge of the Clock. The Output Enable input does not affect the statesof the flip–flops, but when Output Enable is high, all device outputsare forced to the high–impedance state. Thus, data may be stored evenwhen the outputs are not enabled.

The HC574A is identical in function to the HC374A but has theflip–flop inputs on the opposite side of the package from the outputs tofacilitate PC board layout.







http://onsemi.com

MARKINGDIAGRAMS

1

20



HC574AAWLYYWW


1

20

MC74HC574ANAWLYYWW

1

20

120






MC74HC574A


LOGIC DIAGRAM

DATAINPUTS

D02 19

Q0

D1

D2

D3

D4

D5

D6

D7

CLOCK

OUTPUT ENABLE

3

4

5

6

7

8

9

11

1

18

17

16

15

14

13

12

Q1

Q2

Q3

Q4

Q5

Q6

Q7

NON–INVERTINGOUTPUTS


PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUTENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

VCC

CLOCK

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output

OE Clock D Q






UnitsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count*


66.5

ÎÎÎÎÎÎÎÎÎ

ea



1.5 ÎÎÎÎÎÎ

ns



5.0 ÎÎÎÎÎÎ




pJ


MC74HC574A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ




750500ÎÎÎÎÎÎ

mW





ÎÎÎÎÎÎÎÎ




260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: –10 mW/C from 65 to 125CSOIC Package: –7 mW/C from 65 to 125C



ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2








2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4


ÎÎÎÎÎÎÎÎ









µA



MC74HC574A



ÎÎÎÎÎÎ






ÎÎÎUnit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV





IOZÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





6.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


± 5.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

± 10ÎÎÎÎÎÎÎÎÎÎÎÎ

µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


4.0 ÎÎÎÎÎÎ

40 ÎÎÎÎÎÎÎÎ

160 ÎÎÎÎÎÎ

µA



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ






VCCV ÎÎÎÎÎÎÎÎ

– 55 to25C


125CÎÎÎÎÎÎ











µA











µA




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎSymbol




– 55 to25C


125CÎÎÎÎÎÎ





2.03.04.56.0


6.0153035


4.8102428


4.08.02024


MHz


tPLH,tPHL




2.03.04.56.0


1601053227


2001454034


2401904841


ns


tPLZ,tPHZ




2.03.04.56.0


1501003026


1901253833


2251504538


ns


tPZL,tPZH




2.03.04.56 0


140902824


1751203530


2101404236


ns


tTLH,tTHL


Maximum Output Transition Time, any Output(Figures 1 and 4)


2.03.04.56.0


60271210


75321513


90361815


ns


Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF


Cout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three–State Output Capacitance, Output in High–ImpedanceState





pF





MC74HC574A




ÎÎÎÎÎÎÎÎ









ÎÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎParameter ÎÎÎFig.ÎÎÎVCCVoltsÎÎÎMin ÎÎÎMaxÎÎÎMin ÎÎÎMax ÎÎÎMin ÎÎÎMax ÎÎUnitÎÎÎÎ


tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to ClockÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.66.0


5040109.0



65501311



75601513


ÎÎÎÎÎÎÎÎ

ns


thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to DataÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


5.05.05.05.0



5.05.05.05.0



5.05.05.05.0


ÎÎÎÎÎÎÎÎ

ns



Minimum Pulse Width, ClockÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0


75601513



95801916



110902219


ÎÎÎÎÎÎÎÎ

ns


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall TimesÎÎÎÎÎÎÎÎÎÎÎÎ


2.03.04.56.0



1000800500400



1000800500400



1000800500400

ÎÎÎÎÎÎÎÎ

ns

MC74HC574A


SWITCHING WAVEFORMS

Figure 1. Figure 2.

CLOCK

Q

tr tfVCC

GND

90%50%

10%

90%50%

10%

tPLH tPHL

tTLH tTHL

tw

1/fmaxQ

Q

1.3 V

1.3 V

90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

Figure 3.

Figure 4.



50%CLOCK

VCC

VALID

GND

VCC

GND

tsu th

50%DATA


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

C

DQ2

D019

Q0

C

DQ3

D118

Q1

CD

Q4D2

17Q2

CD

Q5D3

16Q3

CD

Q6D4

15Q4

CD

Q7D5

14Q5

CD

Q8D6

13Q6

C

DQ9

D712

Q7

11CLOCK

1OUTPUT ENABLE



MC74HCT574A/D

! !! #! $! ! "! High–Performance Silicon–Gate CMOS

The MC74HCT574A is identical in pinout to the LS574. Thisdevice may be used as a level converter for interfacing TTL or NMOSoutputs to High Speed CMOS inputs.

Data meeting the setup time is clocked to the outputs with the risingedge of the Clock. The Output Enable input does not affect the statesof the flip–flops, but when Output Enable is high, all device outputsare forced to the high–impedance state. Thus, data may be stored evenwhen the outputs are not enabled.

The HCT574A is identical in function to the HCT374A but has theflip–flop inputs on the opposite side of the package from the outputs tofacilitate PC board layout.








http://onsemi.com

MARKINGDIAGRAMS

1

20



HCT574AAWLYYWW


1

20

MC74HCT574ANAWLYYWW

1

20

120






MC74HCT574A


LOGIC DIAGRAM

DATAINPUTS

D02 19

Q0

D1

D2

D3

D4

D5

D6

D7

CLOCK

OUTPUT ENABLE

3

4

5

6

7

8

9

11

1

18

17

16

15

14

13

12

Q1

Q2

Q3

Q4

Q5

Q6

Q7

NON–INVERTINGOUTPUTS


PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUTENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

VCC

CLOCK

Q7

Q6

Q5

Q4

FUNCTION TABLE

Inputs Output

OE Clock D Q




Design Criteria


Value

ÎÎÎÎÎÎÎÎÎ

Units



71.5 ÎÎÎÎÎÎ

ea



1.5 ÎÎÎÎÎÎ

nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power DissipationÎÎÎÎÎÎÎÎÎÎÎÎ



Speed Power Product


0.0075

ÎÎÎÎÎÎÎÎÎ

pJ


MC74HCT574A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA






mW

ÎÎÎÎÎÎÎÎ




C

ÎÎÎÎÎÎÎÎ




260ÎÎÎÎÎÎ

C


†Derating — Plastic DIP: –10 mW/C from 65 to 125CSOIC Package: –7 mW/C from 65 to 125C





MinÎÎÎÎ

MaxÎÎÎÎÎÎ




4.5ÎÎÎÎ

5.5ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

CÎÎÎÎÎÎÎÎ


Input Rise and Fall Time (Figure 1)ÎÎÎÎÎÎ

0ÎÎÎÎ

500ÎÎÎÎÎÎ

ns


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ





– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ


2.02.0ÎÎÎÎÎÎ

V







4.55.5


0.80.8

ÎÎÎÎÎÎÎÎÎ

0.80.8


0.80.8

ÎÎÎÎÎÎÎÎÎ

V










4.45.4ÎÎÎÎÎÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ

4.5ÎÎÎÎÎÎÎÎ

3.98ÎÎÎÎÎÎ


3.7ÎÎÎÎÎÎ

V







4.55.5


0.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.1


0.10.1


ÎÎÎÎÎÎÎÎ





4.5


0.26

ÎÎÎÎÎÎÎÎÎ

0.33


0.4







± 0.1 ÎÎÎÎÎÎ


± 1.0ÎÎÎÎÎÎ

µA







5.5


4.0

ÎÎÎÎÎÎÎÎÎ

40


160

ÎÎÎÎÎÎÎÎÎ

µA

1. Output in high–impedance state.NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).



MC74HCT574A



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ





– 55 to25C

ÎÎÎÎÎÎÎÎÎ



Unit



Maximum Three–StateLeakageCurrent


Vin = VIL or VIH (Note 1)Vout = VCC or GND ÎÎÎÎ

ÎÎÎÎÎÎÎÎ




– 10 ÎÎÎÎÎÎÎÎÎ

µA

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ


≥ – 55CÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ








mA

1. Output in high–impedance state.












UnitÎÎÎÎÎÎÎÎÎÎfMAX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)

ÎÎÎÎÎÎÎÎ30

ÎÎÎÎÎÎÎÎ24

ÎÎÎÎÎÎÎÎ20

ÎÎÎÎÎÎMHzÎÎÎÎÎ


tPLH,tPHL







ns


tPLZ,tPHZ







ns


tPZH,tPZLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay Time, Output Enable to Q(Figures 2 and 5)

ÎÎÎÎÎÎÎÎ

28 ÎÎÎÎÎÎÎÎ

35 ÎÎÎÎÎÎÎÎ

42 ÎÎÎÎÎÎ

ns


tTLH,

tTHL


Maximum Output Transition Time, Any Output(Figures 1, 2 and 4)





ns




10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF





ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit

ÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ– 55 to 25C

ÎÎÎÎÎÎÎÎÎÎ 85C


ÎÎÎÎÎÎÎÎ

ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎFig.ÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

MaxÎÎÎÎUnitÎÎÎÎ

ÎÎÎÎtsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to ClockÎÎÎÎÎÎ

3ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ

thÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to DataÎÎÎÎÎÎ

3ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ


Minimum Pulse Width, Clock ÎÎÎÎÎÎ

1 ÎÎÎÎÎÎ




nsÎÎÎÎÎÎÎÎ

tr, IfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ





500 ÎÎÎÎ

ns

MC74HCT574A



CLOCK

ENABLEOUTPUT

11

1

D02

C

19

D

Q

Q0

D13

C

18

D

Q

Q1

D24

C

17

D

Q

Q2

D35

C

16

D

Q

Q3

D46

C

15

D

Q

Q4

D57

C

14

D

Q

Q5

D68

C

13

D

Q

Q6

D79

C

12

D

Q

Q7

SWITCHING WAVEFORMS

Figure 1. Figure 2.

CLOCK

Q

tr tf3.0 V

GND

2.7 V1.3 V

0.3 V

90%1.3 V

10%

tPLH tPHL

tTLH tTHL

tw

1/fmaxQ

Q

1.3 V

1.3 V

90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

OUTPUTENABLE

1.3 V



1.3 V

CLOCK

3.0 VVALID

GND

3.0 V

GND

tsu th

1.3 VDATA


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ



MC74HC589A/D

! ! ! " ! ! High–Performance Silicon–Gate CMOS

The MC74HC589A device consists of an 8–bit storage latch whichfeeds parallel data to an 8–bit shift register. Data can also be loadedserially (see Function Table). The shift register output, QH, is athree–state output, allowing this device to be used in bus–orientedsystems.

The HC589A directly interfaces with the SPI serial data port onCMOS MPUs and MCUs.








LOGIC DIAGRAMSERIALDATAINPUT

14

15

1

2

3

4

5

6

7

12

11

13

10

SA

A

B

C

D

E

F

G

H

LATCH CLOCK

SHIFT CLOCK


OUTPUT ENABLE

PARALLELDATA

INPUTS DATALATCH

SHIFTREGISTER


9QH

SERIALDATA

OUTPUT

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC589ANAWLYYWW

1

16

HC589AAWLYWW


HC589AALYW

1

16








PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

LATCH CLOCK


SA

A

VCC

QH

OUTPUT ENABLE

SHIFT CLOCK

E

D

C

B

GND

H

G

F

MC74HC589A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C






C


†Derating — Plastic DIP: –10 mW/C from 65 to 125CSOIC Package: –7 mW/C from 65 to 125CTSSOP Package: – 6.1 mW/C from 65 to 125C



ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise and Fall Time VCC = 2.0 VVCC = 3.0 V



000

ÎÎÎÎÎÎÎÎ

1000TBD500400


ns


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTest Conditions

ÎÎÎÎÎÎÎÎ


– 55 to25C


ÎÎÎÎÎÎUnitÎÎÎÎ







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V







2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20


ÎÎÎÎÎÎÎÎ






2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


0.260.260.26


0.330.330.33


0.400.400.40


ÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input LeakageCurrent ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ



± 0.1 ÎÎÎÎÎÎ


± 1.0ÎÎÎÎÎÎ

µA



MC74HC589A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV














µA








4ÎÎÎÎÎÎÎÎÎ



µA


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)ÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


fmax ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



2.03.04.56.0


6.0TBD3035

ÎÎÎÎÎÎÎÎÎ

4.8TBD2428


4.0TBD2024

ÎÎÎÎÎÎÎÎÎ

MHz


tPLH,tPHL


Maximum Propagation Delay, Latch Clock to QH(Figures 1 and 8)


2.03.04.56.0


1751004030


2251105040


2751256050


ns


tPLH,tPHL


Maximum Propagation Delay, Shift Clock to QH(Figures 2 and 8)


2.03.04.56.0


160903025


2001304030


2401604840


ns


tPLH,tPHL


Maximum Propagation Delay, Serial Shift/Parallel Load to QH(Figures 4 and 8)


2.03.04.56.0


160903025

ÎÎÎÎÎÎÎÎÎ

2001304030


2401604840

ÎÎÎÎÎÎÎÎÎ

ns


tPLZ,tPHZ


Maximum Propagation Delay, Output Enable to QH(Figures 3 and 9)


2.03.04.56.0


150802723


1701003025


2001304030


ns


tPZL,tPZH


Maximum Propagation Delay, Output Enable to QH(Figures 3 and 9)


2.03.04.56.0


150802723


1701003025


2001304030


ns


tTLH,tTHL




2.03.04.56.0


60TBD1210


75TBD1513


90TBD1815


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF



Maximum Three–State Output Capacitance (Output inHigh–Impedance State) ÎÎÎÎ

ÎÎÎÎ


15 ÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎ

pF





MC74HC589A





ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


– 55 to25C




tsuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, A–H to Latch Clock(Figure 5)


2.03.04.56.0


100TBD2017


125TBD2521


150TBD3026


ns


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Serial Data Input SA to Shift Clock(Figure 6)


2.03.04.56.0


100TBD2017


125TBD2521


150TBD3026


ns



Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock(Figure 7)


2.03.04.56.0


100TBD2017

ÎÎÎÎÎÎÎÎÎ

125TBD2521


150TBD3026

ÎÎÎÎÎÎÎÎÎ

ns



Minimum Hold Time, Latch Clock to A–H(Figure 5)


2.03.04.56.0


25TBD

55


30TBD

66


40TBD

87


ns



Minimum Hold Time, Shift Clock to Serial Data Input SA(Figure 6)


2.03.04.56.0


5555


5555


5555


ns



Minimum Pulse Width, Shift Clock(Figure 2)


2.03.04.56.0


75TBD1513

ÎÎÎÎÎÎÎÎÎ

95TBD1916


110TBD2319

ÎÎÎÎÎÎÎÎÎ

ns



Minimum Pulse Width, Latch Clock(Figure 1)


2.03.04.56.0


80TBD1614


100TBD2017


120TBD2420


ns



Minimum Pulse Width, Serial Shift/Parallel Load(Figure 4)


2.03.04.56.0


80TBD1614


100TBD2017


120TBD2420


ns





2.03.04.56.0


1000TBD500400


1000TBD500400


1000TBD500400


ns


MC74HC589A


FUNCTION TABLE

Inputs Resulting Function

OperationOutputEnable

Serial Shift/Parallel Load

LatchClock

ShiftClock

SerialInputSA

ParallelInputsA–H

DataLatch

Contents

ShiftRegisterContents

OutputQH

Force output into highimpedance state

H X X X X X X X Z

Load parallel data intodata latch

L H L, H, X a–h a–h U U

Transfer latch contents toshift register

L L L, H, X X X U LRN SRN LRH

Contents of input latchand shift register areunchanged

L H L, H, L, H, X X U U U

Load parallel data intodata latch and shiftregister

L L X X a–h a–h a–h h

Shift serial data into shiftregister

L H X D X * SRA = D,SRN SRN+1

SRG SRH

Load parallel data in datalatch and shift serial datainto shift register

L H D a–h a–h SRA = D,SRN SRN+1

SRG SRH

LR = latch register contents U = remains unchangedSR = shift register contents X = don’t carea–h = data at parallel data inputs A–H Z = high impedanceD = data (L, H) at serial data input SA * = depends on Latch Clock input

MC74HC589A


SWITCHING WAVEFORMS

Figure 1. (Serial Shift/Parallel Load = L) Figure 2. (Serial Shift/Parallel Load = H)

LATCH CLOCK

QH

tr tfVCC

GND

90%50%

10%

tPLH tPHL

tTLH tTHL

twSHIFT CLOCK

QH

VCC

GND50%

50%

tPLH tPHL

1/fmax

90%50%10%

tw

Figure 3.

QH

QH

50%

50%

90%

10%

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

OUTPUTENABLE

50%


QH

50%

tPLH

50%

VCC

GNDtPHL

50%

tw

Figure 4.

A–H 50%

50%LATCH CLOCK

VCC

GND


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

DATA VALID

tsu th

SA 50%

50%SHIFT CLOCK

VCC

GND

DATA VALID

tsu th


50%

50%SHIFT CLOCK

VCC

GNDtsu

Figure 5. Figure 6.


MC74HC589A


TEST CIRCUIT

Figure 9.


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

PIN DESCRIPTIONS

DATA INPUTSA, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Parallel data inputs. Data on these inputs are stored in thedata latch on the rising edge of the Latch Clock input.

SA (Pin 14)

Serial data input. Data on this input is shifted into the shiftregister on the rising edge of the Shift Clock input if SerialShift/Parallel Load is high. Data on this input is ignoredwhen Serial Shift/Parallel Load is low.

CONTROL INPUTSSerial Shift/Parallel Load (Pin 13)

Shift register mode control. When a high level is appliedto this pin, the shift register is allowed to serially shift data.When a low level is applied to this pin, the shift registeraccepts parallel data from the data latch.

Shift Clock (Pin 11)

Serial shift clock. A low–to–high transition on this inputshifts data on the serial data input into the shift register and

data in stage H is shifted out QH, being replaced by the datapreviously stored in stage G.

Latch Clock (Pin 12)

Data latch clock. A low–to–high transition on this inputloads the parallel data on inputs A–H into the data latch.


Active–low output enable A high level applied to this pinforces the QH output into the high impedance state. A lowlevel enables the output. This control does not affect the stateof the input latch or the shift register.

OUTPUTQH (Pin 9)

Serial data output. This pin is the output from the last stageof the shift register. This is a 3–state output.

MC74HC589A


ÉÉÉÉÉÉÉÉÉÉ

TIMING DIAGRAM

SHIFT CLOCK

SERIAL DATAINPUT, SA

OUTPUT ENABLE


LATCH CLOCK

A

B

C

D

E

F

G

H

QH

PARALLELDATA

INPUTS

SERIAL SHIFT SERIAL SHIFT SERIAL SHIFT SERIALSHIFT

RESET LATCHAND SHIFT REGISTER

LOAD LATCH PARALLEL LOADSHIFT REGISTER

LOAD LATCH PARALLEL LOADSHIFT REGISTER

PARALLEL LOAD, LATCHAND SHIFT REGISTER

HIGH IMPEDANCE H L H H HL L H L H L L L H L H H

L

L

L

L

L

L

L

L

H

L

H

L

H

H

L

H

L

L

L

L

L

L

L

H

L

L

L

L

H

H

L

H

MC74HC589A


PARALLELDATA

INPUTS

10

14

11

13

12

15

1

2

3

4

5

6

7

OUTPUT ENABLE

SA

SHIFT CLOCK


LATCH CLOCK

A

B

C

D

E

F

G

H

STAGE A

STAGE B

STAGE C*

STAGE D*

STAGE E*

STAGE F*

STAGE G*

STAGE HVCC

9QH

DC

Q

DC

Q

DC Q

S

R

DC Q

S

R

DC

Q

DC Q

S

R

*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

LOGIC DETAIL



MC74HC595A/D

# ! $#! !!$# $# #"#! %# ### $# $#"High–Performance Silicon–Gate CMOS

The MC74HC595A consists of an 8–bit shift register and an 8–bitD–type latch with three–state parallel outputs. The shift registeraccepts serial data and provides a serial output. The shift register alsoprovides parallel data to the 8–bit latch. The shift register and latchhave independent clock inputs. This device also has an asynchronousreset for the shift register.

The HC595A directly interfaces with the SPI serial data port onCMOS MPUs and MCUs.








• Improvements over HC595— Improved Propagation Delays— 50% Lower Quiescent Power— Improved Input Noise and Latchup Immunity

LOGIC DIAGRAMSERIALDATAINPUT

14

11

10

12

13

SHIFTCLOCK

RESET

LATCHCLOCK

OUTPUTENABLE

SHIFTREGISTER

LATCH

15

1

2

3

4

5

6

7

9

QAQB

QCQDQEQFQGQH

SQH

A


PARALLELDATA

OUTPUTS

SERIALDATA

OUTPUT

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC595ANAWLYYWW

1

16

HC595AAWLYWW


HC595AALYW

1

16








PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

LATCH CLOCK

OUTPUT ENABLE

A

QA

VCC

SQH

RESET

SHIFT CLOCK

QE

QD

QC

QB

GND

QH

QG

QF

MC74HC595A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 35 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 75 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C





260

ÎÎÎÎÎÎÎÎÎ

C







Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V




ÎÎÎÎÎÎÎÎÎ

0 ÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns




ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit







2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V







2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V



Minimum High–Level OutputVoltage, QA – QH




2.04.56.0


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

1.94.45.9


1.94.45.9

ÎÎÎÎÎÎÎÎÎ

V






3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2




Maximum Low–Level OutputVoltage, QA – QH




2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V






3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4

ÎÎÎÎÎÎÎÎÎ



MC74HC595A



ÎÎÎÎÎÎ

Unit



V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV






Minimum High–Level OutputVoltage, SQH


Vin = VIH or VILIIoutI 20 µA


2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V




Vin = VIH or VIL |Iout| 2.4 mAIIoutI 4.0 mA

IIoutI 5.2 mA


3.04.56.0


2.983.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.23.75.2


ÎÎÎÎÎÎÎÎ


Maximum Low–Level OutputVoltage, SQH


Vin = VIH or VILIIoutI 20 µA


2.04.56.0


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

0.10.10.1


0.10.10.1

ÎÎÎÎÎÎÎÎÎ

V




Vin = VIH or VIL |Iout| 2.4 mAIIoutI 4.0 mA

IIoutI 5.2 mA


3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.40.40.4


ÎÎÎÎÎÎÎÎ









µA



Maximum Three–StateLeakageCurrent, QA – QH








µA





Vin = VCC or GNDlout = 0 µA






µA





ÎÎÎÎÎÎÎÎ




ÎÎÎÎÎÎÎÎ


– 55 to25C







2.03.04.56.0


6.0153035


4.8102428


4.08.02024


MHz


tPLH,tPHL


Maximum Propagation Delay, Shift Clock to SQH(Figures 1 and 7)


2.03.04.56.0


1401002824


1751253530


2101504236


ns


tPHL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to SQH(Figures 2 and 7)


2.03.04.56.0


1451002925


1801253631


2201504438


ns


tPLH,tPHL


Maximum Propagation Delay, Latch Clock to QA – QH(Figures 3 and 7)


2.03.04.56.0


1401002824

ÎÎÎÎÎÎÎÎÎ

1751253530


2101504236

ÎÎÎÎÎÎÎÎÎ

ns


tPLZ,tPHZ


Maximum Propagation Delay, Output Enable to QA – QH(Figures 4 and 8)


2.03.04.56.0


1501003026


1901253833


2251504538


ns


tPZL,tPZH


Maximum Propagation Delay, Output Enable to QA – QH(Figures 4 and 8)


2.03.04.56.0


135902723


1701103429


2051304135


ns


tTLH,tTHL


Maximum Output Transition Time, QA – QH(Figures 3 and 7)


2.03.04.56.0


60231210


75271513


90311815


ns

MC74HC595A



ÎÎÎÎÎÎ

Unit



V


Parameter


SymbolÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

– 55 to25C

ÎÎÎÎÎÎÎÎ

VCCV


ParameterÎÎÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tTLH,tTHL


Maximum Output Transition Time, SQH(Figures 1 and 7)


2.03.04.56.0


75271513


95321916


110362219


ns





10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF



Maximum Three–State Output Capacitance (Output inHigh–Impedance State), QA – QH

ÎÎÎÎÎÎÎÎ


15 ÎÎÎÎÎÎ

15 ÎÎÎÎÎÎÎÎ

15 ÎÎÎÎÎÎ

pF





TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)



ÎÎÎÎÎÎÎÎ




Symbol


Parameter


VCCV


25C to– 55C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


tsu ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Serial Data Input A to Shift Clock(Figure 5)


2.03.04.56.0


5040109.0


65501311


75601513


ns



Minimum Setup Time, Shift Clock to Latch Clock(Figure 6)


2.03.04.56.0


75601513

ÎÎÎÎÎÎÎÎÎ

95701916


110802219

ÎÎÎÎÎÎÎÎÎ

ns



Minimum Hold Time, Shift Clock to Serial Data Input A(Figure 5)


2.03.04.56.0


5.05.05.05.0


5.05.05.05.0


5.05.05.05.0


ns



Minimum Recovery Time, Reset Inactive to Shift Clock(Figure 2)


2.03.04.56.0


5040109.0


65501311


75601513


ns





2.03.04.56.0


60451210


75601513


90701815


ns



Minimum Pulse Width, Shift Clock(Figure 1)


2.03.04.56.0


5040109.0


65501311


75601513


ns



Minimum Pulse Width, Latch Clock(Figure 6)


2.03.04.56.0


5040109.0


65501311


75601513


ns





2.03.04.56.0


1000800500400


1000800500400


1000800500400


ns

MC74HC595A


FUNCTION TABLE

Inputs Resulting Function

Operation Reset

SerialInput

AShiftClock

LatchClock

OutputEnable

ShiftRegisterContents

LatchRegisterContents

SerialOutputSQH

ParallelOutputsQA – QH

Reset shift register L X X L, H, ↓ L L U L U

Shift data into shiftregister

H D ↑ L, H, ↓ L D SRA;SRN SRN+1

U SRG SRH U

Shift register remainsunchanged

H X L, H, ↓ L, H, ↓ L U U U U

Transfer shift registercontents to latchregister

H X L, H, ↓ ↑ L U SRN LRN U SRN

Latch register remainsunchanged

X X X L, H, ↓ L * U * U

Enable parallel outputs X X X X L * ** * Enabled

Force outputs into highimpedance state

X X X X H * ** * Z

SR = shift register contents D = data (L, H) logic level ↑ = Low–to–High * = depends on Reset and Shift Clock inputsLR = latch register contents U = remains unchanged ↓ = High–to–Low ** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTSA (Pin 14)

Serial Data Input. The data on this pin is shifted into the8–bit serial shift register.

CONTROL INPUTSShift Clock (Pin 11)

Shift Register Clock Input. A low– to–high transition onthis input causes the data at the Serial Input pin to be shiftedinto the 8–bit shift register.

Reset (Pin 10)

Active–low, Asynchronous, Shift Register Reset Input. Alow on this pin resets the shift register portion of this deviceonly. The 8–bit latch is not affected.

Latch Clock (Pin 12)

Storage Latch Clock Input. A low–to–high transition onthis input latches the shift register data.


Active–low Output Enable. A low on this input allows thedata from the latches to be presented at the outputs. A highon this input forces the outputs (QA–QH) into thehigh–impedance state. The serial output is not affected bythis control unit.

OUTPUTSQA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Noninverted, 3–state, latch outputs.

SQH (Pin 9)

Noninverted, Serial Data Output. This is the output of theeighth stage of the 8–bit shift register. This output does nothave three–state capability.

MC74HC595A


SWITCHING WAVEFORMS

SERIALINPUT A 50%

50%SWITCHCLOCK

VCC

GND

VALID

tsu th

Figure 5.

SHIFTCLOCK

OUTPUTSQH

tr tfVCC

GND

90%50%

10%

90%50%

10%

tPLH tPHL

tTLH tTHL

tw

1/fmax

RESET

OUTPUTSQH

SHIFTCLOCK

tw

50%

50%

50%

VCC

GND

VCC

GND

tPHL

trec

tsu

50%

50%

VCC

GND

LATCHCLOCK

QA–QHOUTPUTS

50%

tPLH tPHL

tTLH tTHL

90%50%

10%

VCC

GND

VCC

GND

SHIFTCLOCK

LATCHCLOCK

Figure 3.

VCC

GNDtw

Figure 1. Figure 2.

Figure 4.

Figure 6.

OUTPUT Q

OUTPUT Q

50%

50%

90%

10%

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

OUTPUTENABLE

50%

TEST CIRCUITS


CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT


CL*

TEST POINT

DEVICEUNDERTEST


1 kΩ

Figure 7. Figure 8.

MC74HC595A


D

R

Q

SRA

D Q

LRA

D Q

SRB

D Q

LRB

R

D Q

SRC

D Q

LRC

R

D Q

SRD

D Q

LRD

R

D Q

SRE

D Q

LRE

R

D Q

SRF

D Q

LRF

R

D Q

SRG

D Q

LRG

R

D Q

SRH

D Q

LRH

R


OUTPUTENABLE

LATCHCLOCK

SERIALDATA

INPUT A

SHIFTCLOCK

RESET

13

12

14

11

10

15

1

2

3

4

5

6

7

9

QA

QB

QC

QD

QE

QF

QG

QH

SERIALDATA

OUTPUT SQH

PARALLELDATA

OUTPUTS

MC74HC595A


TIMING DIAGRAM

SHIFTCLOCK

SERIAL DATAINPUT A

RESET

LATCHCLOCK

OUTPUTENABLE

QA

QB

QC

QD

QE

QF

QG

QH

SERIAL DATAOUTPUT SQH

NOTE: implies that the output is in a high–impedancestate.



MC74HC4020A/D


The MC74C4020A is identical in pinout to the standard CMOSMC14020B. The device inputs are compatible with standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.

This device consists of 14 master–slave flip–flops with 12 stagesbrought out to pins. The output of each flip–flop feeds the next and thefrequency at each output is half of that of the preceding one. Reset isasynchronous and active–high.

State changes of the Q outputs do not occur simultaneously becauseof internal ripple delays. Therefore, decoded output signals are subjectto decoding spikes and may have to be gated with the Clock of theHC4020A for some designs.






• In Compliance With JEDEC Standard No. 7A Requirements


LOGIC DIAGRAM

Q19

Q47

Q55

Q64

Q76

Q813

Q912

Q1014

Q1115

Q121

Q132

Q143

Clock10

Reset11 Pin 16 = VCC

Pin 8 = GND

1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

Q11 Q10 Q8 Q9 Reset Clock Q1

Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND

Pinout: 16–Lead Plastic Package(Top View)

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC4020ANAWLYYWW

1

16

HC4020AAWLYWW


HC4020A

ALYW

1

16








FUNCTION TABLE

Clock Reset Output State

X

L

L

H

No Charge

Advance to Next State

All Outputs Are Low

MC74HC4020A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C







MinÎÎÎÎ

MaxÎÎÎÎÎÎ




2.0ÎÎÎÎ

6.0ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



0ÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ




VCC = 4.5 VVCC = 6.0 V


0000

ÎÎÎÎÎÎÎÎ

1000600500400


ns


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40



MC74HC4020A



Symbol Unit

Guaranteed LimitVCC

VConditionParameterSymbol Unit≤125°C≤85°C–55 to 25°CVCC

VConditionParameter




6.0 4 40 160 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

fmax Maximum Clock Frequency (50% Duty Cycle)(Figures 1 and 4)

2.03.04.56.0

10153050

9.0142850

8.0122540

MHz

tPLH,tPHL

Maximum Propagation Delay, Clock to Q1*(Figures 1 and 4)

2.03.04.56.0

96633125

106713630

115884035

ns

tPHL Maximum Propagation Delay, Reset to Any Q(Figures 2 and 4)

2.03.04.56.0

45303026

52363532

65404035

ns

tPLH,tPHL

Maximum Propagation Delay, Qn to Qn+1(Figures 3 and 4)

2.03.04.56.0

69401714

80452115

90502822

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321915

110362219

ns



* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] nsVCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns




MC74HC4020A



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

trec Minimum Recovery Time, Reset Inactive to Clock(Figure 2)

2.03.04.56.0

302054

402586

5030129

ns

tw Minimum Pulse Width, Clock(Figure 1)

2.03.04.56.0

70401513

80451916

90502420

ns

tw Minimum Pulse Width, Reset(Figure 2)

2.03.04.56.0

70401513

80451916

90502420

ns

tr, tf Maximum Input Rise and Fall Times(Figure 1)

2.03.04.56.0

1000800500400

1000800500400

1000800500400

ns


PIN DESCRIPTIONS

INPUTSClock (Pin 10)

Negative–edge triggering clock input. A high–to–lowtransition on this input advances the state of the counter.

Reset (Pin 11)Active–high reset. A high level applied to this input

asynchronously resets the counter to its zero state, thusforcing all Q outputs low.

OUTPUTSQ1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3)

Active–high outputs. Each Qn output divides the Clockinput frequency by 2N.

SWITCHING WAVEFORMS

tf

Clock

Q1

VCC

GND

90%50%10%

tr

tw

90%50%

10%

tPHL

1/fMAXtPLH

tTLH tTHL

Clock

VCC

GND

tw

trec

50%

Figure 1. Figure 2.

Reset

VCC

GND50%

Any Q 50%

tPHL

MC74HC4020A


SWITCHING WAVEFORMS (continued)

50%

QnVCC

GND50%

Qn+1

CL*


TESTPOINT

DEVICEUNDERTEST

OUTPUT


tPLH tPHL

Figure 5. Expanded Logic Diagram

Clock10

C

C

R

Reset11

Q

Q

C

C

R

Q

Q

Q1

9

C

C

Q

Q

C

C

Q

Q

C

C

Q

Q

C

C

Q

Q4

7

Q5

5

Q12

1

Q13

2

Q14

3

Q6 = Pin 4Q7 = Pin 6Q8 = Pin 13

Q9 = Pin 12Q10 = Pin 14Q11 = Pin 15

VCC = Pin 16GND = Pin 8

MC74HC4020A


Clock

Reset

Q4

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384

Q5

Q6

Q7

Q8

Q9

Q10

Q12

Q13

Q14



Time–Base GeneratorA 60Hz sinewave obtained through a 1.0 Megohm resistor

connected directly to a standard 120 Vac power line isapplied to the input of the MC54/74HC14A, Schmitt-triggerinverter. The HC14A squares–up the input waveform and

feeds the HC4020A. Selecting outputs Q5, Q10, Q11, andQ12 causes a reset every 3600 clocks. The HC20 decodes thecounter outputs, produces a single (narrow) output pulse,and resets the binary counter. The resulting output frequencyis 1.0 pulse/minute.

HC4020A

Figure 7. Time–Base Generator

Clock Q5

Q10

Q11

Q12

VCC

13

12

10

9

1245

81/2HC20

1/2HC20

6

1/6 of HC14A

≥20pF

1.0M

1.0 Pulse/MinuteOutput

VCC

120Vac60Hz



MC74HC4040A/D


The MC74C4040A is identical in pinout to the standard CMOSMC14040. The device inputs are compatible with standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.

This device consists of 12 master–slave flip–flops. The output ofeach flip–flop feeds the next and the frequency at each output is half ofthat of the preceding one. The state counter advances on thenegative–going edge of the Clock input. Reset is asynchronous andactive–high.

State changes of the Q outputs do not occur simultaneously becauseof internal ripple delays. Therefore, decoded output signals are subjectto decoding spikes and may have to be gated with the Clock of theHC4040A for some designs.








LOGIC DIAGRAM

Q19

Q27

Q36

Q45

Q53

Q62

Q74

Q813

Q912

Q1014

Clock10

Reset11 Pin 16 = VCC

Pin 8 = GND

1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

Q11 Q10 Q8 Q9 Reset Clock Q1

Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND

Pinout: 16–Lead Plastic Package(Top View)

Q1115

Q121

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC4040ANAWLYYWW

1

16

HC4040AAWLYWW


HC4040A

ALYW

1

16








FUNCTION TABLE


X

L

L

H

No Charge


All Outputs Are Low

MC74HC4040A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 4.5 VVCC = 6.0 V


0000

ÎÎÎÎÎÎÎÎ

1000600500400


ns


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V



2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V



MC74HC4040A



Symbol Unit

Guaranteed LimitVCC


VConditionParameter


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40




6.0 4 40 160 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit


2.03.04.56.0

10153050

9.0142845

8.0122540

MHz

tPLH,tPHL

Maximum Propagation Delay, Clock to Q1*(Figures 1 and 4)

2.03.04.56.0

96633125

106713630

115884035

ns


2.03.04.56.0

45303026

52363532

65404035

ns

tPLH,tPHL


2.03.04.56.0

69401714

80452115

90502822

ns

tTLH,tTHL


2.03.04.56.0

75271513

95321915

110362219

ns



* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] nsVCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0V: tP = [24.4 + 12 (n–1)] ns




MC74HC4040A



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit


2.03.04.56.0

302054

402586

5030129

ns


2.03.04.56.0

70401513

80451916

90502420

ns


2.03.04.56.0

70401513

80451916

90502420

ns


2.03.04.56.0

1000800500400

1000800500400

1000800500400

ns


PIN DESCRIPTIONS

INPUTS

Clock (Pin 10)Negative–edge triggering clock input. A high–to–low

transition on this input advances the state of the counter.


asynchronously resets the counter to its zero state, thusforcing all Q outputs low.

OUTPUTSQ1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)

Active–high outputs. Each Qn output divides the Clockinput frequency by 2N.

SWITCHING WAVEFORMS

tf

Clock

Q1

VCC

GND

90%50%10%

tr

tw

90%50%

10%

tPHL

1/fMAXtPLH

tTLH tTHL

Clock

VCC

GND

tw

trec

50%

Figure 1. Figure 2.

Reset

VCC

GND50%

Any Q 50%

tPHL

MC74HC4040A


SWITCHING WAVEFORMS (continued)

50%

QnVCC

GND50%

Qn+1

CL*


TESTPOINT

DEVICEUNDERTEST

OUTPUT


tPLH tPHL


Clock10

C

C

R

Reset11

Q

Q

C

C

R

Q

Q

Q1

9

C

C

Q

Q

C

C

Q

Q

C

C

Q

Q

C

C

Q

Q2

7

Q3

6

Q10

14

Q11

15

Q12

1

Q4 = Pin 5Q5 = Pin 3Q6 = Pin 2

Q7 = Pin 4Q8 = Pin 13Q9 = Pin 12

VCC = Pin 16GND = Pin 8

MC74HC4040A


Clock

Reset

Q1

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q10

Q11


Q9

Q12


Time–Base GeneratorA 60Hz sinewave obtained through a 1.0 Megohm resistor

connected directly to a standard 120 Vac power line isapplied to the input of the MC54/74HC14A, Schmitt-triggerinverter. The HC14A squares–up the input waveform and

feeds the HC4040A. Selecting outputs Q5, Q10, Q11, andQ12 causes a reset every 3600 clocks. The HC20 decodes thecounter outputs, produces a single (narrow) output pulse,and resets the binary counter. The resulting output frequencyis 1.0 pulse/minute.

HC4040A

Figure 7. Time–Base Generator

Clock Q5

Q10

Q11

Q12

VCC

13

12

10

9

1245

81/2HC20

1/2HC20

6

1/6 of HC14A

≥20pF

1.0M

1.0 Pulse/MinuteOutput

VCC

120Vac60Hz



MC74HC4046A/D


The MC74HC4046A is similar in function to the MC14046 Metalgate CMOS device. The device inputs are compatible with standardCMOS outputs; with pullup resistors, they are compatible withLSTTL outputs.

The HC4046A phase–locked loop contains three phasecomparators, a voltage–controlled oscillator (VCO) and unity gainop–amp DEMOUT. The comparators have two common signal inputs,COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directlycoupled to large voltage signals, or indirectly coupled (with a seriescapacitor to small voltage signals). The self–bias circuit adjusts smallvoltage signals in the linear region of the amplifier. Phase comparator1 (an exclusive OR gate) provides a digital error signal PC1OUT andmaintains 90 degrees phase shift at the center frequency betweenSIGIN and COMPIN signals (both at 50% duty cycle). Phasecomparator 2 (with leading–edge sensing logic) provides digital errorsignals PC2OUT and PCPOUT and maintains a 0 degree phase shiftbetween SIGIN and COMPIN signals (duty cycle is immaterial). Thelinear VCO produces an output signal VCOOUT whose frequency isdetermined by the voltage of input VCOIN signal and the capacitorand resistors connected to pins C1A, C1B, R1 and R2. The unity gainop–amp output DEMOUT with an external resistor is used where theVCOIN signal is needed but no loading can be tolerated. The inhibitinput, when high, disables the VCO and all op–amps to minimizestandby power consumption.

Applications include FM and FSK modulation and demodulation,frequency synthesis and multiplication, frequency discrimination,tone decoding, data synchronizat ion and condit ioning,voltage–to–frequency conversion and motor speed control.


• Low Power Consumption Characteristic of CMOS Devices

• Operating Speeds Similar to LSTTL

• Wide Operating Voltage Range: 3.0 to 6.0 V

• Low Input Current: 1.0µA Maximum (except SIGIN and COMPIN)


• Low Quiescent Current: 80 µA Maximum (VCO disabled)


• Diode Protection on all Inputs


SO–16D SUFFIX

CASE 751B

http://onsemi.com

1

16


1

16

MARKINGDIAGRAMS

1

16

MC74HC4046ANAWLYYWW

1

16

HC4046AAWLYWW








1

16

HC4046A

ALYW

1

16

SOEIAJ–16F SUFFIXCASE 966

1

16

74HC4046BAWLYWW

1

16

MC74HC4046AF SOIC–EIAJ See Note 1.

MC74HC4046AFEL SOIC–EIAJ See Note 1.

1. For ordering information on the EIAJ version of theSOIC packages, please contact your local ONSemiconductor representative.

MC74HC4046A


Pin No. Symbol Name and Function

12345678910111213141516

PCPOUTPC1OUTCOMPINVCOOUT

INHC1AC1BGND

VCOINDEMOUT

R1R2

PC2OUTSIGIN

PC3OUTVCC

Phase Comparator Pulse OutputPhase Comparator 1 OutputComparator InputVCO OutputInhibit InputCapacitor C1 Connection ACapacitor C1 Connection BGround (0 V) VSSVCO InputDemodulator OutputResistor R1 ConnectionResistor R2 ConnectionPhase Comparator 2 OutputSignal InputPhase Comparator 3 OutputPositive Supply Voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎ


ParameterÎÎÎÎÎÎÎÎÎÎ

ValueÎÎÎÎÎÎ


VCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)ÎÎÎÎÎÎÎÎÎÎ


VÎÎÎÎÎÎÎÎ

VinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)ÎÎÎÎÎÎÎÎÎÎ


VÎÎÎÎÎÎÎÎ

VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)ÎÎÎÎÎÎÎÎÎÎ


VÎÎÎÎÎÎÎÎ

IinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per PinÎÎÎÎÎÎÎÎÎÎ

± 20ÎÎÎÎÎÎ

mAÎÎÎÎÎÎÎÎ

IoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per PinÎÎÎÎÎÎÎÎÎÎ

± 25ÎÎÎÎÎÎ

mAÎÎÎÎÎÎÎÎ

ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


± 50ÎÎÎÎÎÎ





750500

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C



Lead Temperature, 1 mm from Case for 10 SecondsPlastic DIP and SOIC Package†


260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



3.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

VCC DC Supply Voltage (Referenced to GND) NON–VCO 2.0 6.0 V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise and Fall Time VCC = 2.0 V(Pin 5) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns



PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

R2

PC2out

SIGin

PC3out

VCC

VCOin

DEMout

R1

VCOout

COMPin

PC1out

PCPout

GND

C1B

C1A

INH

MC74HC4046A


[Phase Comparator Section]DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol Parameter Test ConditionsVCCVolts

– 55 to25C ≤ 85°C ≤ 125°C Unit

VIH Minimum High–Level InputVoltage DC CoupledSIGIN, COMPIN

Vout = 0.1 V or VCC – 0.1 V|Iout| ≤ 20 µA

2.04.56.0

1.53.154.2

1.53.154.2

1.53.154.2

V

VIL Maximum Low–Level InputVoltage DC CoupledSIGIN, COMPIN


2.04.56.0

0.51.351.8

0.51.351.8

0.51.351.8

V

VOH Minimum High–LevelOutput VoltagePCPOUT, PCnOUT

Vin = VIH or VIL|Iout| ≤ 20 µA

2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V

Vin = VIH or VIL|Iout| ≤ 4.0 mA|Iout| ≤ 5.2 mA

4.56.0

3.985.48

3.845.34

3.75.2

(continued)

[Phase Comparator Section]DC ELECTRICAL CHARACTERISTICS – continued (Voltages Referenced to GND)

Guaranteed Limit


– 55 to25C ≤ 85°C ≤ 125°C Unit

VOL Maximum Low–LevelOutput Voltage Qa–QhPCPOUT, PCnOUT


2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


4.56.0

0.260.26

0.330.33

0.40.4

Iin Maximum Input Leakage Cur-rentSIGIN, COMPIN

Vin = VCC or GND 2.03.04.56.0

± 3.0± 7.0

± 18.0± 30.0

± 4.0± 9.0

± 23.0± 38.0

± 5.0± 11.0± 27.0± 45.0

µA

IOZ Maximum Three–StateLeakage CurrentPC2OUT

Output in High–Impedance StateVin = VIH or VILVout = VCC or GND

6.0 ± 0.5 ± 5.0 ± 10 µA

ICC Maximum Quiescent SupplyCurrent (per Package)(VCO disabled)Pins 3, 5 and 14 at VCCPin 9 at GND; Input LeakageatPins 3 and 14 to be excluded


6.0 4.0 40 160 µA


[Phase Comparator Section]AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

VCCGuaranteed Limit

Symbol ParameterVCCVolts – 55 to 25C ≤ 85°C ≤ 125°C Unit

tPLH,tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT(Figure 1)

2.04.56.0

1753530

2204437

2655345

ns

tPLH,tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT(Figure 1)

2.04.56.0

3406858

4258572

51010287

ns

MC74HC4046A


[Phase Comparator Section]AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

tPLH,tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT(Figure 1)

2.04.56.0

2705446

3406858

4058169

ns

tPLZ,tPHZ

Maximum Propagation Delay, SIGIN/COMPIN OutputDisable Time to PC2OUT (Figures 2 and 3)

2.04.56.0

2004034

2505043

3006051

ns

tPZH,tPZL

Maximum Propagation Delay, SIGIN/COMPIN OutputEnable Time to PC2OUT (Figures 2 and 3)

2.04.56.0

2304639

2905849

3456959

ns

tTLH,tTHL

Maximum Output Transition Time(Figure 1)

2.04.56.0

751513

951916

1102219

ns

[VCO Section]DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit


– 55 to25C ≤ 85°C ≤ 125°C Unit

VIH Minimum High–LevelInput VoltageINH


3.04.56.0

2.13.154.2

2.13.154.2

2.13.154.2

V

VIL Maximum Low–LevelInput VoltageINH


3.04.56.0

0.901.351.8

0.91.351.8

0.91.351.8

V

VOH Minimum High–LevelOutput VoltageVCOOUT

Vin = VIH or VIL|Iout| ≤ 20 µA

3.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


4.56.0

3.985.48

3.845.34

3.75.2

VOL Maximum Low–LevelOutput VoltageVCOOUT


3.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


4.56.0

0.260.26

0.330.33

0.40.4

Iin Maximum InputLeakage CurrentINH, VCOIN

Vin = VCC or GND 6.0 0.1 1.0 1.0 µA

Min Max Min Max Min Max

VVCOINOperating Voltage Range atVCOIN over the rangespecified for R1; Forlinearity see Fig. 15A,Parallel value of R1 and R2should be > 2.7 kΩ

INH = VIL 3.04.56.0

0.10.10.1

1.02.54.0

0.10.10.1

1.02.54.0

0.10.10.1

1.02.54.0

V

R1 Resistor Range 3.04.56.0

3.03.03.0

300300300

3.03.03.0

300300300

3.03.03.0

300300300

kΩ

R2 3.04.56.0

3.03.03.0

300300300

3.03.03.0

300300300

3.03.03.0

300300300

C1 Capacitor Range 3.04.56.0

404040

NoLimit

pF

MC74HC4046A


[VCO Section]AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

VCC– 55 to 25C ≤ 85°C ≤ 125°C

Symbol ParameterVCCVolts Min Max Min Max Min Max Unit

∆f/T Frequency Stability withTemperature Changes(Figure 13A, B, C)

3.04.56.0

%/K

fo VCO Center Frequency(Duty Factor = 50%)(Figure 14A, B, C, D)

3.04.56.0

31113

MHz

∆fVCO VCO Frequency Linearity 3.04.56.0

See Figures 15A, B, C %

∂ VCO Duty Factor at VCOOUT 3.04.56.0

Typical 50% %

[Demodulator Section]DC ELECTRICAL CHARACTERISTICS

Guaranteed Limit

VCC– 55 to 25C ≤ 85°C ≤ 125°C

Symbol Parameter Test ConditionsVCCVolts Min Max Min Max Min Max Unit

RS Resistor Range At RS > 300 kΩ theLeakage Current canInfluence VDEMOUT

3.04.56.0

505050

300300300

kΩ

VOFF Offset VoltageVCOIN to VDEMOUT

Vi = VVCOIN = 1/2 VCC;Values taken over RSRange.

3.04.56.0

See Figure 12 mV

RD Dynamic OutputResistance at DEMOUT

VDEMOUT = 1/2 VCC 3.04.56.0

Typical 25 Ω Ω

MC74HC4046A


SWITCHING WAVEFORMS

Figure 1. Figure 2.


SIGIN, COMPININPUTS 50%

90%50%

10%

PCPOUT, PC1OUTPC3OUTOUTPUTS

VCC

GNDtPHL tPLH

tTLHtTHL

SIGIN INPUT

COMPININPUT

50%

90%

50%

PC2OUT OUTPUT

VCC

GND

tPZHtPHZ

50%

VCC

GND

VOH

HIGH IMPEDANCE

SIGIN INPUT

COMPININPUT

50%

10%PC2OUT OUTPUT

VCC

GND

tPZLtPLZ

50%

VCC

GND

VOL

HIGH IMPEDANCE

TEST POINT

CL*

OUTPUT

DEVICE UNDER

TEST

*INCLUDES ALL PROBE AND JIG CAPACITANCE

50%

MC74HC4046A


DETAILED CIRCUIT DESCRIPTION

Voltage Controlled Oscillator/Demodulator OutputThe VCO requires two or three external components to

operate. These are R1, R2, C1. Resistor R1 and Capacitor C1are selected to determine the center frequency of the VCO(see typical performance curves Figure 14). R2 can be usedto set the offset frequency with 0 volts at VCO input. Forexample, if R2 is decreased, the offset frequency isincreased. If R2 is omitted the VCO range is from 0 Hz. Theeffect of R2 is shown in Figure 24, typical performancecurves. By increasing the value of R2 the lock range of thePLL is increased and the gain (volts/Hz) is decreased. Thus,for a narrow lock range, large swings on the VCO input willcause less frequency variation.

Internally, the resistors set a current in a current mirror, asshown in Figure 5. The mirrored current drives one side ofthe capacitor. Once the voltage across the capacitor charges

up to Vref of the comparators, the oscillator logic flips thecapacitor which causes the mirror to charge the opposite sideof the capacitor. The output from the internal logic is thentaken to VCO output (Pin 4).

The input to the VCO is a very high impedance CMOSinput and thus will not load down the loop filter, easing thefilters design. In order to make signals at the VCO inputaccessible without degrading the loop performance, theVCO input voltage is buffered through a unity gain Op–ampto Demod Output. This Op–amp can drive loads of 50Kohms or more and provides no loading effects to the VCOinput voltage (see Figure 12).

An inhibit input is provided to allow disabling of the VCOand all Op–amps (see Figure 5). This is useful if the internalVCO is not being used. A logic high on inhibit disables theVCO and all Op–amps, minimizing standby powerconsumption.

Figure 5. Logic Diagram for VCO

_+

_+

_+

I1

I2

R2

12

VREF

VCOIN

R1

911

10

5

6 7

4

+ +

Vref

C1 (EXTERNAL)

DEMODOUT

CURRENTMIRROR

I1 + I2 = I3

VCOOUT

INH

I3

– –

The output of the VCO is a standard high speed CMOSoutput with an equivalent LS–TTL fan out of 10. The VCOoutput is approximately a square wave. This output caneither directly feed the COMPIN of the phase comparators or

feed external prescalers (counters) to enable frequencysynthesis.

MC74HC4046A


Phase ComparatorsAll three phase comparators have two inputs, SIGIN and

COMPIN. The SIGIN and COMPIN have a special DC biasnetwork that enables AC coupling of input signals. If thesignals are not AC coupled, standard 74HC input levels arerequired. Both input structures are shown in Figure 6. The

outputs of these comparators are essentially standard 74HCoutputs (comparator 2 is TRI–STATEABLE). In normaloperation VCC and ground voltage levels are fed to the loopfilter. This differs from some phase detectors which supplya current to the loop filter and should be considered in thedesign. (The MC14046 also provides a voltage).

Figure 6. Logic Diagram for Phase Comparators

SIGIN

COMPIN

VCC VCC

VCC

14

3

13

1

15

2

PC2OUT

PCPOUT

PC3OUT

PC1OUT

Phase Comparator 1This comparator is a simple XOR gate similar to the

74HC86. Its operation is similar to an overdriven balancedmodulator. To maximize lock range the input frequenciesmust have a 50% duty cycle. Typical input and outputwaveforms are shown in Figure 7. The output of the phasedetector feeds the loop filter which averages the outputvoltage. The frequency range upon which the PLL will lockonto if initially out of lock is defined as the capture range.The capture range for phase detector 1 is dependent on theloop filter design. The capture range can be as large as thelock range, which is equal to the VCO frequency range.

To see how the detector operates, refer to Figure 7. Whentwo square wave signals are applied to this comparator, anoutput waveform (whose duty cycle is dependent on thephase difference between the two signals) results. As thephase difference increases, the output duty cycle increasesand the voltage after the loop filter increases. In order toachieve lock when the PLL input frequency increases, theVCO input voltage must increase and the phase differencebetween COMPIN and SIGIN will increase. At an inputfrequency equal to fmin, the VCO input is at 0 V. Thisrequires the phase detector output to be grounded; hence, the

two input signals must be in phase. When the inputfrequency is fmax, the VCO input must be VCC and the phasedetector inputs must be 180 degrees out of phase.

Figure 7. Typical Waveforms for PLL UsingPhase Comparator 1

VCC

GND

SIGIN

COMPIN

PC1OUT

VCOIN

The XOR is more susceptible to locking onto harmonicsof the SIGIN than the digital phase detector 2. For instance,a signal 2 times the VCO frequency results in the sameoutput duty cycle as a signal equal to the VCO frequency.The difference is that the output frequency of the 2f exampleis twice that of the other example. The loop filter and VCOrange should be designed to prevent locking on toharmonics.

MC74HC4046A


Phase Comparator 2This detector is a digital memory network. It consists of

four flip–flops and some gating logic, a three state outputand a phase pulse output as shown in Figure 6. Thiscomparator acts only on the positive edges of the inputsignals and is independent of duty cycle.

Phase comparator 2 operates in such a way as to force thePLL into lock with 0 phase difference between the VCOoutput and the signal input positive waveform edges. Figure8 shows some typical loop waveforms. First assume thatSIGIN is leading the COMPIN. This means that the VCO’sfrequency must be increased to bring its leading edge intoproper phase alignment. Thus the phase detector 2 output isset high. This will cause the loop filter to charge up the VCOinput, increasing the VCO frequency. Once the leading edgeof the COMPIN is detected, the output goes TRI–STATEholding the VCO input at the loop filter voltage. If the VCOstill lags the SIGIN then the phase detector will again chargeup the VCO input for the time between the leading edges ofboth waveforms.

If the VCO leads the SIGIN then when the leading edge ofthe VCO is seen; the output of the phase comparator goeslow. This discharges the loop filter until the leading edge ofthe SIGIN is detected at which time the output disables itselfagain. This has the effect of slowing down the VCO to againmake the rising edges of both waveforms coincidental.

When the PLL is out of lock, the VCO will be runningeither slower or faster than the SIGIN. If it is running slowerthe phase detector will see more SIGIN rising edges and sothe output of the phase comparator will be high a majorityof the time, raising the VCO’s frequency. Conversely, if theVCO is running faster than the SIGIN, the output of thedetector will be low most of the time and the VCO’s outputfrequency will be decreased.

As one can see, when the PLL is locked, the output ofphase comparator 2 will be disabled except for minorcorrections at the leading edge of the waveforms. When PC2is TRI–STATED, the PCP output is high. This output can beused to determine when the PLL is in the locked condition.

This detector has several interesting characteristics. Overthe entire VCO frequency range there is no phase differencebetween the COMPIN and the SIGIN. The lock range of thePLL is the same as the capture range. Minimal power wasconsumed in the loop filter since in lock the detector outputis a high impedance. When no SIGIN is present, the detectorwill see only VCO leading edges, so the comparator outputwill stay low, forcing the VCO to fmin.

Phase comparator 2 is more susceptible to noise, causingthe PLL to unlock. If a noise pulse is seen on the SIGIN, thecomparator treats it as another positive edge of the SIGIN

and will cause the output to go high until the VCO leadingedge is seen, potentially for an entire SIGIN period. Thiswould cause the VCO to speed up during that time. Whenusing PC1, the output of that phase detector would bedisturbed for only the short duration of the noise spike andwould cause less upset.

Phase Comparator 3This is a positive edge–triggered sequential phase

detector using an RS flip–flop as shown in Figure 6. Whenthe PLL is using this comparator, the loop is controlled bypositive signal transitions and the duty factors of SIGIN andCOMPINare not important. It has some similar characteristics to theedge sensitive comparator. To see how this detector works,assume input pulses are applied to the SIGIN andCOMPIN’s as shown in Figure 9. When the SIGIN leads theCOMPIN, the flop is set. This will charge the loop filter andcause the VCO to speed up, bringing the comparator intophase with the SIGIN. The phase angle between SIGIN andCOMPIN varies from 0° to 360° and is 180° at fo. Thevoltage swing for PC3 is greater than for PC2 butconsequently has more ripple in the signal to the VCO.When no SIGIN is present the VCO will be forced to fmax asopposed to fmin when PC2 is used.

The operating characteristics of all three phasecomparators should be compared to the requirements of thesystem design and the appropriate one should be used.

Figure 8. Typical Waveforms for PLL UsingPhase Comparator 2

VCC

GND

SIGIN

COMPINPC2OUT

VCOINPCPOUT

HIGH IMPEDANCE OFF–STATE

Figure 9. Typical Waveform for PLL UsingPhase Comparator 3

VCC

GND

SIGINCOMPIN

PC3OUTVCOIN

MC74HC4046A


Figure 10. Input Resistance at SIG IN, COMPIN with∆VI = 1.0 V at Self–Bias Point

Figure 11. Input Current at SIG IN, COMPIN with∆VI = 500 mV at Self–Bias Point

Figure 12. Offset Voltage at Demodulator Output asa Function of VCO IN and RS

Figure 13A. Frequency Stability versus AmbientTemperature: V CC = 3.0 V

800

0

VCC=3.0 V

VCC=4.5 V

VCC=6.0 V

1/2 VCC–1.0 V 1/2 VCC

4.0

–4.01/2VCC – 500 mV

VI (V)1/2 VCC 1/2 VCC + 500 mV

0

6.0

00 3.0 6.0

VCC=4.5 V RS=300 kVCC=4.5 V RS=50 k

VCC=3.0 V RS=300 kVCC=3.0 V RS=50 k

DEMOD OUT15

10

5.0

0

–5.0

–10

–15–100 –50 0 50 100 150

R1=100 kΩ

R1=300 kΩ

R1=3.0 kΩ

R1=100 kΩ

R1=300 kΩ

R1=3.0 kΩ

VCC = 3.0 VC1 = 100 pF; R2 = ∞; VVCOIN=1/3 VCC

FREQ

UEN

CY

STAB

ILIT

Y (%

)

AMBIENT TEMPERATURE (°C)

VCC=3.0 V

VCC=4.5 V

VCC=6.0 VR

IΩ

)(k

400

I I(

A)µ

V DEM

OU

T VCC=6.0 V RS=300 kVCC=6.0 V RS=50 k

Figure 13B. Frequency Stability versus AmbientTemperature: V CC = 4.5 V

Figure 13C. Frequency Stability versus AmbientTemperature: V CC = 6.0 V

R1=100 kΩ

R1=300 kΩ

R1=3.0 kΩ15

10

5.0

0

–5.0

–10

–15–100 –50 0 50 100 150

VCC = 4.5 VC1 = 100 pF; R2 = ∞; VVCOIN = 1/2 VCC


FREQ

UEN

CY

STAB

ILIT

Y (%

)

FREQ

UEN

CY

STAB

ILIT

Y (%

)

R1=100 kΩ

R1=3.0 kΩ

6.0

4.0

0

–2.0

–10–100 –50 0 50 100 150

VCC = 6.0 VC1 = 100 pF; R2 = ∞; VVCOIN=1/2 VCC


–8.0

–6.0

–4.0

2.0

8.0

10

R1=300 kΩ

1/2 VCC+1.0 V

VI (V)

VCOIN (V)

=

MC74HC4046A


Figure 14A. VCO Frequency (f VCO) as a Functionof the VCO Input Voltage (V VCOIN)

Figure 14B. VCO Frequency (f VCO) as a Functionof the VCO Input Voltage (V VCOIN)

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 3.0 kΩC1 = 39 pF

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

23

21

19

17

15

13

11

9

7.0

VVCOIN (V)

(MH

z)f VC

O

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

70

60

50

40

30

20

10

0

VVCOIN (V)

(KH

z)f VC

O

VCC = 6.0 VVCC = 4.5 V

VCC = 3.0 V

R1 = 3.0 kΩC1 = 0.1 µF

Figure 14C. VCO Frequency (f VCO) as a Functionof the VCO Input Voltage (V VCOIN)

Figure 14D. VCO Frequency (f VCO) as a Functionof the VCO Input Voltage (V VCOIN)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

2.0

1.0

0

VVCOIN (V)

(MH

z)f VC

O

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 300 kΩC1 = 39 pF

4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

1.0

VVCOIN (V)

(KH

z)f VC

O

4.5

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 300 kΩC1 = 0.1 µF

Figure 15A. Frequency Linearity versusR1, C1 and VCC

Figure 15B. Definition of VCO Frequency Linearity

∆f VC

O(%

)

2.0

1.0

–2.0

0

–1.0

100 101 102 103

R1 (kΩ)

R2 = ∞; ∆V = 0.5 VC1 = 39 pF

C1 = 1.0 µF

f2

f0f0′

f1

MIN 1/2 VCC MAX

∆V = 0.5 V OVER THE VCC RANGE:FOR VCO LINEARITY

f0′ = (f1 + f2) / 2

LINEARITY = (f0′ – f0) / f0′) x 100%

VCC=

4.5 V

6.0 V

3.0 V

4.5 V

6.0 V

3.0 V

MC74HC4046A


Figure 16. Power Dissipation versus R1 Figure 17. Power Dissipation versus R2

Figure 18. DC Power Dissipation ofDemodulator versus R S

Figure 19. VCO Center Frequency versus C1

R1 (kΩ)

106

105

104

103

100 101 102 103

P R1

W)

µ(

VCC = 6.0 V, C1 = 40 pF

VCC = 6.0 V, C1 = 1.0 µF

VCC = 4.5 V, C1 = 40 pF

VCC = 3.0 V, C1 = 40 pF

VCC = 3.0 V, C1 = 1.0 µF

CL = 50 pF; R2 = ∞; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;

VVCOIN = 1/3 VCC FOR VCC = 3.0 V; Tamb = 25°C

VCC = 6.0 V, C1 = 40 pF

VCC = 6.0 V, C1 = 1.0 µF

VCC = 4.5 V, C1 = 40 pFVCC = 4.5 V, C1 = 1.0 µF

VCC = 4.5 V, C1 = 1.0 µF

VCC = 3.0 V, C1 = 1.0 µF

CL = 50 pF; R1 = ∞; VVCOIN = 0 V; Tamb = 25°C106

105

104

103

100 101 102 103R2 (kΩ)

P R2

W)

µ(

P DEM

(W

)µ

RS (kΩ)

103

102

101

100

101 102 103

R1 = R2 = ∞; Tamb = 25°C

VCC=6.0 V

VCC=4.5 V

VCC=3.0 V

101 102 103 104 105 106

C1 (pF)

6.0 V4.5 V3.0 V6.0 V4.5 V3.0 V

VCC = INH = GND; Tamb = 25°C; R2 = ∞; VVCOIN = 1/3 VCC

R1=3.0 kΩ

R1=100 kΩ

R1=300 kΩ

f VCO

(Hz)

108

107

106

105

104

103

102

VCC = 3.0 V, C1 = 40 pF

6.0 V4.5 V3.0 V

Figure 20. Frequency Offset versus C1 Figure 21. Typical Frequency Lock Range (2f L)versus R 1C1

f off

(Hz)

108

107

106

105

104

103

102

101

C1 (pF)

101 102 103 104 105 106

6.0 V4.5 V3.0 V

6.0 V4.5 V3.0 V

6.0 V4.5 V3.0 V

VCC =108

107

106

105

104

103

102

2 fL

(Hz)

10–7 10–6 10–5 10–4 10–3 10–2 10–1

R1C1

R1 = ∞; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;

VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25°C

R2=3.0 kΩ

R2=100 kΩ

R2=300 kΩ

VCC = 4.5 V; R2 = ∞

MC74HC4046A


Figure 22. R2 versus f max Figure 23. R2 versus f min

Figure 24. R2 versus Frequency Lock Range (2f L)

FREQ

. (M

Hz)

1.0 101 104 105102 103 0

5.0

10

15

20

C1=39 pF

R2 ( kΩ)100 101 104 105 106

C1=39 pF

102 103–2.0

0

4.0

2.0

6.0

8.0

10

12

14

FREQ

. (M

Hz)

R2 ( kΩ)

R1=10 kΩR1=3 kΩ

R1=20 kΩR1=30 kΩR1=40 kΩR1=50 kΩR1=100 kΩR1=300 kΩ

R1=3.0 kΩ

R1=20 kΩ

R1=30 kΩ

R1=100 kΩ

R1=300 kΩ

R1=50 kΩ

R2 ( kΩ)1.0 101 102 103 104 105

2f

0

10

20

C1=39 pF

R1=10 kΩR1=3.0 kΩ

R1=20 kΩ

R1=30 kΩ

R1=40 kΩR1=50 kΩ

R1=100 kΩ

R1=300 kΩ

R1=40 kΩ

L(M

Hz)

R1=10 kΩ

MC74HC4046A


APPLICATION INFORMATION

The following information is a guide for approximate values of R1, R2, and C1. Figures 19, 20, and 21 should be used asreferences as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DCELECTRICAL CHARACTERISTICS tables.

Phase Comparator 1 Phase Comparator 2 Phase Comparator 3

R2 = ∞ R2 R2 = ∞ R2 R2 = ∞ R2

• Given f0

• Use f0 withFigure 19 todetermine R1 andC1.

(see Figure 23 forcharacteristics ofthe VCO operation)

• Given f0 and fL

• Calculate fminfmin = f0–fL

• Determine valuesof C1 and R2 fromFigure 20.

• Determine R1–C1from Figure 21.

• Calculate value ofR1 from the valueof C1 and theproduct of R1C1from Figure 21.


• Given fmax and f0

• Determine thevalue of R1 andC1 using Figure19 and use Figure21 to obtain 2fLand then use thisto calculate fmin.

• Given f0 and fL

• Calculate fminfmin = f0–fL





• Given fmax and f0

• Determine thevalue of R1 andC1 using Figure19 and Figure 21to obtain 2fL andthen use this tocalculate fmin.

• Given f0 and fL

• Calculate fmin:fmin = f0–fL







MC74HC4051A/D


The MC74HC4051A, MC74HC4052A and MC74HC4053A utilizesilicon–gate CMOS technology to achieve fast propagation delays,low ON resistances, and low OFF leakage currents. These analogmultiplexers/demultiplexers control analog voltages that may varyacross the complete power supply range (from VCC to VEE).

The HC4051A, HC4052A and HC4053A are identical in pinout tothe metal–gate MC14051AB, MC14052AB and MC14053AB. TheChannel–Select inputs determine which one of the AnalogInputs/Outputs is to be connected, by means of an analog switch, to theCommon Output/Input. When the Enable pin is HIGH, all analogswitches are turned off.

The Channel–Select and Enable inputs are compatible with standardCMOS outputs; with pullup resistors they are compatible with LSTTLoutputs.

These devices have been designed so that the ON resistance (Ron) ismore linear over input voltage than Ron of metal–gate CMOS analogswitches.

For a multiplexer/demultiplexer with injection current protection,see HC4851A and HC4852A.• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V

• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V

• Improved Linearity and Lower ON Resistance Than Metal–GateCounterparts

• Low Noise

• In Compliance With the Requirements of JEDEC Standard No. 7A

• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent GatesHC4052A — 168 FETs or 42 Equivalent GatesHC4053A — 156 FETs or 39 Equivalent Gates

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16

1

16


SO–16 WIDEDW SUFFIXCASE 751G

1

16

1

16

MARKINGDIAGRAMS

1

16

HC405xANAWLYYWW

1

16

HC405xADAWLYYWW


HC405xA

ALYW

1

16

1

16

HC405xAAWLYWW

See detailed ordering and shipping information in the packagedimensions section on page 331 of this data sheet.



1

16

74HC405xBAWLYWW

1

16

MC74HC4051A, MC74HC4052A, MC74HC4053A


LOGIC DIAGRAMMC74HC4051A

Single–Pole, 8–Position Plus Common Off

X013

X114

X215

X312

X41

X55

X62

X74

A11

B10

C9

ENABLE6

MULTIPLEXER/DEMULTIPLEXER

X3

ANALOGINPUTS/

CHANNEL

INPUTS

PIN 16 = VCCPIN 7 = VEEPIN 8 = GND

COMMONOUTPUT/INPUT

1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

X2 X1 X0 X3 A B C

X4 X6 X X7 X5 Enable VEE GND

Pinout: MC74HC4051A (Top View)

OUTPUTS

SELECT

LLLLHHHHX

LLHHLLHHX

LHLHLHLHX

FUNCTION TABLE – MC74HC4051A

Control Inputs

ON ChannelsEnableSelect

C B A

X0X1X2X3X4X5X6X7

NONE

LLLLLLLLH

X = Don’t Care


Double–Pole, 4–Position Plus Common Off

X012

X114

X215

X311

Y01

Y15

Y22

Y34

A10

B9

ENABLE6

X SWITCH

Y SWITCH

X13

ANALOGINPUTS/OUTPUTS

CHANNEL-SELECTINPUTS PIN 16 = VCC

PIN 7 = VEEPIN 8 = GND

COMMONOUTPUTS/INPUTS

LLHHX

LHLHX


Control Inputs


B A

X0X1X2X3

LLLLH

X = Don’t Care


1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

X2 X1 X X0 X3 A B

Y0 Y2 Y Y3 Y1 Enable VEE GND

Y3

Y0Y1Y2Y3

NONE




Triple Single–Pole, Double–Position Plus Common Off

X012

X113

A11

B10

C9

ENABLE6

X SWITCH

Y SWITCH

X14


CHANNEL-SELECTINPUTS

PIN 16 = VCCPIN 7 = VEEPIN 8 = GND


LLLLHHHHX

LLHHLLHHX

LHLHLHLHX


Control Inputs


C B A

LLLLLLLLH

X = Don’t Care


1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

Y X X1 X0 A B C

Y1 Y0 Z1 Z Z0 Enable VEE GND

Z0Z0Z0Z0Z1Z1Z1Z1

Y0Y0Y1Y1Y0Y0Y1Y1

X0X1X0X1X0X1X0X1

NONE

Y02

Y11 Y

15

Z05

Z13 Z

4Z SWITCH

NOTE: This device allows independent control of each switch.Channel–Select Input A controls the X–Switch, Input B controlsthe Y–Switch and Input C controls the Z–Switch

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎSymbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎÎÎValue


ÎÎÎÎÎÎÎÎ

VCC


Positive DC Supply Voltage (Referenced to GND)(Referenced to VEE)


– 0.5 to + 7.0– 0.5 to + 14.0

ÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VEEÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage (Referenced to GND)ÎÎÎÎÎÎÎÎÎÎ



VISÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input VoltageÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VEE – 0.5 toVCC + 0.5

ÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ


Digital Input Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ

I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current, Into or Out of Any Pin ÎÎÎÎÎÎÎÎÎÎ

± 25 ÎÎÎÎÎÎ

mA



Power Dissipation in Still Air, Plastic DIP†EIAJ/SOIC Package†

TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ


Storage Temperature RangeÎÎÎÎÎÎÎÎÎÎ






260

ÎÎÎÎÎÎÎÎÎ

C


†Derating — Plastic DIP: – 10 mW/C from 65 to 125CEIAJ/SOIC Package: – 7 mW/C from 65 to 125CTSSOP Package: – 6.1 mW/C from 65 to 125C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).






ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit


VCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)(Referenced to VEE)

ÎÎÎÎÎÎÎÎÎ

2.02.0ÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ

VEEÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage, Output (Referenced toGND)

ÎÎÎÎÎÎ

– 6.0 ÎÎÎÎ

GNDÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VISÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input VoltageÎÎÎÎÎÎ

VEEÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ

VinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)ÎÎÎÎÎÎ

GNDÎÎÎÎ

VCCÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ

VIO*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Static or Dynamic Voltage Across SwitchÎÎÎÎÎÎÎÎÎÎ

1.2ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ



– 55ÎÎÎÎ

+ 125ÎÎÎÎÎÎ



Input Rise/Fall Time VCC = 2.0 V(Channel Select or Enable Inputs) VCC = 3.0 V

VCC = 4.5 VVCC = 6.0 V


0000

ÎÎÎÎÎÎÎÎ

1000600500400


ns

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may bedrawn; i.e., the current out of the switch may contain both VCC and switch input components.The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted

VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit

VIH Minimum High–Level InputVoltage, Channel–Select orEnable Inputs

Ron = Per Spec 2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V

VIL Maximum Low–Level InputVoltage, Channel–Select orEnable Inputs

Ron = Per Spec 2.03.04.56.0

0.50.91.351.8

0.50.91.351.8

0.50.91.351.8

V

Iin Maximum Input Leakage Current,Channel–Select or Enable Inputs

Vin = VCC or GND,VEE = – 6.0 V

6.0 ± 0.1 ± 1.0 ± 1.0 µA


Channel Select, Enable andVIS = VCC or GND; VEE = GNDVIO = 0 V VEE = – 6.0

6.06.0

14

1040

2080

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).



DC CHARACTERISTICS — Analog Section

Guaranteed Limit

Symbol Parameter Condition VCC VEE –55 to 25°C ≤85°C ≤125°C Unit

Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC toVEE; IS ≤ 2.0 mA(Figures 1, 2)

4.54.56.0

0.0– 4.5– 6.0

190120100

240150125

280170140

Ω

Vin = VIL or VIH; VIS = VCC orVEE (Endpoints); IS ≤ 2.0 mA(Figures 1, 2)

4.54.56.0

0.0– 4.5– 6.0

15010080

190125100

230140115

∆Ron Maximum Difference in “ON”Resistance Between Any TwoChannels in the Same Package

Vin = VIL or VIH;VIS = 1/2 (VCC – VEE);IS ≤ 2.0 mA

4.54.56.0

0.0– 4.5– 6.0

301210

351512

401814

Ω

Ioff Maximum Off–Channel LeakageCurrent, Any One Channel

Vin = VIL or VIH;VIO = VCC – VEE;Switch Off (Figure 3)

6.0 – 6.0 0.1 0.5 1.0µA

Maximum Off–Channel HC4051ALeakage Current, HC4052ACommon Channel HC4053A

Vin = VIL or VIH;VIO = VCC – VEE;Switch Off (Figure 4)

6.06.06.0

– 6.0– 6.0– 6.0

0.20.10.1

2.01.01.0

4.02.02.0

Ion Maximum On–Channel HC4051ALeakage Current, HC4052AChannel–to–Channel HC4053A

Vin = VIL or VIH;Switch–to–Switch =VCC – VEE; (Figure 5)

6.06.06.0

– 6.0– 6.0– 6.0

0.20.10.1

2.01.01.0

4.02.02.0

µA


VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tPLH,tPHL

Maximum Propagation Delay, Channel–Select to Analog Output(Figure 9)

2.03.04.56.0

270905945

3201107965

3501258575

ns

tPLH,tPHL

Maximum Propagation Delay, Analog Input to Analog Output(Figure 10)

2.03.04.56.0

40251210

60301513

70321815

ns

tPLZ,tPHZ

Maximum Propagation Delay, Enable to Analog Output(Figure 11)

2.03.04.56.0

160704839

200956355

2201107663

ns

tPZL,tPZH

Maximum Propagation Delay, Enable to Analog Output(Figure 11)

2.03.04.56.0

2451154939

3151456958

3451558367

ns

Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF

CI/O Maximum Capacitance Analog I/O 35 35 35 pF

(All Switches Off) Common O/I: HC4051AHC4052AHC4053A

1308050

1308050

1308050

Feedthrough 1.0 1.0 1.0

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor High–Speed CMOS Data Book (DL129/D)


CPD Power Dissipation Capacitance (Figure 13)* HC4051AHC4052AHC4053A

458045

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High–Speed CMOS Data Book (DL129/D).



ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

VCC VEE Limit*


VVEE

V 25°C Unit

BW Maximum On–Channel BandwidthMi i F R

fin = 1MHz Sine Wave; Adjust fin Voltage toObt i 0dB t V I f

‘51 ‘52 ‘53 MHzor Minimum Frequency Response(Figure 6)

Obtain 0dBm at VOS; Increase finFrequency Until dB Meter Reads –3dB;RL = 50Ω, CL = 10pF

2.254.506.00

–2.25–4.50–6.00

808080

959595

120120120

— Off–Channel Feedthrough Isolation(Figure 7)

fin = Sine Wave; Adjust fin Voltage toObtain 0dBm at VIS

fin = 10kHz, RL = 600Ω, CL = 50pF

2.254.506.00

–2.25–4.50–6.00

–50–50–50

dB

fin = 1.0MHz, RL = 50Ω, CL = 10pF

2.254.506.00

–2.25–4.50–6.00

–40–40–40

— Feedthrough Noise.Channel–Select Input to CommonI/O (Figure 8)

Vin ≤ 1MHz Square Wave (tr = tf = 6ns);Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600Ω, CL = 50pF

2.254.506.00

–2.25–4.50–6.00

25105135

mVPP

RL = 10kΩ, CL = 10pF

2.254.506.00

–2.25–4.50–6.00

35145190

— Crosstalk Between Any TwoSwitches (Figure 12)(Test does not apply to HC4051A)

fin = Sine Wave; Adjust fin Voltage toObtain 0dBm at VIS

fin = 10kHz, RL = 600Ω, CL = 50pF

2.254.506.00

–2.25–4.50–6.00

–50–50–50

dB

fin = 1.0MHz, RL = 50Ω, CL = 10pF

2.254.506.00

–2.25–4.50–6.00

–60–60–60

THD Total Harmonic Distortion(Figure 14)

fin = 1kHz, RL = 10kΩ, CL = 50pFTHD = THDmeasured – THDsource

VIS = 4.0VPP sine waveVIS = 8.0VPP sine wave

VIS = 11.0VPP sine wave

2.254.506.00

–2.25–4.50–6.00

0.100.080.05

%

*Limits not tested. Determined by design and verified by qualification.

Figure 1a. Typical On Resistance, V CC – VEE = 2.0 V Figure 1b. Typical On Resistance, V CC – VEE = 3.0 V

250

200

150

100

50

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Ron

, ON

RES

ISTA

NC

E (O

HM

S)

100

80

60

40

20

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

25°C

– 55°C

125°C

25°C

– 55°C

125°C

2.00

300 180

160

140

120

02.5 2.75 3.0



Figure 1c. Typical On Resistance, V CC – VEE = 4.5 V Figure 1d. Typical On Resistance, V CC – VEE = 6.0 V

120

100

80

60

40

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

75

60

45

30

15

0 1.0 2.0 3.0 4.0 5.0 6.03.5 4.5 5.5


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

20

0

25°C

– 55°C

125°C

25°C

– 55°C

125°C

90

105

00.5 1.5 2.5

Figure 1e. Typical On Resistance, V CC – VEE = 9.0 V

–4.5 –3.5

70

60

50

40

30


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

20

10

–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5

25°C

– 55°C

125°C

80

0

Figure 1f. Typical On Resistance, V CC – VEE = 12.0 V

–6.0 –5.0

60

50

40

30


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

20

10

–4.0 –3.0 –2.0 2.0 3.0 4.0 5.0 6.0

25°C

– 55°C

125°C

0–1.0 1.00

Figure 2. On Resistance Test Set–Up

PLOTTER

MINI COMPUTERPROGRAMMABLE

POWERSUPPLY

DC ANALYZER

VCC

DEVICEUNDER TEST

+–

VEE

ANALOG IN COMMON OUT

GND



Figure 3. Maximum Off Channel Leakage Current,Any One Channel, Test Set–Up

Figure 4. Maximum Off Channel Leakage Current,Common Channel, Test Set–Up

Figure 5. Maximum On Channel Leakage Current,Channel to Channel, Test Set–Up

Figure 6. Maximum On Channel Bandwidth,Test Set–Up

Figure 7. Off Channel Feedthrough Isolation,Test Set–Up

Figure 8. Feedthrough Noise, Channel Select toCommon Out, Test Set–Up

OFF

OFF

678

16

COMMON O/I

VCC

VEE

VIH

NCAVCC

VEE

VCC

OFF

OFF

678

16

COMMON O/I

VCC

VEE

VIH

ANALOG I/O

VCC

VEE

VCC

ON

OFF

678

16

COMMON O/I

VCC

VEE

VIL

VCC

VEE

VCC

N/C

A

ANALOG I/O

ON

678

16

VCC

VEE

0.1µF

CL*

finRL

dBMETER


OFF

678

16

VCC

VEE

0.1µF

CL*

finRL

dBMETER


VOS

VOS

RL

VIS

VIL or VIHCHANNEL SELECT

ON/OFF

678

16

VCC

VEE

CL*RL


CHANNEL SELECT

TESTPOINT

COMMON O/I

11

VCC

OFF/ONANALOG I/O

RL

RL

VCCGND

Vin ≤ 1 MHztr = tf = 6 ns



Figure 9a. Propagation Delays, Channel Selectto Analog Out

Figure 9b. Propagation Delay, Test Set–Up ChannelSelect to Analog Out

Figure 10a. Propagation Delays, Analog Into Analog Out

Figure 10b. Propagation Delay, Test Set–UpAnalog In to Analog Out

Figure 11a. Propagation Delays, Enable toAnalog Out

Figure 11b. Propagation Delay, Test Set–UpEnable to Analog Out

VCC

GND

CHANNELSELECT

ANALOGOUT 50%

tPLH tPHL

50%ON/OFF

678

16

VCC

CL*


CHANNEL SELECT

TESTPOINT

COMMON O/I

OFF/ONANALOG I/O

VCC

VCC

GND

ANALOGIN

ANALOGOUT 50%

tPLH tPHL

50%

ON

678

16

VCC

CL*


TESTPOINT

COMMON O/IANALOG I/O

ON/OFF

678

ENABLE

VCC

ENABLE90%50%10%

tf trVCC

GND

ANALOGOUT

tPZL

ANALOGOUT

tPZH

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

10%

90%

tPLZ

tPHZ

50%

50%

ANALOG I/O

CL*

TESTPOINT

16

VCC1kΩ

1

2

1

2

POSITION 1 WHEN TESTING tPHZ AND tPZHPOSITION 2 WHEN TESTING tPLZ AND tPZL



RL

Figure 12. Crosstalk Between Any TwoSwitches, Test Set–Up

Figure 13. Power Dissipation Capacitance, Test Set–Up

Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion

0

– 10

– 20

– 30

– 40

– 50

– 1001.0 2.0 3.125

FREQUENCY (kHz)

dB

– 60

– 70

– 80

– 90

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

ON

678

16

VEE CL*


OFF

RL

RL

VIS

RL CL*

VOSfin

0.1µF

ON/OFF

678

16

VCC

CHANNEL SELECT

NCCOMMON O/I

OFF/ONANALOG I/O

VCCA

11

VCC

VEE

ON

678

16

VCC

VEE

0.1µF

CL*

finRL

TODISTORTION

METER


VOS

VIS


The Channel Select and Enable control pins should be atVCC or GND logic levels. VCC being recognized as a logichigh and GND being recognized as a logic low. In thisexample:

VCC = +5V = logic highGND = 0V = logic low

The maximum analog voltage swings are determined bythe supply voltages VCC and VEE. The positive peak analogvoltage should not exceed VCC. Similarly, the negative peakanalog voltage should not go below VEE. In this example,the difference between VCC and VEE is ten volts. Therefore,using the configuration of Figure 15, a maximum analogsignal of ten volts peak–to–peak can be controlled. Unusedanalog inputs/outputs may be left floating (i.e., notconnected). However, tying unused analog inputs and

outputs to VCC or GND through a low value resistor helpsminimize crosstalk and feedthrough noise that may bepicked up by an unused switch.

Although used here, balanced supplies are not arequirement. The only constraints on the power supplies arethat:

VCC – GND = 2 to 6 voltsVEE – GND = 0 to –6 voltsVCC – VEE = 2 to 12 volts

and VEE ≤ GND

When voltage transients above VCC and/or below VEE areanticipated on the analog channels, external Germanium orSchottky diodes (Dx) are recommended as shown in Figure16. These diodes should be able to absorb the maximumanticipated current surges during clipping.



ANALOG

SIGNAL

Figure 15. Application Example Figure 16. External Germanium orSchottky Clipping Diodes

a. Using Pull–Up Resistors b. Using HCT Interface

Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs

ON

678

16

+5V

–5V

ANALOG

SIGNAL

+5V

–5V

+5V

–5V

11109

TO EXTERNAL CMOSCIRCUITRY 0 to 5V DIGITAL SIGNALS

ON/OFF

78

16

VCC

VEE

VEE

Dx

VCC

Dx

VEE

Dx

VCC

Dx

ANALOG

SIGNALON/OFF

678

16

+5V

VEE

ANALOG

SIGNAL

+5V

VEE

+5V

VEE

11109

R*

R R

LSTTL/NMOSCIRCUITRY

+5V

* 2K ≤ R ≤ 10K

ANALOG

SIGNALON/OFF

678

16

+5V

VEE

ANALOG

SIGNAL

+5V

VEE

+5V

VEE

11109

LSTTL/NMOSCIRCUITRY

+5V

HCTBUFFER

Figure 18. Function Diagram, HC4051A

13X0

14X1

15X2

12X3

1X4

5X5

2X6

4X7

3X

LEVELSHIFTER

LEVELSHIFTER

LEVELSHIFTER

LEVELSHIFTER

11A

10B

9C

6ENABLE





13X1

12X0

1Y1

2Y0

3Z1

5Z0

14X

LEVELSHIFTER

LEVELSHIFTER

LEVELSHIFTER

LEVELSHIFTER

11A

10B

9C

6ENABLE

12X0

14X1

15X2

11X3

1Y0

5Y1

2Y2

4Y3

3Y

LEVELSHIFTER

LEVELSHIFTER

LEVELSHIFTER

10A

9B

6ENABLE

13X

15Y

4Z



ORDERING & SHIPPING INFORMATION


MC74HC4051AN PDIP–16 500 Units / Unit Pak

MC74HC4051AD SOIC–16 48 Units / Rail

MC74HC4051ADR2 SOIC–16 2500 Units / Tape & Reel

MC74HC4051ADT TSSOP–16 96 Units / Rail

MC74HC4051ADTR2 TSSOP–16 2500 Units / Tape & Reel

MC74HC4051ADW SOIC WIDE 48 Units / Rail

MC74HC4051ADWR2 SOIC WIDE 1000 Units / Tape & Reel

MC74HC4051AF SOEIAJ–16 See Note 1.

MC74HC4051AFEL SOEIAJ–16 See Note 1.



















1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.



MC74HC4060A/D


The MC74C4060A is identical in pinout to the standard CMOSMC14060B. The device inputs are compatible with standard CMOSoutputs; with pullup resistors, they are compatible with LSTTLoutputs.

This device consists of 14 master–slave flip–flops and an oscillatorwith a frequency that is controlled either by a crystal or by an RCcircuit connected externally. The output of each flip–flop feeds thenext and the frequency at each output is half of that of the precedingone. The state of the counter advances on the negative–going edge ofthe Osc In. The active–high Reset is asynchronous and disables theoscillator to allow very low power consumption during stand–byoperation.

State changes of the Q outputs do not occur simultaneously becauseof internal ripple delays. Therefore, decoded output signals are subjectto decoding spikes and may have to be gated with Osc Out 2 of theHC4060A.








1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

Q10 Q8 Q9 Reset Osc InOsc

Out 1Osc

Out 2

Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND

Pinout: 16–Lead Plastic Package (Top View)

FUNCTION TABLE


X

L

L

H

No Charge


All Outputs Are Low

SO–16D SUFFIX

CASE 751B

http://onsemi.com


1

16


1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC4060ANAWLYYWW

1

16

HC4060AAWLYWW


HC4060A

ALYW

1

16








LOGIC DIAGRAM

Q47

Q55

Q64

Q76

Q814

Q913

Q1015

Q121

Q132

Q143

Osc In 11

Reset 12 Pin 16 = VCCPin 8 = GND

Osc Out 1 Osc Out 2

910

MC74HC4060A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ



2.5* ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



0 ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C




VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns

*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are testedat 2.0 V by driving Pin 11 with an external clock source.


VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit



2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V



2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V

VOH Minimum High–Level OutputVoltage (Q4–Q10, Q12–Q14)


2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V


3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20



MC74HC4060A



Symbol Unit

Guaranteed LimitVCC


VConditionParameter

VOL Maximum Low–Level OutputVoltage (Q4–Q10, Q12–Q14)


2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V


3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40

VOH Minimum High–Level OutputVoltage (Osc Out 1, Osc Out 2)

Vin = VCC or GND|Iout| ≤ 20µA

2.04.56.0

1.94.45.9

1.94.45.9

1.94.45.9

V

Vin =VCC or GND |Iout| ≤ 0.7mA|Iout| ≤ 1.0mA|Iout| ≤ 1.3mA

3.04.56.0

2.483.985.48

2.343.845.34

2.203.705.20

VOL Maximum Low–Level OutputVoltage (Osc Out 1, Osc Out 2)

Vin = VCC or GND|Iout| ≤ 20µA

2.04.56.0

0.10.10.1

0.10.10.1

0.10.10.1

V

Vin =VCC or GND |Iout| ≤ 0.7mA|Iout| ≤ 1.0mA|Iout| ≤ 1.3mA

3.04.56.0

0.260.260.26

0.330.330.33

0.400.400.40




6.0 4 40 160 µA



VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit


2.03.04.56.0

6.0103050

9.0142845

8.0122540

MHz

tPLH,tPHL

Maximum Propagation Delay, Osc In to Q4*(Figures 1 and 4)

2.03.04.56.0

3001806051

3752007564

4502509075

ns

tPLH,tPHL

Maximum Propagation Delay, Osc In to Q14*(Figures 1 and 4)

2.03.04.56.0

500350250200

750450275220

1000600300250

ns


2.03.04.56.0

195753933

2451004942

3001256153

ns

tPLH,tPHL


2.03.04.56.0

75601513

95751916

125952420

ns

MC74HC4060A


AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) – continued

VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit

tTLH,tTHL


2.03.04.56.0

75271513

95321916

110362219

ns



* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] nsVCC = 3.0 V: tP = [61.5+ 34.4 (n–1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns





VCCGuaranteed Limit

Symbol ParameterVCC

V –55 to 25°C ≤85°C ≤125°C Unit


2.03.04.56.0

100752017

1251002521

1501203025

ns


2.03.04.56.0

75271513

95321916

110362319

ns


2.03.04.56.0

75271513

95321916

110362319

ns


2.03.04.56.0

1000800500400

1000800500400

1000800500400

ns


MC74HC4060A


PIN DESCRIPTIONS

INPUTSOsc In (Pin 11)

Negative–edge triggering clock input. A high–to–lowtransition on this input advances the state of the counter. OscIn may be driven by an external clock source.


asynchronously resets the counter to its zero state (forcingall Q outputs low) and disables the oscillator.

OUTPUTSQ4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)

Active–high outputs. Each Qn output divides the Clockinput frequency by 2N. The user should note the Q1, Q2, Q3and Q11 are not available as outputs.

Osc Out 1, Osc Out 2 (Pins 9, 10)Oscillator outputs. These pins are used in conjunction

with Osc In and the external components to form anoscillator. When Osc In is being driven with an externalclock source, Osc Out 1 and Osc Out 2 must be left opencircuited. With the crystal oscillator configuration in Figure6, Osc Out 2 must be left open circuited.

SWITCHING WAVEFORMS

twtf

Osc In

Q

VCC

GND

90%50%10%

tr

tw

90%50%

10%

tPHL

1/fMAXtPLH

tTLH tTHL

Reset

VCC

GNDtPHL

50%

Figure 1. Figure 2.

Q

VCC

GND

50%

Osc In 50%

trec

50%

QnVCC

GND50%

Qn+1

CL*


TESTPOINT

DEVICEUNDERTEST

OUTPUT


tPLH tPHL

MC74HC4060A



C

C

R

Osc Out 29

Q

Q

C

C

R

Q

Q

C

C

Q

Q

C

C

Q

Q

C

C

Q

Q

C

C

Q

Q4

7

Q5

5

Q12

1

Q13

2

Q14

3

Q6 = Pin 4Q7 = Pin 6Q8 = Pin 14Q9 = Pin 13

Q10 = Pin 15VCC = Pin 16GND = Pin 8Osc Out 1

10

Osc In11

Reset12

Figure 6. Oscillator Circuit Using RC Configuration

Reset12

Osc In 11 Osc Out 1 10 Osc Out 2 9

RtcCtcRS

For 2.0V ≤ VCC ≤ 6.0V10Rtc > RS > 2Rtc400Hz ≤ f ≤ 400Khz:

f 13 RtcCtc

(f in Hz, Rtc in ohms, Ctc in farads)

The formula may vary for other frequencies.

Figure 7. Pierce Crystal Oscillator Circuit

Reset12

Osc In 11 Osc Out 1 10 9 Osc Out 2

Rf

C1 C2

R1

MC74HC4060A


TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25°C; Input = Pin 11, Output = Pin 10)

Type Positive Reactance (Pierce)

Input Resistance, Rin 60MΩ Minimum

Output Impedance, Zout (4.5V Supply) 200Ω (See Text)

Input Capacitance, Cin 5pF Typical

Output Capacitance, Cout 7pF Typical

Series Capacitance, Ca 5pF Typical

Open Loop Voltage Gain with Output at Full Swing, α 3Vdc Supply4Vdc Supply5Vdc Supply6Vdc Supply

5.0 Expected Minimum4.0 Expected Minimum3.3 Expected Minimum3.1 Expected Minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

Figure 8. Equivalent Crystal Networks

RS LS CS

Re Xe 212121CO

Value are supplied by crystal manufacturer (parallel resonant crystal).

Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier

Zload

–jXCo

–jXC2 R

–jXC–jXCs

jXLs

RSRload

Xload

NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part ofthe load. Ca and Rf typically have minimal effect below 2MHz.

Cin Cout

Ca

Values are listed in Table 1.

MC74HC4060A


DESIGN PROCEDURES

The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additionalimpedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from180°C.

Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.

Ze jXCo(Rs jXLs jXCs)

jXCoRs jXLs jXCs Re jXe

Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.The maximum Rs for the crystal should be used in the equation.

Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν isthe gain of the HC4060A amplifier.

Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external loadcapacitance of 32pF at the required frequency.

Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLS/Q) – Rs where Ls and Rs arecrystal parameters.

Step 5: Simultaneously solve, using a computer,

XC XC2

R Re XC2 (Xe XC)( Eq 1 )(with feedback phase shift = 180°)

Xe XC2 XCReXC2

R XCload ( Eq 2 )(where the loading capacitor is an external load, not including Co)

RloadRXCoXC2 [(XC XC2)(XC XCo) XC(XC XCo XC2)]

X2C2(XC XCo)2R2(XC XCo XC2)2( Eq 3 )

Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.

Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact thatQ = 2πfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.CHOOSING R1

Power is dissipated in the effective series resistance of thecrystal. The drive level specified by the crystal manufactureris the maximum stress that a crystal can withstand withoutdamage or excessive shift in frequency. R1 limits the drivelevel.

To verify that the maximum dc supply voltage does notoverdrive the crystal, monitor the output frequency as afunction of voltage at Osc Out 2 (Pin 9). The frequencyshould increase very slightly as the dc supply voltage isincreased. An overdriven crystal will decrease in frequencyor become unstable with an increase in supply voltage. Theoperating supply voltage must be reduced or R1 must beincreased in value if the overdriven condition exists. Theuser should note that the oscillator start-up time isproportional to the value of R1.

SELECTING RfThe feedback resistor, Rf, typically ranges up to 20MΩ. Rf

determines the gain and bandwidth of the amplifier. Properbandwidth insures oscillation at the correct frequency plusroll-off to minimize gain at undesirable frequencies, such as

the first overtone. Rf must be large enough so as to not affectthe phase of the feedback network in an appreciable manner.

ACKNOWLEDGEMENTS AND RECOMMENDEDREFERENCES

The following publications were used in preparing thisdata sheet and are hereby acknowledged and recommendedfor reading:

Technical Note TN-24, Statek Corp.Technical Note TN-7, Statek Corp.D. Babin, “Designing Crystal Oscillators”, Machine

Design, March 7, 1985. D. Babin, “Guidelines for Crystal Oscillator Design”,

Machine Design, April 25, 1985.

ALSO RECOMMENDED FOR READING:E. Hafner, “The Piezoelectric Crystal Unit-Definitions

and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2,Feb., 1969.

D. Kemper, L. Rosine, “Quartz Crystals for FrequencyControl”, Electro-Technology, June, 1969.

P. J. Ottowitz, “A Guide to Crystal Selection”, ElectronicDesign, May, 1966.

MC74HC4060A


Clock

Reset

Q4

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384

Q5

Q6

Q7

Q8

Q9

Q10

Q12

Q13

Q14




MC74HC4066A/D


The MC74HC4066A utilizes silicon–gate CMOS technology toachieve fast propagation delays, low ON resistances, and lowOFF–channe l leakage cur ren t . Th is b i la te ra l sw i tch /multiplexer/demultiplexer controls analog and digital voltages thatmay vary across the full power–supply range (from VCC to GND).

The HC4066A is identical in pinout to the metal–gate CMOSMC14016 and MC14066. Each device has four independent switches.The device has been designed so that the ON resistances (RON) aremuch more linear over input voltage than RON of metal–gate CMOSanalog switches.

The ON/OFF control inputs are compatible with standard CMOSoutputs; with pullup resistors, they are compatible with LSTTL outputs.For analog switches with voltage–level translators, see the HC4316A.• Fast Switching and Propagation Speeds

• High ON/OFF Output Voltage Ratio

• Low Crosstalk Between Switches


• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts

• Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts

• Improved Linearity and Lower ON Resistance over Input Voltagethan the MC14016 or MC14066

• Low Noise

• Chip Complexity: 44 FETs or 11 Equivalent GatesLOGIC DIAGRAM

XA YA1 2

A ON/OFF CONTROL 13

XB YB4 3

B ON/OFF CONTROL 5

XC YC8 9

C ON/OFF CONTROL 6

XD YD11 10

D ON/OFF CONTROL 12

ANALOGOUTPUTS/INPUTS

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XDPIN 14 = VCCPIN 7 = GND

FUNCTION TABLEOn/Off Control State of

Input Analog Switch

L OffH On

This document contains information on a new product. Specifications and informationherein are subject to change without notice.





http://onsemi.com

55 / Rail


MARKINGDIAGRAMS





HC4066A

ALYW

1

14

1

14PDIP–14

N SUFFIXCASE 646

HC4066ANAWLYYWW

SOIC–14D SUFFIX

CASE 751A

1

14

HC4066ADAWLYWW

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

YD

XD

D ON/OFFCONTROL

A ON/OFFCONTROL

VCC

XC

YC

XB

YB

YA

XA

GND

C ON/OFFCONTROL

B ON/OFFCONTROL


1

14

74HC4066AAWLYWW


1. For ordering information on the EIAJ version of theSOIC packages, please contact your local ONSemiconductor representative.

MC74HC4066A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ


Positive DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ

– 0.5 to + 14.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ


Digital Input Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ


DC Current Into or Out of Any Pin ÎÎÎÎÎÎÎÎÎÎ

± 25 ÎÎÎÎÎÎ

mA



Power Dissipation in Still Air, Plastic DIP†EIAJ/SOIC Package†

TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ




C





260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ


Positive DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ

2.0 ÎÎÎÎ

12.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND) ÎÎÎÎÎÎ

GND ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND) ÎÎÎÎÎÎ

GND ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ


Static or Dynamic Voltage Across Switch ÎÎÎÎÎÎ

— ÎÎÎÎ

1.2ÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎTA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOperating Temperature, All Package Types



tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time, ON/OFF ControlInputs (Figure 10) VCC = 2.0 V

VCC = 3.0 VVCC = 4.5 VVCC = 9.0 V

VCC = 12.0 V


00000


1000600500400250


ns

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current maybe drawn; i.e., the current out of the switch may contain both VCC and switch inputcomponents. The reliability of the device will be unaffected unless the Maximum Ratings areexceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ

Symbol


Parameter


Test Conditions


VCCV


– 55 to25C



125C

ÎÎÎÎÎÎÎÎÎ

Unit


VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–Level VoltageON/OFF Control Inputs


Ron = Per Spec ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.59.012.0


1.52.13.156.38.4


1.52.13.156.38.4


1.52.13.156.38.4


V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–Level VoltageON/OFF Control Inputs


Ron = Per SpecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.59.012.0


0.50.91.352.73.6


0.50.91.352.73.6


0.50.91.352.73.6


V

ÎÎÎÎÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage CurrentON/OFF Control Inputs




± 0.1 ÎÎÎÎÎÎ


± 1.0ÎÎÎÎÎÎ

µA





Vin = VCC or GNDVIO = 0 V


6.012.0


24

ÎÎÎÎÎÎÎÎÎ

2040


40160

ÎÎÎÎÎÎÎÎÎ

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book(DL129/D).


Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.I/O pins must be connected to aproperly terminated line or bus.

MC74HC4066A


DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



– 55 to25C


125CÎÎÎÎÎÎ


RonÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum “ON” ResistanceÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIHVIS = VCC to GNDIS 2.0 mA (Figures 1, 2)


2.0†3.0†4.59.012.0


——

1207070


——

1608585


——

200100100


Ω




Vin = VIHVIS = VCC or GND (Endpoints)IS 2.0 mA (Figures 1, 2)


2.03.04.59.012.0


——705030


——856060


——

1008080



∆RonÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Difference in “ON”Resistance Between Any TwoChannels in the Same Package


Vin = VIHVIS = 1/2 (VCC – GND)IS 2.0 mA


2.04.59.012.0


—201515


—252020


—302525


Ω


IoffÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Off–Channel LeakageCurrent, Any One Channel


Vin = VILVIO = VCC or GNDSwitch Off (Figure 3)






µA


IonÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum On–Channel LeakageCurrent, Any One Channel ÎÎÎÎÎÎÎÎ


Vin = VIHVIS = VCC or GND(Figure 4)






µA

†At supply voltage (VCC) approaching 3 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltageoperation, it is recommended that these devices only be used to control digital signals.


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎSymbol




– 55 to25C


ÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tPLH,tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Analog Input to Analog Output(Figures 8 and 9)


2.03.04.59.012.0


4030555


5040777


6050888


ns


tPLZ,tPHZ


Maximum Propagation Delay, ON/OFF Control to Analog Output(Figures 10 and 11)


2.03.04.59.012.0


8060202020


9070252525


11080353535


ns


tPZL,tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output(Figures 10 and 1 1)


2.03.04.59.012.0


8045202020


9050252525


10060303030


ns


C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Capacitance ON/OFF Control InputÎÎÎÎÎÎÎÎ


10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF



Control Input = GNDAnalog I/O

Feedthrough


——


351.0

ÎÎÎÎÎÎÎÎÎ

351.0


351.0

ÎÎÎÎÎÎÎÎÎNOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).


CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF


MC74HC4066A


ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)


Symbol


Parameter


Test Conditions

ÎÎÎÎÎÎÎÎÎ

VCCV


Limit*25C

54/74HC

ÎÎÎÎÎÎÎÎÎ


BW ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum On–Channel BandwidthorMinimum Frequency Response

(Figure 5)


fin = 1 MHz Sine WaveAdjust fin Voltage to Obtain 0 dBm at VOSIncrease fin Frequency Until dB Meter Reads – 3 dB

RL = 50 Ω, CL = 10 pF


4.59.012.0


150160160


MHz


— ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Off–Channel Feedthrough Isolation(Figure 6)


fin Sine WaveAdjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

ÎÎÎÎÎÎÎÎÎ

4.59.012.0


– 50– 50– 50

ÎÎÎÎÎÎÎÎÎ

dB




fin = 1.0 MHz, RL = 50 Ω, CL = 10 pFÎÎÎÎÎÎÎÎÎÎÎÎ

4.59.012.0


– 40– 40– 40


ÎÎÎÎÎÎÎÎ


Feedthrough Noise, Control toSwitch

(Figure 7)


Vin 1 MHz Square Wave (tr = tf = 6 ns)Adjust RL at Setup so that IS = 0 A

RL = 600 Ω, CL = 50 pF

ÎÎÎÎÎÎÎÎÎ

4.59.012.0


60130200

ÎÎÎÎÎÎÎÎÎ

mVPP




RL = 10 kΩ, CL = 10 pFÎÎÎÎÎÎÎÎÎ

4.59.012.0


3065100



—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Crosstalk Between Any TwoSwitches

(Figure 12)



fin = 10 kHz, RL = 600 Ω, CL = 50 pF


4.59.012.0


– 70– 70– 70


dB




fin = 1.0 MHz, RL = 50 Ω, CL = 10 pFÎÎÎÎÎÎÎÎÎ

4.59.012.0


– 80– 80– 80



THDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion(Figure 14)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 kHz, RL = 10 kΩ, CL = 50 pFTHD = THDMeasured – THDSource

VIS = 4.0 VPP sine waveVIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave


4.59.012.0


0.100.060.04


%

*Guaranteed limits not tested. Determined by design and verified by qualification.

MC74HC4066A


Figure 1a. Typical On Resistance, V CC = 2.0 V Figure 1b. Typical On Resistance, V CC = 4.5 V

Figure 1c. Typical On Resistance, V CC = 6.0 V Figure 1d. Typical On Resistance, V CC = 9.0 V

Figure 1e. Typical On Resistance, V CC = 12 V Figure 2. On Resistance Test Set–Up

TBD TBD

TBDTBD

TBD

PLOTTER


POWERSUPPLY

DC ANALYZER

VCC+–


GND

DEVICEUNDER TEST

MC74HC4066A



OFF

7

14VCC

AVCC

GND

VCC

SELECTEDCONTROL

INPUT

VIL

Figure 4. Maximum On Channel Leakage Current,Test Set–Up

ON

14

VCC

N/CAGND

VCC

7

SELECTEDCONTROL

INPUT

VIH

Figure 5. Maximum On–Channel BandwidthTest Set–Up

ON

14

VCC

0.1µF CL*

findB

METER

*Includes all probe and jig capacitance.

VOS

7

SELECTEDCONTROL

INPUT

VCC

Figure 6. Off–Channel Feedthrough Isolation,Test Set–Up

OFF

7

14

VCC

0.1µF CL*

fin dBMETER


VOS

RL

VIS

SELECTEDCONTROLINPUT

Figure 7. Feedthrough Noise, ON/OFF Control toAnalog Out, Test Set–Up

14

VCC

CL*


OFF/ON

VCCGND

Vin ≤ 1 MHztr = tf = 6 ns

CONTROL

VCC/2

RLIS

RLVOS

7

SELECTEDCONTROL

INPUT

VCC/2

VCC

GNDANALOG IN

ANALOG OUT50%

tPLH tPHL

50%

Figure 8. Propagation Delays, Analog In toAnalog Out

MC74HC4066A


POSITION WHEN TESTING tPLZ AND tPZL

Figure 9. Propagation Delay Test Set–Up

ON

14

VCC


TESTPOINT

ANALOG OUTANALOG IN

CL*

7

SELECTEDCONTROL

INPUT

VCC

tr tf

VCC

GND

HIGH IMPEDANCE

VOL

VOH

HIGH IMPEDANCE

CONTROL

ANALOGOUT

90%50%

10%

50%

50%

10%

90%

tPZH tPHZ

tPZL tPLZ

Figure 10. Propagation Delay, ON/OFF Controlto Analog Out

ON/OFF

VCC

TESTPOINT

14

VCC1 kΩ

POSITION WHEN TESTING tPHZ AND tPZH

CL*

1

2

1

2


1

2

7


Figure 12. Crosstalk Between Any Two Switches,Test Set–Up

RL

ON

14

VCC OR GND CL*


OFF

RL

RL

VIS

RL CL*

VOSfin

0.1 µF

VCC/2 VCC/2

7


VCC/2

Figure 13. Power Dissipation Capacitance Test Set–Up

14

VCC

N/COFF/ON

A

N/C

7SELECTEDCONTROL

INPUT

ON/OFF CONTROL

ON

VCC

0.1 µF

CL*

fin

RL

TODISTORTION

METER


VOSVIS

7SELECTEDCONTROL

INPUT

VCC

Figure 14. Total Harmonic Distortion, Test Set–Up


VCC

VCC/2

MC74HC4066A


0

– 10

– 20

– 30

– 40

– 50

1.0 2.0

FREQUENCY (kHz)

dBm

– 60

– 70

– 80

– 90


DEVICE

SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

APPLICATION INFORMATION

The ON/OFF Control pins should be at VCC or GND logiclevels, VCC being recognized as logic high and GND beingrecognized as a logic low. Unused analog inputs/outputsmay be left floating (not connected). However, it isadvisable to tie unused analog inputs and outputs to VCC orGND through a low value resistor. This minimizes crosstalkand feedthrough noise that may be picked–up by the unusedI/O pins.

The maximum analog voltage swings are determined bythe supply voltages VCC and GND. The positive peak analogvoltage should not exceed VCC. Similarly, the negative peakanalog voltage should not go below GND. In the example

below, the difference between VCC and GND is twelve volts.Therefore, using the configuration in Figure 16, a maximumanalog signal of twelve volts peak–to–peak can becontrolled.

When voltage transients above VCC and/or below GNDare anticipated on the analog channels, external diodes (Dx)are recommended as shown in Figure 17. These diodesshould be small signal, fast turn–on types able to absorb themaximum anticipated current surges during clipping. Analternate method would be to replace the Dx diodes withMOsorbs (ON Semiconductor high current surgeprotectors). MOsorbs are fast turn–on devices ideallysuited for precise DC protection with no inherent wear outmechanism.

ANALOG O/ION

14

VCC = 12 V

ANALOG I/O+ 12 V

0 V

+ 12 V

0 V

OTHER CONTROLINPUTS

(VCC OR GND)

ON

16

VCC

Dx

Dx

VCC

Dx

Figure 16. 12 V Application Figure 17. Transient Suppressor Application

7


Dx

OTHER CONTROLINPUTS

(VCC OR GND)7


VCC

MC74HC4066A


+ 5 V

14

HC4066A

CONTROLINPUTS

7

5

6

14

15

LSTTL/NMOS

ANALOGSIGNALS

R* R* R* R*

ANALOGSIGNALS

HCTBUFFER

R* = 2 TO 10 kΩ

VDD = 5 V VCC = 5 TO 12 V

ANALOGSIGNALS

ANALOGSIGNALS

1 16 14

CONTROLINPUTS

78

MC14504

13

3

5

7

9

11

14

2

4

6

10

5

6

14

15

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4SWITCHES

COMMON I/O

1 2 3 4CONTROL INPUTS

INPUTOUTPUT

0.01 µF

LF356 OREQUIVALENT

a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

Figure 19. TTL/NMOS–to–CMOS Level ConverterAnalog Signal Peak–to–Peak Greater than 5 V

(Also see HC4316A)

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

+

–1 OF 4

SWITCHES

+ 5 V

14

CONTROLINPUTS

7

5

6

14

15

LSTTL/NMOS

ANALOGSIGNALS

ANALOGSIGNALS

1 OF 4SWITCHES

1 OF 4SWITCHES

1 OF 4SWITCHES

HC4066A

HC4066A



MC74HC4316A/D

!! High–Performance Silicon–Gate CMOS

The MC74HC4316A utilizes silicon–gate CMOS technology toachieve fast propagation delays, low ON resistances, and lowOFF–channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may varyacross the full analog power–supply range (from VCC to VEE).

The HC4316A is similar in function to the metal–gate CMOSMC14016 and MC14066, and to the High–Speed CMOS HC4066A.Each device has four independent switches. The device control andEnable inputs are compatible with standard CMOS outputs; withpullup resistors, they are compatible with LSTTL outputs. The devicehas been designed so that the ON resistances (RON) are much morelinear over input voltage than RON of metal–gate CMOS analogswitches. Logic–level translators are provided so that the On/OffControl and Enable logic–level voltages need only be VCC and GND,while the switch is passing signals ranging between VCC and VEE.When the Enable pin (active–low) is high, all four analog switches areturned off.

• Logic–Level Translator for On/Off Control and Enable Inputs

• Fast Switching and Propagation Speeds

• High ON/OFF Output Voltage Ratio


• Analog Power–Supply Voltage Range (VCC – VEE) = 2.0 to 12.0Volts

• Digital (Control) Power–Supply Voltage Range (VCC – GND) = 2.0to 6.0 Volts, Independent of VEE

• Improved Linearity of ON Resistance


PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

YD

XD

D ON/OFFCONTROL

A ON/OFFCONTROL

VCC

VEE

XC

YC

XB

YB

YA

XA

GND

ENABLE

C ON/OFFCONTROL

B ON/OFFCONTROL

FUNCTION TABLEInputs State of

On/Off AnalogEnable Control Switch

L H OnL L OffH X Off

X = don’t care

This document contains information on a product under development. ON Semiconductorreserves the right to change or discontinue this product without notice.

http://onsemi.com

MARKINGDIAGRAMS

1

16PDIP–16P SUFFIXCASE 648

HC4316ANAWLYYWW

SOIC–16D SUFFIX

CASE 751B

1

16

HC4316ADAWLYWW










1

16

74HC4316AAWLYWW


1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.


HC4316A

ALYW

1

16

MC74HC4316A


LOGIC DIAGRAM

XA

A ON/OFF CONTROL

ANALOGSWITCH

LEVELTRANSLATOR

ANALOGOUTPUTS/INPUTS

PIN 16 = VCCPIN 8 = GNDPIN 9 = VEEGND ≥ VEE

2YA

1

15

XB

B ON/OFF CONTROL

ANALOGSWITCH

LEVELTRANSLATOR

3YB

4

5

XC

C ON/OFF CONTROL

ANALOGSWITCH

LEVELTRANSLATOR

11YC

10

6

XD

D ON/OFF CONTROL

ANALOGSWITCH

LEVELTRANSLATOR

12YD

13

14

ENABLE7

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD


MAXIMUM RATINGS*ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ


Positive DC Supply Voltage (Ref. to GND)(Ref. to VEE)


– 0.5 to + 7.0– 0.5 to + 14.0

ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎVEE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNegative DC Supply Voltage (Ref. to GND)

ÎÎÎÎÎÎÎÎÎÎ– 7.0 to + 0.5

ÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎÎÎÎÎ

VISÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input VoltageÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VEE – 0.5to VCC + 0.5

ÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ


DC Input Voltage (Ref. to GND) ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ


DC Current Into or Out of Any Pin ÎÎÎÎÎÎÎÎÎÎ

± 25 ÎÎÎÎÎÎ

mA



Power Dissipation in Still Air Plastic DIP†EIAJ/SOIC Package†

TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.I/O pins must be connected to aproperly terminated line or bus.

MC74HC4316A



ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ


Positive DC Supply Voltage (Ref. to GND) ÎÎÎÎÎÎ

2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VEEÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage (Ref. to GND) ÎÎÎÎÎÎ

– 6.0 ÎÎÎÎ

GNDÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage ÎÎÎÎÎÎ

VEE ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎVin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDigital Input Voltage (Ref. to GND) ÎÎÎGND ÎÎVCCÎÎÎVÎÎÎÎÎÎÎÎVIO*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎStatic or Dynamic Voltage Across Switch

ÎÎÎÎÎÎ—ÎÎÎÎ1.2ÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎTAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOperating Temperature, All Package Types




Input Rise and Fall Time VCC = 2.0 V(Control or Enable Inputs) VCC = 3.0 V



0000

ÎÎÎÎÎÎÎÎ

1000600500400


ns

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current maybe drawn; i.e., the current out of the switch may contain both VCC and switch inputcomponents. The reliability of the device will be unaffected unless the Maximum Ratings areexceeded.

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎ



ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTest Conditions

ÎÎÎÎÎÎÎÎ


– 55 to25C





Minimum High–Level Voltage,Control or Enable Inputs


Ron = Per SpecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V



Maximum Low–Level Voltage,Control or Enable Inputs


Ron = Per SpecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V



Maximum Input LeakageCurrent, Control or EnableInputs


Vin = VCC or GNDVEE = – 6.0 V






µA





Vin = VCC or GNDVIO = 0 V VEE = GND

VEE = – 6.0


6.06.0


24

ÎÎÎÎÎÎÎÎÎ

2040


40160

ÎÎÎÎÎÎÎÎÎ

µA


MC74HC4316A


DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎÎÎ



Test ConditionsÎÎÎÎÎÎÎÎÎ

VCCVÎÎÎÎÎÎÎÎÎ

VEEVÎÎÎÎÎÎÎÎÎ




Unit


Ron ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum “ON” Resistance ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIHVIS = VCC to VEEIS 2.0 mA (Figures 1, 2)

ÎÎÎÎÎÎÎÎÎ

2.0*4 54.56.0

ÎÎÎÎÎÎÎÎÎ

0.00.0

– 4.5– 6.0

ÎÎÎÎÎÎÎÎÎ

—1609090


—200110110


—240130130

ÎÎÎÎÎÎÎÎÎ

Ω




Vin = VIHVIS = VCC or VEE (Endpoints)IS 2.0 mA (Figures 1, 2)


2.04.54.56.0


0.00.0

– 4.5– 6.0


—907070


—1159090


—140105105



∆RonÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Difference in “ON”Resistance Between Any TwoChannels in the Same Package


Vin = VIHVIS = 1/2 (VCC – VEE)IS 2.0 mA


2.04.54.56.0


0.00.0

– 4.5– 6.0


—201515


—252020


—302525


Ω


IoffÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Off–ChannelLeakage Current, Any OneChannel


Vin = VILVIO = VCC or VEESwitch Off (Figure 3)







µA


Ion ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum On–ChannelLeakage Current, Any OneChannel


Vin = VIHVIS = VCC or VEE(Figure 4)

ÎÎÎÎÎÎÎÎÎ






µA

*At supply voltage (VCC – VEE) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltageoperation, it is recommended that these devices only be used to control digital signals.


AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)



ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎSymbol




– 55 to25C


125CÎÎÎÎÎÎ


tPLH,tPHL


Maximum Propagation Delay, Analog Input to Analog Output(Figures 8 and 9)


2.04.56.0


4065


5087


6098


ns


tPLZ,tPHZ


Maximum Propagation Delay, Control or Enable to Analog Output(Figures 10 and 11)


2.04.56.0


1304030

ÎÎÎÎÎÎÎÎÎ

1605040


2006050

ÎÎÎÎÎÎÎÎÎ

ns


tPZL,tPZH


Maximum Propagation Delay, Control or Enable to Analog Output(Figures 10 and 11)


2.04.56.0


1404030

ÎÎÎÎÎÎÎÎÎ

1755040


2506050

ÎÎÎÎÎÎÎÎÎ

ns


CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Capacitance ON/OFF Controland Enable Inputs






pF



Control Input = GNDAnalog I/O

Feedthrough


——


351.0

ÎÎÎÎÎÎÎÎÎ

351.0


351.0

ÎÎÎÎÎÎÎÎÎNOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).


CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF


MC74HC4316A


ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)



ParameterÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


VCCVÎÎÎÎÎÎÎÎÎ

VEEVÎÎÎÎÎÎÎÎÎ

Limit*25CÎÎÎÎÎÎÎÎÎ

Unit


BW ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum On–Channel Bandwidth orMinimum Frequency Response

(Figure 5)


fin = 1 MHz Sine WaveAdjust fin Voltage to Obtain 0 dBm at VOSIncrease fin Frequency Until dB MeterReads – 3 dB RL = 50 Ω, CL = 10 pF


2.254.506.00

ÎÎÎÎÎÎÎÎÎ

– 2.25– 4.50– 6.00

ÎÎÎÎÎÎÎÎÎ

150160160

ÎÎÎÎÎÎÎÎÎ

MHz


—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Off–Channel Feedthrough Isolation(Figure 6)



fin = 10 kHz, RL = 600 Ω, CL = 50 pF


2.254.506.00


– 2.25– 4.50– 6.00


– 50– 50– 50


dB





2.254.506.00

ÎÎÎÎÎÎÎÎÎ

– 2.25– 4.50– 6.00

ÎÎÎÎÎÎÎÎÎ

– 40– 40– 40


ÎÎÎÎÎÎÎÎ


Feedthrough Noise, Control toSwitch

(Figure 7)


Vin 1 MHz Square Wave (tr = tf = 6 ns)Adjust RL at Setup so that IS = 0 A

RL = 600 Ω, CL = 50 pF


2.254.506.00

ÎÎÎÎÎÎÎÎÎ

– 2.25– 4.50– 6.00

ÎÎÎÎÎÎÎÎÎ

60130200

ÎÎÎÎÎÎÎÎÎ

mVPP




RL = 10 kΩ, CL = 10 pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

2.254.506.00


– 2.25– 4.50– 6.00


3065100


ÎÎÎÎÎÎÎÎ


Crosstalk Between Any TwoSwitches

(Figure 12)



fin = 10 kHz, RL = 600 Ω, CL = 50 pF


2.254.506.00

ÎÎÎÎÎÎÎÎÎ

– 2.25– 4.50– 6.00

ÎÎÎÎÎÎÎÎÎ

– 70– 70– 70

ÎÎÎÎÎÎÎÎÎ

dB





2.254.506.00

ÎÎÎÎÎÎÎÎÎ

– 2.25– 4.50– 6.00

ÎÎÎÎÎÎÎÎÎ

– 80– 80– 80



THDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion(Figure 14)


fin = 1 kHz, RL = 10 kΩ, CL = 50 pFTHD = THDMeasured – THDSource

VIS = 4.0 VPP sine waveVIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave


2.254.506.00


– 2.25– 4.50– 6.00


0.100.060.04


%

*Limits not tested. Determined by design and verified by qualification.

MC74HC4316A


Figure 1b. Typical On Resistance, VCC – VEE = 4.5 V

Figure 1d. Typical On Resistance,VCC – VEE = 9.0 V

Figure 1c. Typical On Resistance,VCC – VEE = 6.0 V

Figure 1e. Typical On Resistance,VCC – VEE = 12.0 V

Figure 1a. Typical On Resistance,VCC – VEE = 2.0 V

Figure 2. On Resistance Test Set–Up

PLOTTER


POWERSUPPLY

DC ANALYZER

VCC+–


GND

DEVICEUNDER TEST

VEE

TBD TBD

TBD TBD

TBD

MC74HC4316A



Figure 4. Maximum On Channel Leakage Current,Test Set–Up

OFF

16VCC

VEE

AVCC

VEE

VCC

O/I

789

SELECTEDCONTROL

INPUT

VIL

ON

16VCC

N/CA

VEE

VCC

VEE

789

SELECTEDCONTROL

INPUT

VIH

Figure 5. Maximum On–Channel BandwidthTest Set–Up

ON

16

VCC

0.1 µF CL*

finTO dB

METER


RL

RL

VEE

789

SELECTEDCONTROL

INPUT

VCC

Figure 6. Off–Channel Feedthrough Isolation,Test Set–Up

OFF

16

VCC

0.1 µF CL*

finTO dB

METER


RL

VEE

789

SELECTEDCONTROL

INPUT

RL

VCC

Figure 7. Feedthrough Noise, Control to Analog Out,Test Set–Up

16

VCC


ON/OFF

CONTROL

RL

SELECTEDCONTROL

INPUTVEE

789

CL*

TESTPOINT

RL

VCC

GNDANALOG IN

ANALOG OUT50%

tPLH tPHL

50%

Figure 8. Propagation Delays, Analog In toAnalog Out

VIS

MC74HC4316A


POSITION WHEN TESTING tPLZ AND tPZL


ON

16

VCC


TESTPOINT

ANALOG O/IANALOG I/O

50 pF*

SELECTEDCONTROL

INPUT

VCC

Figure 10. Propagation Delay, ON/OFF Controlto Analog Out

ON/OFF

VCC

TESTPOINT

16

VCC1 kΩ

POSITION WHEN TESTING tPHZ AND tPZH

50 pF*

1

2

1

2


1

2

Figure 12. Crosstalk Between Any Two Switches,Test Set–Up (Adjacent Channels Used)

RL

ON

16


OFF

RL

VIS

fin0.1 µF

Figure 13. Power Dissipation Capacitance Test Set–Up

16

VCC

N/CON/OFF

A

N/C

SELECTEDCONTROL

INPUT

CONTROL

ON

16

VCC

10 µF

CL*

finRL

TODISTORTION

METER


VOSVIS

SELECTEDCONTROL

INPUT

VCC

Figure 14. Total Harmonic Distortion, Test Set–Up

789


89

CONTROLOR

ENABLE

VCC

789

VEE

CL*

CL*

RL

SELECTEDCONTROL

INPUT

VCC

TESTPOINT

ANALOG I/O

789

VEE

789

VEE

50%

50%90%

10%

tPZL tPLZ

tPZH tPHZ

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

VCC

GND50%

ANALOGOUT

CONTROL

ENABLE

tr tf

MC74HC4316A



0

– 10

– 20

– 30

– 40

– 50

– 1001.0 2.0

FREQUENCY (kHz)

dBm

– 60

– 70

– 80

– 90


DEVICE

SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

The Enable and Control pins should be at VCC or GNDlogic levels, VCC being recognized as logic high and GNDbeing recognized as a logic low. Unused analoginputs/outputs may be left floating (not connected).However, it is advisable to tie unused analog inputs andoutputs to VCC or VEE through a low value resistor. Thisminimizes crosstalk and feedthrough noise that may bepicked up by the unused I/O pins.

The maximum analog voltage swings are determined bythe supply voltages VCC and VEE. The positive peak analogvoltage should not exceed VCC. Similarly, the negative peakanalog voltage should not go below VEE. In the examplebelow, the difference between VCC and VEE is twelve volts.

Therefore, using the configuration in Figure 16, a maximumanalog signal of twelve volts peak–to–peak can becontrolled.

When voltage transients above VCC and/or below VEE areanticipated on the analog channels, external diodes (Dx) arerecommended as shown in Figure 17. These diodes shouldbe small signal, fast turn–on types able to absorb themaximum anticipated current surges during clipping. Analternate method would be to replace the Dx diodes withMOsorbs (ON Semiconductor high current surgeprotectors). MOsorbs are fast turn–on devices ideallysuited for precise dc protection with no inherent wear outmechanism.

ANALOG O/ION

16

VCC = 6 V

ANALOG I/O+ 6 V

– 6 V

+ 6 V

– 6 V

ENABLE CONTROLINPUTS

(VCC OR GND)

ON

16

VCC

Dx

Dx

VCC

Dx

Figure 16. Figure 17. Transient Suppressor Application

8


DxSELECTEDCONTROLINPUT

+ 6 V

VEE

– 6 V

VCC

VEE ENABLE CONTROLINPUTS

(VCC OR GND)

VEE

VEE

MC74HC4316A


VCC = 5 V

16

HC4316A

ENABLEAND

CONTROLINPUTS

8

56

1415

TTL

ANALOGSIGNALS

R*

ANALOGSIGNALS

HCTBUFFER

R* = 2 TO 10 kΩ

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4SWITCHES

COMMON I/O

1 2 3 4

CONTROL INPUTS

INPUTOUTPUT

0.01 µF

LF356 OREQUIVALENT

a. Using Pull–Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

Figure 19. Switching a 0–to–12 V Signal Using aSingle Power Supply (GND ≠ 0 V)

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

+

–1 OF 4

SWITCHES

+ 5 V

16

HC4016A

CONTROLINPUTS

7

5

6

14

15

LSTTL/NMOS

ANALOGSIGNALS

ANALOGSIGNALS

1 OF 4SWITCHES

1 OF 4SWITCHES

1 OF 4SWITCHES

7

R*R*R*R*

VEE = 0TO – 6 V

9

VEE = 0TO – 6 V

9

12 VPOWERSUPPLY

R1 = R2

R1

R2

VCC = 12 V

VEE = 0 V

GND = 6 V

12 VPP

ANALOGINPUT

SIGNAL

C

R3

R4

VCC

VEE

1 OF 4SWITCHES

ANALOGOUTPUTSIGNAL 12 V

0

R1 = R2R3 = R4



MC74HC4538A/D

The MC74HC4538A is identical in pinout to the MC14538B. Thedevice inputs are compatible with standard CMOS outputs; withpullup resistors, they are compatible with LSTTL outputs.

This dual monostable multivibrator may be triggered by either thepositive or the negative edge of an input pulse, and produces aprecision output pulse over a wide range of pulse widths. Because thedevice has conditioned trigger inputs, there are no trigger–input riseand fall time restrictions. The output pulse width is determined by theexternal timing components, Rx and Cx. The device has a resetfunction which forces the Q output low and the Q output high,regardless of the state of the output pulse circuitry.

• Unlimited Rise and Fall Times Allowed on the Trigger Inputs

• Output Pulse is Independent of the Trigger Pulse Width

• ± 10% Guaranteed Pulse Width Variation from Part to Part (Usingthe Same Test Jig)








LOGIC DIAGRAM

PIN 16 = VCCPIN 8 = GNDRX AND CX ARE EXTERNAL COMPONENTSPIN 1 AND PIN 15 MUST BE HARD WIRED TO GND

CX1 RX1VCC

Q1

RESET 1

B1

A1TRIGGERINPUTS Q1

1 2

4

5

3

6

7

CX2 RX2VCC

Q2

RESET 2

B2

A2TRIGGERINPUTS Q2

15 14

12

11

13

10

9

SO–16D SUFFIX

CASE 751B

http://onsemi.com

1

16


1

16

MARKINGDIAGRAMS

1

16

MC74HC4538ANAWLYYWW

1

16

HC4538AAWLYWW







PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A2

RESET 2

CX2/RX2

GND

VCC

Q2

Q2

B2

A1

RESET 1

CX1/RX1

GND

GND

Q1

Q1

B1

FUNCTION TABLE

Inputs Outputs

Reset A B Q Q

H HH L

H X L Not TriggeredH H X Not Triggered

H L,H, H Not TriggeredH L L,H, Not Triggered

L X X L HX X Not Triggered

MC74HC4538A



MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ




V

ÎÎÎÎÎÎÎÎ



– 0.5 to VCC + 0.5ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin A, B, ResetCx, Rx


± 20± 30ÎÎÎÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ



± 50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ




750500ÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ


Storage TemperatureÎÎÎÎÎÎÎÎÎÎ






260

ÎÎÎÎÎÎÎÎÎ

C






Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Min ÎÎÎÎÎÎÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

Unit


VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


3.0** ÎÎÎÎÎÎÎÎÎÎÎÎ

6.0 ÎÎÎÎÎÎ

V


Vin, VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ


VCC ÎÎÎÎÎÎ

V


TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types ÎÎÎÎÎÎÎÎÎÎ

– 55 ÎÎÎÎÎÎÎÎÎÎÎÎ

+ 125 ÎÎÎÎÎÎ

C




VCC = 6.0 V


000


1000500400

ÎÎÎÎÎÎÎÎÎ

ns



A or B (Figure 5)ÎÎÎÎÎÎÎÎÎÎ


No LimitÎÎÎÎÎÎÎÎÎÎÎ


RxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

External Timing Resistor VCC < 4.5 VVCC ≥ 4.5 V


1.02.0


**

ÎÎÎÎÎÎÎÎÎ

kΩ


Cx ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

External Timing Capacitor ÎÎÎÎÎÎÎÎÎÎ


* ÎÎÎÎÎÎ

µF

* The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage dueto board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 µF/1.0 MΩ. Values of Cx> 1.0 µF may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals mayoccur for Rx > 1.0 MΩ.

** The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V.NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).



MC74HC4538A



DC CHARACTERISTICS FOR THE MC54/74HC4538A

ÎÎÎÎÎÎÎÎ




Guaranteed Limits ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ

VCC


– 55 to25C




ÎÎÎÎ



Test Conditions ÎÎÎÎÎÎ


MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

Unit


VIH ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–LevelInput Voltage



ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

1.53.154.2

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.53.154.2

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.53.154.2

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

V


VIL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–LevelInput Voltage



ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.51.351.8

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.51.351.8

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.51.351.8

ÎÎÎÎÎÎ

V


VOHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–LevelOutput Voltage



ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

1.94.45.9

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.94.45.9

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1.94.45.9

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

V




Vin = VIH or VIL|Iout| –4.0 mA|Iout| –5.2 mA


4.56.0


3.985.48



3.845.34



3.75.2



ÎÎÎÎÎÎÎÎ

VOL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–LevelOutput Voltage



ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.10.10.1

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.10.10.1

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.10.10.1

ÎÎÎÎÎÎ

V





ÎÎÎÎÎÎÎÎÎ

4.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.260.26

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.330.33

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

0.40.4



IinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum InputLeakage Current(A, B, Reset)










µA


Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current(Rx, Cx)


Vin = VCC or GND ÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

± 50ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

± 500ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

± 500 ÎÎÎÎÎÎ

nA



Maximum QuiescentSupply Current(per package)Standby State


Vin = VCC or GNDQ1 and Q2 = LowIout = 0 µA








350 ÎÎÎÎÎÎÎÎ

µA


ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum SupplyCurrent(per package)


Vin = VCC or GNDQ1 and Q2 = HighIout = 0 µA

ÎÎÎÎÎÎÎÎÎ


25C


– 45C to85C


– 55C to125C



( er ackage)Active State


Iout = 0 µAPins 2 and 14 = 0.5 VCC

ÎÎÎÎÎÎ6.0ÎÎÎÎÎÎÎÎÎÎÎÎ400ÎÎÎÎÎÎÎÎÎÎÎÎ600ÎÎÎÎÎÎÎÎÎÎÎÎ800ÎÎÎÎµA

MC74HC4538A



AC CHARACTERISTICS FOR THE MC54/74HC4538A (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎVCC


– 55 to25C



ÎÎÎÎÎÎÎÎ

ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎ

VCCVoltsÎÎÎÎÎÎMinÎÎÎÎÎÎMaxÎÎÎÎÎÎMinÎÎÎÎÎÎMaxÎÎÎÎÎÎMinÎÎÎÎÎÎMaxÎÎÎÎUnitÎÎÎÎ



Maximum Propagation DelayInput A or B to Q

(Figures 6 and 8)


2.04.56.0



1753530



2204437



2655345

ÎÎÎÎÎÎÎÎ

ns


tPHL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation DelayInput A or B to NQ

(Figures 6 and 8)

ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1953933

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

2454942

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

2955950

ÎÎÎÎÎÎ

ns


tPHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation DelayReset to Q

(Figures 7 and 8)

ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1753530

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

2204437

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

2655345

ÎÎÎÎÎÎ

ns



Maximum Propagation DelayReset to NQ

(Figures 7 and 8)


2.04.56.0



1753530



2204437



2655345

ÎÎÎÎÎÎÎÎ

ns


tTLHtTHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

751513

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

951916

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1102219

ÎÎÎÎÎÎ

ns


Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance (A. B, Reset)(Cx, Rx)

ÎÎÎÎÎÎÎÎÎ

—ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1025

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1025

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

1025

ÎÎÎÎÎÎ

pF



CPD Power Dissipation Capacitance (Per Multivibrator)* 150 pF



TIMING CHARACTERISTICS FOR THE MC54/74HC4538A (Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎ





ÎÎÎÎÎÎVCC


– 55 to25C



ÎÎÎÎÎÎÎÎ

ÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


VCCVoltsÎÎÎÎÎÎMinÎÎÎÎÎÎMaxÎÎÎÎÎÎMinÎÎÎÎÎÎMaxÎÎÎÎÎÎMinÎÎÎÎÎÎMaxÎÎÎÎ


trecÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Inactive to A or B(Figure 7)


2.04.56.0


000



000



000


ÎÎÎÎÎÎÎÎ

ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Input A or B(Figure 6)

ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

601210

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

751513

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

901815

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ns


tw ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎÎ

2.04.56.0

ÎÎÎÎÎÎÎÎÎ

601210

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

751513

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

901815

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ns



Maximum Input Rise and Fall Times, Reset(Figure 7)


2.04.56.0



1000500400



1000500400



1000500400

ÎÎÎÎÎÎÎÎ

ns



A or B(Figure 7)

ÎÎÎÎÎÎÎÎÎ

2.04.56.0


No LimitÎÎÎÎÎÎ

MC74HC4538A



OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t

ÎÎÎÎÎÎÎÎ



Conditions ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ



ÎÎÎÎÎÎÎÎÎ

VCC


– 55 to25C




ÎÎÎÎ



Timing Components ÎÎÎÎÎÎ


MinÎÎÎÎÎÎ

MaxÎÎÎÎÎÎ

MinÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

Min ÎÎÎÎÎÎ

Max ÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

τ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Pulse Width*(Figures 6 and 8)


Rx = 10 kΩ, Cx = 0.1 µF ÎÎÎÎÎÎ

5.0ÎÎÎÎÎÎ

0.63ÎÎÎÎÎÎ

0.77ÎÎÎÎÎÎ

0.6 ÎÎÎÎÎÎ

0.8 ÎÎÎÎÎÎ

0.59 ÎÎÎÎÎÎ

0.81 ÎÎÎÎ

ms


—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Pulse Width MatchBetween Circuits in thesame Package



—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


%

ÎÎÎÎÎÎÎÎ

— ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Pulse Width MatchVariation (Part to Part)


— ÎÎÎÎÎÎ

—ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

± 10 ÎÎÎÎ

%

*For output pulse widths greater than 100 µs, typically τ = kRxCx, where the value of k may be found in Figure 1.

Figure 1. Typical Output Pulse Width Constant, k,versus Supply Voltage

(For output pulse widths > 100 µs: τ = kRxCx)

Figure 2. Output Pulse Width versusTiming Capacitance

Figure 3. Normalized Output Pulse Widthversus Power Supply Voltage

0.8

0.7

0.6

0.5

0.4

0.3

10 s

1 s

100 ms

10 ms

1 ms

100 µs

10 µs

1 µs

100 ns

1.1

1

0.9

0.8

0.7

0.6

0.5

1 2 3 4 5 6 7 0.00001 0.0001 0.001 0.01 0.1 1 10 100

1 2 3 4 5 6 7

VCC, POWER SUPPLY VOLTAGE (VOLTS) CAPACITANCE (µF)

VCC, POWER SUPPLY VOLTAGE (VOLTS)

k, O

UTP

UT

PULS

E W

IDTH

CO

NST

ANT

(TYP

ICAL

)

OU

TPU

T PU

LSE

WID

TH (

)τ

OU

TPU

T PU

LSE

WID

TH (t

)(N

OR

MAL

IZED

TO

5 V

NU

MBE

R)

TA = 25°CVCC = 5 V, TA = 25°C

1 MΩ

100 kΩ

10 kΩ

1 kΩ

TA = 25°CRx = 100 kΩCx = 1000 pF

Rx = 1 MΩCx = 0.1 µF

MC74HC4538A




1.1

1.05

1

0.95

0.9

0.85

0.8

1.03

1.02

1.01

1

0.99

0.98

0.97

– 75 – 50 – 25 0 25 50 75 100 125 150

– 75 – 50 – 25 0 25 50 75 100 125 150



OU

TPU

T PU

LSE

WID

TH (

)τ(N

OR

MAL

IZED

TO

25

C N

UM

BER

)°

Rx = 10 kΩCx = 0.1 µF

VCC = 6 V

VCC = 3 V

Rx = 10 kΩCx = 0.1 µF

VCC = 5.5 V

VCC = 4.5 V

VCC = 5 VOU

TPU

T PU

LSE

WID

TH (

)τ(N

OR

MAL

IZED

TO

25

C N

UM

BER

)°

MC74HC4538A


SWITCHING WAVEFORMS

Figure 6.

A

B

Q

Q

A

B

RESET

Q

Q

50%

tPLH

50%

50%

tPLH

50%GND

VCC

GND

VCC

tr tf

90%

10%

tf

tTLH

tTHL

90%

10%

90%

10%

tPLH

tPHL

50%

50%

tf

90%

10%

50%

50% (RETRIGGERED PULSE)

50%

GND

VCC

GND

VCC

GND

VCC

tw(H)

tw(L)

tw(L) trec τ + trr

trr

τ

tPHLtPHL

Figure 7.



CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

τ

τ τ

MC74HC4538A


PIN DESCRIPTIONS

INPUTSA1, A2 (Pins 4, 12)

Positive–edge trigger inputs. A rising–edge signal oneither of these pins triggers the corresponding multivibratorwhen there is a high level on the B1 or B2 input.

B1, B2 (Pins 5, 11)

Negative–edge trigger inputs. A falling–edge signal oneither of these pins triggers the corresponding multivibratorwhen there is a low level on the A1 or A2 input.

Reset 1, Reset 2 (Pins 3, 13)

Reset inputs (active low). When a low level is applied toone of these pins, the Q output of the correspondingmultivibrator is reset to a low level and the Q output is set toa high level.

CX1/RX1 and CX2/RX2 (Pins 2 and 14)

External timing components. These pins are tied to thecommon points of the external timing resistors and

capacitors (see the Block Diagram). Polystyrene capacitorsare recommended for optimum pulse width control.Electrolytic capacitors are not recommended due to highleakages associated with these type capacitors.

GND (Pins 1 and 15)

External ground. The external timing capacitors dischargeto ground through these pins.

OUTPUTSQ1, Q2 (Pins 6, 10)

Noninverted monostable outputs. These pins (normallylow) pulse high when the multivibrator is triggered at eitherthe A or the B input. The width of the pulse is determined bythe external timing components, RX and CX.

Q1, Q2 (Pins 7, 9)

Inverted monostable outputs. These pins (normally high)pulse low when the multivibrator is triggered at either the Aor the B input. These outputs are the inverse of Q1 and Q2.

+–

+–

Figure 9.

RxCx

VCC

M1

2 kΩ

M3

M2

A

B

RESET

POWERON

RESETRESET LATCH

TRIGGER CONTROLRESET CIRCUIT

TRIGGER CONTROLCIRCUIT

OUTPUTLATCH

UPPERREFERENCE

CIRCUIT

Vre, UPPER

LOWERREFERENCE

CIRCUIT

Vre, LOWER

Q

Q

C

CB

Q

R

VCC

LOGIC DETAIL(1/2 THE DEVICE)

MC74HC4538A


CIRCUIT OPERATION

Figure 12 shows the HC4538A configured in theretriggerable mode. Briefly, the device operates as follows(refer to Figure 10): In the quiescent state, the externaltiming capacitor, Cx, is charged to VCC. When a triggeroccurs, the Q output goes high and Cx discharges quickly tothe lower reference voltage (Vref Lower 1/3 VCC). Cxthen charges, through Rx, back up to the upper referencevoltage (Vref Upper 2/3 VCC), at which point theone–shot has timed out and the Q output goes low.

The following, more detailed description of the circuitoperation refers to both the logic detail (Figure 9) and thetiming diagram (Figure 10).

QUIESCENT STATEIn the quiescent state, before an input trigger appears, the

output latch is high and the reset latch is high (#1 inFigure 10). Thus the Q output (pin 6 or 10) of the monostablemultivibrator is low (#2, Figure 10).

The output of the trigger–control circuit is low (#3), andtransistors M1, M2, and M3 are turned off. The externaltiming capacitor, Cx, is charged to VCC (#4), and both theupper and lower reference circuit has a low output (#5).

In addition, the output of the trigger–control reset circuitis low.

TRIGGER OPERATIONThe HC4538A is triggered by either a rising–edge signal

at input A (#7) or a falling–edge signal at input B (#8), withthe unused trigger input and the Reset input held at thevoltage levels shown in the Function Table. Either triggersignal will cause the output of the trigger–control circuit togo high (#9).

The trigger–control circuit going high simultaneouslyinitiates two events. First, the output latch goes low, thustaking the Q output of the HC4538A to a high state (#10).Second, transistor M3 is turned on, which allows theexternal timing capacitor, Cx, to rapidly discharge towardground (#11). (Note that the voltage across Cx appears at theinput of both the upper and lower reference circuitcomparator).

When Cx discharges to the reference voltage of the lowerreference circuit (#12), the outputs of both reference circuitswill be high (#13). The trigger–control reset circuit goeshigh, resetting the trigger–control circuit flip–flop to a lowstate (#14). This turns transistor M3 off again, allowing Cxto begin to charge back up toward VCC, with a time constantt = RxCx (#15). Once the voltage across Cx charges to abovethe lower reference voltage, the lower reference circuit willgo low allowing the monostable multivibrator to beretriggered.

2

18

1

6

5

417

143

9

8

7

QUIESCENTSTATE

TRIGGER CYCLE(A INPUT)

TRIGGER CYCLE(B INPUT) RESET RETRIGGER

trr

Vref UPPERVref LOWER

TRIGGER INPUT A(PIN 4 OR 12)

TRIGGER INPUT B(PIN 5 OR 11)

TRIGGER-CONTROLCIRCUIT OUTPUT

RX/CX INPUT(PIN 2 OR 14)

UPPER REFERENCECIRCUIT

LOWER REFERENCECIRCUIT

RESET INPUT(PIN 3 OR 13)

RESET LATCH

Q OUTPUT(PIN 6 OR 10)


10

11

12

13

15

16

19

20

21

22

23

24

25

τ τ + trr

13

τ

MC74HC4538A


When Cx charges up to the reference voltage of the upperreference circuit (#17), the output of the upper referencecircuit goes low (#18). This causes the output latch to toggle,taking the Q output of the HC4538A to a low state (#19), andcompleting the time–out cycle.

POWER–DOWN CONSIDERATIONSLarge values of Cx may cause problems when powering

down the HC4538A because of the amount of energy storedin the capacitor. When a system containing this device ispowered down, the capacitor may discharge from VCCthrough the input protection diodes at pin 2 or pin 14.Current through the protection diodes must be limited to 30mA; therefore, the turn–off time of the VCC power supplymust not be faster than t = VCCCx/(30 mA). For example,if V CC = 5.0 V and Cx = 15 µF, the VCC supply must turn offno faster than t = (5.0 V)(15 µF)/30 mA = 2.5 ms. This isusually not a problem because power supplies are heavilyfiltered and cannot discharge at this rate.

When a more rapid decrease of VCC to zero volts occurs,the HC4538A may sustain damage. To avoid this possibility,use an external damping diode, Dx, connected as shown inFigure 11. Best results can be achieved if diode Dx is chosento be a germanium or Schottky type diode able to withstandlarge current surges.

RESET AND POWER ON RESET OPERATIONA low voltage applied to the Reset pin always forces the

Q output of the HC4538A to a low state.The timing diagram illustrates the case in which reset

occurs (#20) while Cx is charging up toward the referencevoltage of the upper reference circuit (#21). When a reset

occurs, the output of the reset latch goes low (#22), turningon transistor M1. Thus Cx is allowed to quickly charge up toVCC (#23) to await the next trigger signal.

On power up of the HC4538A the power–on reset circuitwill be high causing a reset condition. This will prevent thetrigger–control circuit from accepting a trigger input duringthis state. The HC4538A’s Q outputs are low and the Q notoutputs are high.

RETRIGGER OPERATIONWhen used in the retriggerable mode (Figure 12), the

HC4538A may be retriggered during timing out of theoutput pulse at any time after the trigger–control circuitflip–flop has been reset (#24), and the voltage across Cx isabove the lower reference voltage. As long as the Cx voltageis below the lower reference voltage, the reset of theflip–flop is high, disabling any trigger pulse. This preventsM3 from turning on during this period resulting in an outputpulse width that is predictable.

The amount of undershoot voltage on RxCx during thetrigger mode is a function of loop delay, M3 conductivity,and VDD. Minimum retrigger time, trr (Figure 7), is afunction of 1) time to discharge RxCx from VDD to lowerreferencevoltage (Tdischarge); 2) loop delay (Tdelay); 3) time to chargeRxCx from the undershoot voltage back to the lowerreference voltage (Tcharge).

Figure 13 shows the device configured in thenon–retriggerable mode.

For additional information, please see Application Note(AN1558/D) titled Characterization of Retrigger Time inthe HC4538A Dual Precision Monstable Multivibrator.

DX

CX VCC

Q

Q

RESET

A

B

Figure 11. Discharge Protection During Power Down

RX

MC74HC4538A


TYPICAL APPLICATIONS

RESET = VCC

RISING–EDGETRIGGER

B = VCC

RESET = VCC


A = GND

RESET = VCC

FALLING–EDGETRIGGER

RESET = VCC


Figure 12. Retriggerable Monostable Circuitry Figure 13. Non–retriggerable Monostable Circuitry

CX

VCC

Q

Q

A

B

RX CX

VCC

Q

QA

B

RX

CX

VCC

Q

QB

RX CX

VCC

Q

Q

A

B

RX

Figure 14. Connection of Unused Section

A = GND

RESET

RXCX

VCCQ

QB

GND N/C

N/C

N/C

ONE–SHOT SELECTION GUIDE

100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 sMC14528BMC14536BMC14538BMC14541BHC4538A*

*Limited operating voltage (2–6 V)

23 HR

5 MIN

TOTAL OUTPUT PULSE WIDTH RANGERECOMMENDED PULSE WIDTH RANGE



MC74HC4851A/D

! #! # " ! Automotive Customized

These devices are pin compatible to standard HC405x andMC1405xB analog mux/demux devices, but feature injection currenteffect control. This makes them especially suited for usage inautomotive applications where voltages in excess of normal logicvoltage are common.

The injection current effect control allows signals at disabled analoginput channels to exceed the supply voltage range without affectingthe signal of the enabled analog channel. This eliminates the need forexternal diode/ resistor networks typically used to keep the analogchannel signals within the supply voltage range.

The devices utilize low power silicon gate CMOS technology. TheChannel Select and Enable inputs are compatible with standard CMOSoutputs.• Injection Current Cross–Coupling Less than 1mV/mA (See Figure 9)

• Pin Compatible to HC405X and MC1405XB Devices

• Power Supply Range (VCC – GND) = 2.0 to 6.0 V

• In Compliance With the Requirements of JEDEC Standard No. 7A


http://onsemi.com

MARKINGDIAGRAMS

1

16PDIP–16

N SUFFIXCASE 648

HC485xANAWLYYWW

SOIC–16D SUFFIX

CASE 751B


1

16

HC485xADAWLYWW

HC485xA

ALYW

1

16


SOIC–16 WIDEDW SUFFIXCASE 751G

1

16

HC485xADWAWLYWW

See detailed ordering and shipping information in the packagedimensions section on page 380 of this data sheet.




Figure 1. MC74HC4851A Logic DiagramSingle–Pole, 8–Position Plus Common Off

X013

X114

X215

X312

X41

X55

X62

X74

A11

B10

C9

ENABLE6

MULTIPLEXER/DEMULTIPLEXER X

3ANALOGINPUTS/

CHANNEL

INPUTS


COMMONOUTPUT/INPUT

1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

X2 X1 X0 X3 A B C

X4 X6 X X7 X5 Enable NC GND

Figure 2. MC74HC4851A 16–Lead Pinout (Top View)

OUTPUTS

SELECT

LLLLHHHHX

LLHHLLHHX

LHLHLHLHX


Control Inputs


C B A

X0X1X2X3X4X5X6X7

NONE

LLLLLLLLH

Figure 3. MC74HC4852A Logic DiagramDouble–Pole, 4–Position Plus Common Off

X012

X114

X215

X311

Y01

Y15

Y22

Y34

A10

B9

ENABLE6

X SWITCH

Y SWITCH

X13


CHANNEL-SELECTINPUTS PIN 16 = VCC

PIN 8 = GND


LLHHX

LHLHX


Control Inputs


B A

X0X1X2X3

LLLLH

X = Don’t Care

Figure 4. MC74HC4852A 16–Lead Pinout (Top View)

1516 14 13 12 11 10

21 3 4 5 6 7

VCC9

8

X2 X1 X X0 X3 A B

Y0 Y2 Y Y3 Y1 Enable NC GND

Y3

Y0Y1Y2Y3

NONE




MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ



Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ


Positive DC Supply Voltage (Referenced to GND)ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ


DC Input Voltage (Any Pin) (Referenced to GND)ÎÎÎÎÎÎÎÎÎÎ


V

ÎÎÎÎÎÎÎÎ


DC Current, Into or Out of Any Pin ÎÎÎÎÎÎÎÎÎÎ

± 25 ÎÎÎÎÎÎ

mA




TSSOP Package†


750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ








260

ÎÎÎÎÎÎÎÎÎ

C





ÎÎÎÎÎÎÎÎ



Min ÎÎÎÎ

MaxÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ


Positive DC Supply Voltage (Referenced to GND)ÎÎÎÎÎÎ

2.0 ÎÎÎÎ

6.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Any Pin) (Referenced to GND)ÎÎÎÎÎÎ

GND ÎÎÎÎ

VCCÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ


Static or Dynamic Voltage Across Switch ÎÎÎÎÎÎ

0.0 ÎÎÎÎ

1.2ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ



– 55 ÎÎÎÎ

+ 125ÎÎÎÎÎÎ

C



Input Rise/Fall Time VCC = 2.0 V(Channel Select or Enable Inputs) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎÎÎÎÎÎÎ

000

ÎÎÎÎÎÎ

1000500400

ÎÎÎÎÎÎÎÎÎ

ns

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may bedrawn; i.e., the current out of the switch may contain both VCC and switch input components.The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted

VCCGuaranteed Limit


V –55 to 25°C ≤85°C ≤125°C Unit

VIH Minimum High–Level InputVoltage, Channel–Select or EnableInputs

Ron = Per Spec 2.03.04.56.0

1.502.103.154.20

1.502.103.154.20

1.502.103.154.20

V

VIL Maximum Low–Level InputVoltage, Channel–Select or EnableInputs

Ron = Per Spec 2.03.04.56.0

0.500.901.351.80

0.500.901.351.80

0.500.901.351.80

V

Iin Maximum Input Leakage Currenton Digital Pins (Enable/A/B/C)

Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA


Vin(digital) = VCC or GNDVin(analog) = GND

6.0 2 20 40 µA






DC CHARACTERISTICS — Analog Section

Guaranteed Limit

Symbol Parameter Condition VCC –55 to 25°C ≤85°C ≤125°C Unit

Ron Maximum “ON” Resistance Vin = VIL or VIH;VIS = VCC toGND; IS ≤ 2.0 mA

2.03.04.56.0

17001100550400

17501200650500

18001300750600

Ω

∆Ron Delta “ON” Resistance Vin = VIL or VIH; VIS = VCC/2IS ≤ 2.0 mA

2.03.04.56.0

3001608060

40020010080

500240120100

Ω

Ioff Maximum Off–Channel LeakageCurrent,

Any One ChannelCommon Channel

Vin = VCC or GND6.0 ±0.1

±0.2±0.5±2.0

±1.0±4.0

µA

Ion Maximum On–Channel LeakageChannel–to–Channel

Vin = VCC or GND6.0 ±0.2 ±2.0 ±4.0

µA


Symbol Parameter VCC –55 to 25°C ≤85°C ≤125°C Unit

tPHL,tPLH

Maximum Propagation Delay, Analog Input to Analog Output 2.03.04.56.0

160804030

180904535

2001005040

ns

tPHL, tPHZ,PZHtPLH, tPLZ,PZL

Maximum Propagation Delay, Enable or Channel–Select toAnalog Output

2.03.04.56.0

2601608060

2801809070

30020010080

ns

Cin Maximum Input Capacitance Digital Pins(All Switches Off) Any Single Analog Pin(All Switches Off) Common Analog Pin

1035130

1035130

1035130

pF

CPD Power Dissipation Capacitance Typical 5.0 20 pF

INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = –55°C to +125°C)

Symbol Parameter Typ Max Unit Condition

V∆out Maximum Shift of Output Voltage of Enabled AnalogChannel

0.11.00.55.0

1.05.02.020

mV Iin* ≤ 1mA, RS ≤ 3,9kΩIin* ≤ 10mA, RS ≤ 3,9kΩIin* ≤ 1mA, RS ≤ 20kΩIin* ≤ 10mA, RS ≤ 20kΩ

* Iin = Total current injected into all disabled channels.



Figure 5. Typical On Resistance V CC = 2V Figure 6. Typical On Resistance V CC = 3V

Figure 7. Typical On Resistance V CC = 4.5V Figure 8. Typical On Resistance V CC = 6V

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Ron

, ON

RES

ISTA

NC

E (O

HM

S) –55°C

+25°C

+125°C


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

–55°C

+25°C

+125°C


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

–55°C

+25°C

+125°C


Ron

, ON

RES

ISTA

NC

E (O

HM

S)

–55°C

+25°C

+125°C

1100

1000

900

800

700

600

500

400

300

200

100

0

1100

1000

900

800

700

600

500

400

300

200

100

0

660

600

540

480

420

360

300

240

180

120

60

0

440

400

360

320

280

240

200

160

120

80

40

00.0 0.9 1.8 2.7 3.6 4.5 0.0 1.2 2.4 3.6 4.8 6.0

0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.6 1.2 1.8 2.4 3.0



VCC = 5VIin

Vin2 < VSS or VCC < Vin2Any Disabled Channel

VSS < Vin1 < VCCEnabled Channel

RS

Vout = Vin1 ±V∆out

Figure 9. Injection Current Coupling Specification

Channel 1Channel 2Channel 3Channel 4Channel 5Channel 6Channel 7Channel 8

Common Out

VCCHC4051A Microcontroller

A/D – Input

VCC5V6V5V

Sensor

(8x Identical Circuitry)

Figure 10. Actual TechnologyRequires 32 passive components and one extra 6V regulator

to suppress injection current into a standard HC4051 multiplexer

Channel 1Channel 2Channel 3Channel 4Channel 5Channel 6Channel 7Channel 8

Common Out

VCCHC4851A Microcontroller

A/D – Input

VCC5V

Sensor

(8x Identical Circuitry)

Figure 11. MC74HC4851A SolutionSolution by applying the HC4851A multiplexer



Figure 12. On Resistance TestSet–Up

PLOTTER


POWERSUPPLY

DC ANALYZER

VCC

DEVICEUNDER TEST

+–


GND


OFF

OFF

6

8

16

COMMON O/I

VCC

VIH

NCAVCC

VEE

VCC

Figure 14. Maximum Off Channel Leakage Current,Common Channel, Test Set–Up

OFF

OFF

6

8

16

COMMON O/I

VCC

VIH

ANALOG I/O

VCC

VEE

VCC

Figure 15. Maximum On Channel Leakage Current,Channel to Channel, Test Set–Up

ON

OFF

6

8

16

COMMON O/I

VCC

VIL

VCC

VEE

VCC

N/C

A

ANALOG I/O

Figure 16. Propagation Delays, Channel Selectto Analog Out

Figure 17. Propagation Delay, Test Set–Up ChannelSelect to Analog Out

VCC

GND

CHANNELSELECT

ANALOGOUT 50%

tPLH tPHL

50%ON/OFF

6

8

16

VCC

CL*


CHANNEL SELECT

TESTPOINT

COMMON O/I

OFF/ONANALOG I/O

VCC



Figure 18. Propagation Delays, Analog Into Analog Out

Figure 19. Propagation Delay, Test Set–UpAnalog In to Analog Out

Figure 20. Propagation Delays, Enable toAnalog Out

Figure 21. Propagation Delay, Test Set–UpEnable to Analog Out

VCC

GND

ANALOGIN

ANALOGOUT 50%

tPLH tPHL

50%

ON

6

8

16

VCC

CL*


TESTPOINT

COMMON O/IANALOG I/O

ON/OFF

6

8

ENABLE

VCC

ENABLE90%50%10%

tf trVCC

GND

ANALOGOUT

tPZL

ANALOGOUT

tPZH

HIGHIMPEDANCE

VOL

VOH

HIGHIMPEDANCE

10%

90%

tPLZ

tPHZ

50%

50%

ANALOG I/O

CL*

TESTPOINT

16

VCC10kΩ

1

2

1

2

POSITION 1 WHEN TESTING tPHZ AND tPZHPOSITION 2 WHEN TESTING tPLZ AND tPZL

Figure 22. Power Dissipation Capacitance, Test Set–Up

ON/OFF

6

8

16

VCC

CHANNEL SELECT

NCCOMMON O/I

OFF/ONANALOG I/O

VCCA

11

VCC



13X0

14X1

15X2

12X3

1X4

5X5

2X6

4X7

3X

11A

10B

9C

6ENABLE

Figure 23. Diagram of Bipolar Coupling MechanismAppears if Vin exceeds VCC, driving injection current into the substrate


+++

P+ P+

N – Substrate (on VCC potential)

Gate = VCC(Disabled) Common Analog Output

Vout > VCCDisabled Analog Mux Input

Vin > VCC + 0.7V

INJECTIONCURRENTCONTROL












10A

9B

6ENABLE

13X0

14X1

15X2

12X3

1Y0

5Y1

2Y2

4Y3

13X










3Y


ORDERING & SHIPPING INFORMATION





MC74HC4851ADW SOIC–16 WIDE 48 Units / Rail

MC74HC4851ADWR2 SOIC–16 WIDE 1000 Units / Tape & Reel






MC74HC4852ADW SOIC–16 WIDE 48 Units / Rail

MC74HC4852ADWR2 SOIC–16 WIDE 1000 Units / Tape & Reel




CHAPTER 4Application Notes

AN1410/D, Configuring and Applyingthe MC74HC4046APhase–Locked Loop 382. . . . . . . . . . . . .

AN1558/D, Characterization of Retrigger Time in theMC74HC4538A Dual Precision Monostable Multivibrator 388. . . . . . . . . .



AN1410/D

! "

A versatile device for 0.1 to 16MHzfrequency synchronization

Prepared by: Cleon Petty, Gary Tharalson & Marten SmithLogic Application Engineers

AbstractThe MC74HC4046A (hereafter designated HC4046A)

phase–locked loop contains three phase comparators, avoltage–controlled oscillator (VCO) and an outputamplifier. The user of this document should have a copy ofthe HC4046A data sheet in ON Semiconductor Data BookDL129 available for details of device operation andoperating specifications. The user should also be aware that

the following information is useful for approximating adesign but, because of process, layout and other variables,there can be substantial deviation between theory and actualresults. Therefore, it is highly recommended thatprototypes be built and checked before committing adesign to production.

Typical applications for the HC4046A usually involve aconfiguration such as shown in Figure 1.

Figure 1. Typical Phase–Locked Loop

Ref Osc Phase Detector

÷N

Low Pass Filter VCO fo

Feedback

VCO/OUTPUT FREQUENCY

The output frequency, Fo, is calculated as a function of theRef Osc input and the ÷N feedback counter:

Fo = Ref Osc * N ( 1 )

The ability of the loop to emulate the above formulamakes it ideal for multiplying an input frequency by anynumber up to the maximum of the VCO. The HC4046AVCO frequency is controlled by the equation:

VCO freq = f(I * C) ( 2 )

where I is controlled by the external resistors R1 and R2 andC by external capacitor Cext .

Frequency of oscillation is calculated by starting with thefamiliar equation:

( 3 )I c dVdt

and reworking it to obtain a formula that incorporates all thedetail to fit the HC4046A. First, the charge time of the devicefor half–cycle time is obtained as follows:

dt dV CI

and Fo1

2dt

( 4 )or, Fo1

2CdV

I

I2CdV

where I and dV must be obtained for the HC4046A.

There are two components that comprise the I charge forthe HC4046A VCO, I1 and I2. I1 is the current that sets thefrequency associated with the VCO input and is a functionof R1, VCOin, and an internal current mirror that is ratioedat 120/5 ≈ 24, resulting in the equation:

( 5 )I1VCOin

R1120

5

http://onsemi.com

APPLICATION NOTE

AN1410/D


I2 is set by R2 and adds a constant current to limit the Fo minof the VCO and is a function of Vdd, R2, and an internalcurrent mirror of ratio 23/5, resulting in the equation:

( 6 )I2 2Vdd3R2 23

5

The dV of Equation ( 4 ) is determined by design to be ≈ 1/3Vdd. Substituting this and I = I1 + I2 into Equation ( 4 ) resultsin:

Fo VCOin

R1120

5 2Vdd

3R223

5

2CextVdd

3

VCOin

R1(24) 2Vdd

3R2(4.6)

2CextVdd

3

( 7 )3VCOin

R1(24) 2Vdd

R2(4.6)

2Cext Vdd

It was found by experiment that when the Cext potentialreaches threshold (at Vdd/3), the inversion of the chargingvoltage of Cext is forced below ground due to chargecoupling. Therefore, the dV is not just Vdd/3 as expected andthe charging time must start at a point below ground whichaffects t and thus, Fo. An undershoot voltage must be addedto the equation for better accuracy in calculating t and Fo.This modifies Equation ( 7 ) as follows:

3VCOin(Iconstant ratio)

R1

9.2(Vdd)

R2

2Cext (Vdd 3 * undershoot)( 8 )

Fo 3VCOin

R1(24) 2Vdd

R2(4.6)

2Cext (Vdd 3 * undershoot)

Equation ( 8 ) now contains all the factors to calculate an Fofor the HC4046A VCO.

It was determined by experiment that the undershoot ofthe charging waveform is a function of Cext and an on–chipparasitic diode that clamps it at a maximum of –0.7V. Thesize of the Cext capacitor limits the voltage and was found tobe near zero volts for Cstray ≈17pF ≤ Cext ≤ 30pF; the voltageincreases at 6 mV/pF for a 30pF ≤ Cext ≤ 150pF range of Cext.The on–chip diode then takes over and limits the voltage to–0.7V.

It was also found that the Iconstant ratio is a function of R1and increases as R1 becomes larger. The change is attributedto saturation of the current mirror at lower value resistances,and to voltage divider problems at higher value resistancescombined with the resistance of the small FET in the currentmirror. Experimental data shows that Iconstant ratio followsTable 1 somewhat. The ratio goes to 25 somewhere between9.1KΩ and 51KΩ, and for those limits, 25 should givereasonable results. In addition, these numbers seem to holdfor a range of Vdd of 3.0V ≤ Vdd ≤ 6V.

1. Iconstant ratio versus R 1

R1 (KΩ) Iconstant ratio

3.05.19.11215304051110300

13.517.521.523.024.026.527.028.529.031.0

The VCO calculation [Equation ( 8 )] becomes a bit moreaccurate by adjusting the VCOin and Iconstant ratio. Forexample, with R1 = 300K, R2 = ∞, Cext = 0.1µF, VCOin =1.0V, Vdd = 4.5V, and Iconstant ratio = 31, Equation ( 8 ) yields:

Fo (3)(1)(31)

300K

2(0.1 * 10-6)(4.5 2.1)

235Hz

For comparison, from Chart 14D in the HC4046A datasheet, the Fo based on measurements is approximately 270Hz. Thus, the calculated and measured values are not too farapart taking into consideration such variables as processvariation, temperature, and breadboard inaccuracies. TheCstray of a PCB layout will affect results if the Cext is not Cstray. So for Cext ≤ 1000pF, adding Cstray to the Cext fixedcapacitance will result in better accuracy.

The gain of a VCO is calculated by knowing fmax atVCOin max and fmin at VCOinmin and calculating thefollowing equation:

( 9 )VCO gain f max f min

VCOin max VCOin min

freqvolt

The gain of the VCO is needed to calculate a suitable loopfilter for a PLL system.

Fo is determined by VCOin and is clamped as a functionof a % of Vdd. The clamp voltage generally follows the slopeof 4%/V for Vdd changes from 3.5V ≤ Vdd ≤ 6V, starting at56% at Vdd = 3.5V and going to 66% at Vdd = 6V. Knowingthis limit point allows picking a VCOin max point a fewhundred mV below it and keeps Fo in the linear range ofoperation. It also best to pick a VCOin min point at a levelof a few hundred mV above 0V for the same reason givenabove.

As an example, for a Cext =1100pF, R1 = 9.1K, R2 = ∞, Vdd=5.0V, and VCOin min = 0.25V, VCOin max can bedetermined and a gain calculated as follows. VCOin limit =(4%/V)(1.5V) + 56% = (62%)(Vdd ) = 3.1V. So, for sake oflinearity, choose VCOin = 2.5V. Using Equation ( 8 ), VCOinmin and VCOin max can be used to calculate Fo min and Fomax as follows:

AN1410/D


Fo min(3)(0.25)(21.5)

9.1K

2(1100 * 10-12)(5 2.1) 113.4KHz

Fo max (3)(2.5)(21.5)

9.1K

2(1100 * 10-12)(5 2.1) 1.3MHz

Then, using Equation ( 9 ), the VCO gain is:

VCO gain 1.3 * 106–0.11 * 1062.5–0.25

528.9KHzV

This gain factor will be known as Kvco in the loop filterequations.

R2 is used in applications where a minimum outputfrequency is desired when VCOin is 0V. It is calculated atVCOin = 0V causing Equation ( 8 ) to become:

Fo 9.2 (Vdd)

2C (R2) (Vdd 3 * undershoot)

The additional I2 current is a constant that adds to totalcharge current for Cext and increases the VCOin versus Focurve by a theoretical constant amount. In reality, theamount of increase actually decreases at a slight rate asVCOin increases. The decrease is slight and the use ofEquation ( 8 ) will give adequate accuracy for mostapplications.

The Fmax of the HC4046A VCO was determined to beabout 16MHz. Beyond 16MHz, the output logic swing tendsto reduce and is therefore somewhat useless for driving aCMOS input. The VCO will operate at ≈ 28MHz but theoutput has a VOL≈ 2.0V and a VOH≈ 4.5V at Vdd = 5.0V.

The following table was generated to make calculation ofR1 and Cext a function of Fo with Vdd = 5V, VCOin = 1V, androom temperature. Use of the table allows a rough estimateof (R1)(Cext) for a given Fo. The final values can be adjustedby use of Equation ( 8 ), Table 1 for Iconstant ratio, rules forundershoot voltage, Vdd variations, and VCOin variations.The example below shows a typical calculation.

2. (R1)(Cext ) versus F o

R1 (Ω) Cext (pF) (R1)(Cext )

3.0K ≤ R1 ≤ 9.0K 0 ≤ Cext ≤ 3030 ≤ Cext ≤ 150150 ≤ Cext ≤ ∞

5.40/Fo4.15/Fo3.80/Fo

9.1K ≤ R1 ≤ 50K 0 ≤ Cext ≤ 3030 ≤ Cext ≤ 150150 ≤ Cext ≤ ∞

7.50/Fo5.77/Fo5.28/Fo

50K ≤ R1 ≤ 900K 0 ≤ Cext ≤ 3030 ≤ Cext ≤ 150150 ≤ Cext ≤ ∞

9.00/Fo6.92/Fo6.34/Fo

Assume a desired value of Fo of 1MHz. From 2, choosean R1 range of 9.1K ≤ R1 ≤ 50K and a Cext range of > 150pF;this condition leads to (R1)(Cext) = 5.28/Fo. Thus,

(R1) (Cext) 5.28

1 * 106 5.28 * 10-6

Now choose a Cext of 200pF. Then, from above result,

R1 5.28 * 10-6

200 * 10-12 26K

This appears reasonable and there are standard values forCext = 200pF and R1 = 27K. Using these values, Equation (8 ) can be adjusted according to the desired Fo min, Fo max,and Fo center.

LOW PASS FILTER DESIGN

The design of low pass filters is well known and the intenthere is to simply show some typical examples. Referenceshould be made to the HC4046A Data Sheet and toApplication Note AN535/D — “Phase–Locked LoopFundamentals” (available through ON SemiconductorLiterature Distribution).

Some simple types of low pass filters are shown inFigure 2 and Figure 3.

Figure 2. Simple Low Pass Filter A

R1

C1

VCOin∅ det Charge Pump Output

R2

R1

C1

VCOin∅ det Charge Pump Output

Figure 3. Simple Low Pass Filter B

The equations for calculating loop natural frequency (wn)and damping factor (d) are as follows:

For Filter A (Figure 2):

wn KøKVCONC1R1

d 0.5wn

KøKVCO

where K∅ = phase detector gain, KVCO = VCO gain, and N =divide counter.

For Filter B (Figure 3):

( 10 )

wn KøKVCO

NC1(R1R2)

d 0.5wn(R2C1N

KøKVCO)

AN1410/D


Figure 4 shows an active filter using an op amp fromApplication Note AN535/D.

Figure 4. Op Amp Filter

R1

C1

VCOin∅ det ChargePump Output

OPAMP

R1

For Figure 4, the equations become:

wnKøKVCONC1R1

dKøKVCOR2

2wnNR1

wnC1R2

2, where Op Amp gain is large

( 11 )

( 12 )

From the above equations, it is possible to design asuitable filter to meet the needs of many PLL applications.The inclusion of R2 in the equations for Figure 3 andFigure 4 permits the capability to change wn and dseparately while Figure 2 equations do not. Normally, adesign is easier if wn and d can be chosen independently.Both factors affect the loop acquisition time and stability. Agood starting value for d is 0.707 and Fref/10 for wn.

Manipulation of the equations allows calculation of R1,R2, and C1 from the other measured, calculated, or pickedparameters. For example,

( 13 )R1 R2KøKVCONC1wn2

( 14 )R22d

C1wn N

C1(KøKVCO)

C1KøKVCO

Nwn2(R1R2), or alternatively,

C12d

R2wn N

R2(KøKVCO)

Usually, C1, wn, and d are picked and the remainingparameters calculated.

DESIGN EXAMPLE

The goal is to design a phase–locked loop that has an Frefof 100KHz, an output Fo of 1MHz center frequency, and theability to move from 200KHz to 2MHz in 100KHz steps.

Figure 5. Parametized PLL

Ref OscFref

∅ det (K∅ )

fo

Feedback

LP Filterwn

KVCO

÷N

To determine N, use equation (1) for Fo min = 200KHz,and Fo max = 2MHz resulting in the following:

N min = 200/100 = 2, and

N max = 2000/100 = 20

The results so far indicate the following starting parameters:A. A VCO with a 10:1 range is required

B. wn = Fref/10 = 10KHzC. d = 0.707

D. R2 = ∞E. Vdd = 5.0V

The Fo center frequency ≈

F max F min2

2.0 0.22

1.1MHz

Recalling that the clamp voltage % at Vdd = 5V is about62, then Fmax VCOin limit = (0.62)(5) = 3.1V, but asdescribed earlier, this needs to be reduced by a factor to bringit into linearity (≈ 350mV) so the final Fmax VCOin limit =2.75V.

For the Fmin VCOin limit pick 0.25V. This results in acenter frequency VCOin of:

Center freq VCOin2.75 0.25

2 1.25V

From 2, for picked values of 9.1K≤R1≤50K and 30≤Cext≤150, obtain an estimate for (R1)(Cext) of 5.77/Fo. Thus, atthe Fo center frequency,

(R1)(Cext)5.77

1.1 * 106 5.245 * 10-6

Now, a reasonable starting point is established for setting thevalues of the loop filter and the VCO range. Choosing R1 =9.1K, Cext becomes

Cext5.245 * 10-6

9.1K 576pF WHOOPS!

This value, 576pF, is outside of the original picked range forCext; therefore, we need to go back and pick a larger valueof R1, e.g., 42K should be sufficient. Then Cext becomes

Cext5.245 * 10-6

42K 125pF

and now both R1 and Cext are within selected ranges.

AN1410/D


Now calculate Fmax and Fmin using Equation ( 8 ) with R1= 42kΩ, R2 = , Vdd = 5.0V, Iconstant ratio = 27 (from 1. andR1 = 42kΩ), Vundershoot = 0.57V (calculated from 6pF/mV(125pF–30pF) = 0.57V), VCOin min = 0.25V, and VCOinmax = 2.75V:

Fo min(3)(0.25)(27)

42K (9.2) (5.0)

(2)(125 * 10-12f) [5.0V 3(0.57V)]

20.2570.455 * 10-6

287.4KHz

Fo max(3)(2.75)(27)

42K (9.2) (5.0)

(2)(125 * 10-12f) [5.0V 3(0.57V)]

222.7570.455 * 10-6

3.16MHz

0

0

Fmax is > the required 2.0MHz, but the Fmin is not lowenough for required application. It is necessary to adjusteither Cext or R1 to achieve required specification of 0.2 to2.0MHz Fo. Since R1 = 42kΩ is a standard resistor value, tryadjusting Cext to a higher value, such as 175pF. Because Cextis now > 150pF, the Vundershoot must be adjusted to 0.7V, asper earlier explanation:

So,

Fo min(3)(0.25)(27)

42K (9.2) (5.0)

(2)(175 * 10-12f) [5.0V 3(0.7V)]

20.25104.37 * 10-6

194.02KHz

0

and

Fo max(3)(2.75)(27)

42K (9.2) (5.0)

(2)(175 * 10-12f) [5.0V 3(0.7V)]

222.75104.37 * 10-6

2.13MHz

0

These values are adequate for the specified application.

The next item to determine is the VCO gain factor, KVCO,using Equation ( 9 ):

KVCOf max f min

VCOin max VCOin min

KVCO2.13 * 106 0.194 * 106

2.75V 0.25V 774.4KHzV

(2) (774.4 * 103) 4.86 * 106RadsecV

or in radians

The final values used for the desired frequency range areR1 = 42kΩ, Cext = 175pF, R2 = , VCOin max = 2.75V, andVCOin min = 0.25V.

The next step is to determine the loop filter. Choosing afilter like the one in Figure 3, calculate the component asfollows:

KøVdd4 5.0

4 0.4Vrad

wn100KHz

10 10KHz * 2 62.83 * 103radsec

d = 0.707 (for starters), and

N = 2 to 20

whereK∅ = phase detector gain

Vdd = output swing

Choose C1 to be 0.01µF, N = 10 for approximatemid–range Fo, and calculate R1 and R2 using Equations ( 13) and ( 14 ):

R1 R2KøKVCONC1wn2

(0.4)(4.86 * 106)

(10)(0.01 * 10-6)(62.83 * 103)2

1.944 * 106

394.76 4924.5

R22d

C1wn N

C1(KøKVCO)

2250.52–514.4 1736

(2)(0.707)

(0.01 * 10-6) (62830)– 10

(0.01 * 10-6)(0.4)(4.86 * 106)

Then, R1 = 4924.5 – 1736 = 3188.5Ω.

Since N is changeable, it is a good idea to check min andmax on wn and d. For more information on why, seeApplication Note AN535/D or the MC4044 Data Sheet inthe MECL Data Book DL122/D. The following examplesshow sample calculations for N = 2 and 20.

For N = 20, use Equation ( 10 ) to calculate wn and d:

wn min KøKVCONC1(R1 R2)

44.43 * 103radsec, or

(0.4)(4.86 * 106)

(20)(0.01 * 10-6)(3188.5 1736)

44.43 * 103radsec

2 7KHz

AN1410/D


and

(1736)(0.01 * 10-6) 20(0.4)(4.86 * 106)

d min (0.5)(wn) R2C1 N

KøKVCO

0.6144

(0.5)(44.43 * 103) *

For N = 2:

wn max (0.4)(4.86 * 106)

(2)(0.01 * 10-6)(3188.5 1736)

140.49 * 103radsec, or

140.49 * 103radsec

2 22.36KHz

and

(1736)(0.01 * 10-6) 2(0.4)(4.86 * 106)

1.292

d max (0.5)(140.49 * 103) *

This shows the effect of changing n on loop performance andfor this application is adequate.

If the components are not what is desired, choosing adifferent wn and/or d allows them to be modified.

Alternatively, picking different C, R1 or R2 andrecalculating the other parameters can be done. If the filterdoes not provide adequate performance, making wn smalleror d larger may improve stability.


February, 2000 – Rev. 1388 Publication Order Number:

AN1558/D

" !

Prepared by: Douglas M. Buzard, Rodolfo E. Soto

IntroductionThe MC74HC4538A is a monostable multivibrator

commonly used as a one–shot, or in applications that requirea pulse width of reliable dimensions. The pulse width andthe minimum retrigger time are usually well behaved overthe suggested pulse–width range of 1µs to 1 second.However, some customers have found that in using shorterthan recommended pulse widths the retrigger time did notbehave as it had at longer pulse widths. ON Semiconductorhas done an overall characterization of the minimumretrigger time in an investigation of this phenomenon.

The retrigger time is applicable when the device istriggered a second time within the period of the output pulse.When this happens, the output pulse remains high for aperiod of τ + Trr. The earliest the part can be retriggered, orthe minimum retrigger time, is the focus of thischaracterization. A trigger pulse on A or B inputs before thisminimum retrigger time would be ignored.

Analysis and DataWhen used in the retriggerable mode (Figure 1), the

MC74HC4538A uses an external Rx & Cx to regulate theoutput pulse width, and the minimum retrigger time (Trr). The minimum retrigger time depends on:

1) Time to discharge RxCx from VCC to (Vref lower=1/3VCC) Tdischarge. This discharge occurs quicklybecause external resistance, Rx, does not have anyeffect on the RC time constant. The resistance in thedischarge path, as seen in Figure 2, is theon–resistance of M3, and the interconnect resistance.The interconnection resistance is dependent on thepolysilicon sheet resistance, the metal sheet

resistance, and the contact resistance. Theinterconnection resistance is heavily processdependent, but fortunately it is small overall anddoesn’t vary significantly from lot to lot. The discharge time can be computed from:

Tdischarge Ln 32 RiCx

(Equation 1)

Typically the value of Ri would be near 300Ω.

2) Loop delay (Tdelay = constant) ranges from 20–60ns,and is strongly correlated to VCC. This is the time forthe signal coming from the lower reference circuit toreset the flip–flop, and turn off M3. The amount ofthe undershoot voltage is a function of the loop delay,and for small values of capacitance the undershootvoltage is well below the lower reference voltage.

3) The time to charge RxCx from the undershoot voltageback to the lower reference voltage (Vref lower). Thistime is given by the RxCx transient equation:

Tcharge RxCx Ln 1 3 Vundershoot2 VCC

(Equation 2)

where Vundershoot = (Vref lower) – Gnd. Hence theretrigger time is given by:

(Equation 3)

Trr = Tdischarge + Tdelay + Tcharge

http://onsemi.com

APPLICATION NOTE

AN1558/D


Figure 1. Retriggerable Monostable Circuitry

A = GND

RESET = VCC


CX

VCC

Q

QB

RX

RESET = VCC


B = VCC

CX

VCC

Q

Q

A

B

RX

Figure 2. MC74HC4538A Logic Circuit Detail

+–

+–

RxCx

VCC

M1

2 kΩ

M3

M2

A

B

RESET

POWERON

RESETRESET LATCH

TRIGGER CONTROLRESET CIRCUIT

TRIGGER CONTROLCIRCUIT

OUTPUTLATCH

UPPERREFERENCE

CIRCUIT

Vref UPPER

LOWERREFERENCE

CIRCUIT

Vref LOWER

Q

Q

C

CB

Q

R

VCC

LOGIC DETAIL(1/2 THE DEVICE)

AN1558/D


QUIESCENTSTATE

TRIGGER CYCLE(A INPUT)

TRIGGER CYCLE(B INPUT) RESET RETRIGGER

trr

TRIGGER INPUT A(PIN 4 OR 12)

TRIGGER INPUT B(PIN 5 OR 11)

TRIGGER-CONTROLCIRCUIT OUTPUT

RX/CX INPUT(PIN 2 OR 14)

UPPER REFERENCECIRCUIT

LOWER REFERENCECIRCUIT

RESET INPUT(PIN 3 OR 13)

RESET LATCH

Q OUTPUT(PIN 6 OR 10)

τ τ + trrτ


Design and ApplicationsThe output pulse width of the HC4538A is determined by

the external timing components, Rx and Cx, and can berepresented linearly as shown in Figure 10.

The array in Table 1 was generated to make a concisestudy of the behavior for the retrigger time for short pulsewidths. A sample of 10 pieces from each of 7 non–consec–utive wafer lots were tested at each condition.

The retrigger time for external capacitance that rangesfrom 3000pF < Cx < 4.7µF, Region 3 on the graphs, can becomputed by making use of the following linear equation(Equation 4).

Table 1. Test Matrix

Cx/Rx 10pF 100pF 220pF 1000pF

2KΩ 4.5V 4.5V 4.5V 4.5V

10KΩ 3.0V4.5V

3.0V4.5V

3.0V4.5V

3.0V4.5V

100KΩ 3.0V4.5V

3.0V4.5V

3.0V4.5V

3.0V4.5V

1MΩ 3.0V4.5V

3.0V4.5V

3.0V4.5V

3.0V4.5V

Equation 4. Retrigger Time for 4.7µF > Cx > 3000pF

where z –1062.41 – (0.1236764 VCC) (1.13509292 (Log Cx)3 ) – (2.875 10–17 Rx3 )

Trr = 10z,

(3.5256 1016 (Log Cx)2 Rx) (5.9621 1012 (Log Cx) Rx2 ) (4.03306325 (Log Cx)2 )

(7.9452 1011Rx2 ) (5.1513 105 (Log Cx) Rx) (0.02312176 Log Rx)

(1.8339 104 Rx) (171.91718 Log Cx) (4.64784302 108 Cx)

AN1558/D


1.0pF 10pF 100pF 1000pF 0.01µF 0.1µF 1.0µF 10µF 100µF

Cx (Farad)

0.01µs

0.1µs

1.0µs

10µs

100µs

1.0ms

T rr(

sec)

1MΩ

100kΩ

10KΩ

2KΩ

Figure 4. Retrigger Time versus Timing Capacitance at V CC = 4.5V

Region 1 Region 2 Region 3

Figure 5. Retrigger Time versus Timing Capacitance at V CC = 3.0V

1.0pF 10pF 100pF 1000pF 0.01µF 0.1µF 1.0µF 10µFCx (Farad)

0.1µs

1.0µs

10µs

100µs

1.0ms

T rr(

sec)

1MΩ

100kΩ

10KΩRegion 1

Region 2Region 3

For values of 1000pF < Cx < 3000pF, the non–linearportion of the curves are converging. In this region, Region2, the equation was represented by too few measurements togenerate a reasonably accurate equation. Therefore, theequation in Region 2 will remain underived. A value may beapproximated from the graphs in Figure 4 and Figure 5.

It was determined from experiment and statistical analysisof the data that the retrigger time for small values of externalcapacitance within the range of 10pF < Cx < 1000pF, Region1, can be characterized with the following linear equation(Equation 5).

AN1558/D


where z –315.29624–(0.082881 VCC)–(0.3146338 (Log Cx)3 ) 4.3277 10–16Rx3 )–

Equation 5. Retrigger Time for 10pF < Cx < 1000pF

Trr = 10z,

(3.984 107 (Log Cx)2Rx) (3.0657 1012 (Log Cx) Rx2 ) (9.467093 (Log Cx)2 )

(4.575 1010 Rx2 ) (1.124 105 (Log Cx)Rx) (94.092747 Log Cx)

(1.36599588 108 Cx) (1.423 105Rx)

Here, the same components of:

(Equation 3)

Trr = Tdischarge + Tdelay + Tcharge

are still represented, but have become combined by thelinear regression. The constant and VCC dependent term stillderive from the loop delay, and serve to shift the componentsalong the vertical axis. The major difference between thisand the larger values of Cx is twofold.

First, over all of Region 3 the undershoot is effectively 0volts. This results in Tcharge not contributing to Trr and thepredictable minimum Trr occurring in Region 2.

Second, as we progress to smaller values of capacitancein Region 1, Cx is too small to support Vreflower as thecharge is drained through M3. This is why the resistance ofRx now plays a role in Trr. This condition creates theundershoot of Vreflower and the time of Tcharge is thencontrolled by the current through Rx. This is also why as the

value of Cx increases for the same resistance, Trr increasesas it takes longer to charge the larger capacitor. For valuesof Rx > 10kΩ, this increasing undershoot of Vreflower andthe resultant increase in Tcharge negates any improvement inTrr.

At small values of Cx, the circuit capacitance will alsocome into play. The size of the undershoot of Vreflower canvary as a function of normal process variance. This will alsointroduce an uncertainty into Trr for these smaller values.The curves and regression equations here were derivedstatistically and only represent the mean of the variance in7 non–consecutive production lots.

This difference in the non–zero value of Tcharge in Region1 can also be seen in Figure 6 and Figure 7 as the slope of Trrbecomes zero as the undershoot becomes zero.

Also, note that in Figure 8 through Figure 11, this effecthas no influence on the Output Pulse Width as the PulseWidth is controlled by RxCx and Vrefupper.

where z –1.0059363–(7.6336 10–3 VCC) (0.87653815 Log Rx)

Equation 6. Pulse Width

τ = 10z,

(0.8635535 Log Cx) (9.3203 103 Log Rx Log Cx)

Equation 6 is a linear regression equation for calculatingthe pulse width and is also made from the data means. Fromthe logarithmic plots in Figure 8 through Figure 11, it can beseen that there is no cubic dependency similar to Trr, even atthe small values of capacitance. The pulse width iscompletely controlled by the relationship between RxCx andVrefupper. This predictability of the pulse width has temptedsome customers into trying to use the part for very shortpulse widths. Unfortunately it has also resulted ininconsistent performance for Trr.

SummaryWhile smaller pulse widths and Trr values can be

achieved, selection of the external components must takeinto account the introduction of undershoot of Vreflower.

Also, as we have stated above, as the value of Cx decreasesin the non–linear region, the total capacitance becomes moredependent upon internal circuit capacitance. Since theinternal circuit capacitance is process dependent, it can varyfrom lot to lot, and from manufacturing site tomanufacturing site. It is for this reason that the device is notrecommended to be used in this range, as doing so wouldpotentially result in inconsistent performance over largeproduction runs. The curves represented in this applicationsnote were made using linear regression on a number of lotswidely separated in time, but all from the samemanufacturing site. As a result, the curves can only beregarded as statistical means, and may not represent theperformance of any particular device the customer mayencounter.

AN1558/D


Figure 6. Retrigger Time vs Resistance at V CC = 4.5V

Figure 7. Retrigger Time vs Resistance at V CC = 3.0V

1.0E+06

1.0E–05

1.0E–06

1.0E–07

1.0E–08

1.0E–04

1.0E+03 1.0E+04

T

RESISTANCE (Ω)

10pF

100pF

200pF

1000pF

0.01µF

0.1µF

1.0E+05

rr(s

ec)

1.0E+06

1.0E–04

1.0E–05

1.0E–06

1.0E–07

1.0E–03

1.0E+04 1.0E+05

T

RESISTANCE (Ω)

10pF

100pF

200pF1000pF

0.01µF

rr(s

ec)

0.1µF

AN1558/D


Figure 8. Pulse Width vs Timing Capacitance at V CC = 4.5V

Figure 9. Pulse Width vs Timing Capacitance at V CC = 3.0V

1.0E–07

1.0E–03

1.0E–04

1.0E–05

1.0E–06

1.0E–07

1.0E–02

1.0E–11 1.0E–10

PULS

E W

IDTH

(sec

)

Cx (Farads)

1MΩ

100kΩ

10kΩ

2kΩ

1.0E–09 1.0E–08

1.0E–07

1.0E–03

1.0E–04

1.0E–05

1.0E–06

1.0E–07

1.0E–02

1.0E–11 1.0E–10

PULS

E W

IDTH

(sec

)

Cx (Farads)

1MΩ

100kΩ

10kΩ

1.0E–09 1.0E–08

Figure 10. Output Pulse Width vs Timing Capacitance

10s

1s

100ms

10ms

1ms

100µs

10µs

1µs

100ns0.00001 0.0001 0.001 0.01 0.1 1 10 100

CAPACITANCE (µF)

OU

TPU

T PU

LSE

WID

TH (

)τ

VCC = 5 V, TA = 25°C

1 MΩ

100 kΩ

10 kΩ

1 kΩ

AN1558/D


1.0E+06

Figure 11. Pulse Width versus Resistance at V CC = 3.0V

1.0E–03

1.0E–04

1.0E–05

1.0E–06

1.0E–07

1.0E–02

1.0E+04 1.0E+05

PULS

E W

IDTH

(sec

)

RESISTANCE (Ω)

10pF

100pF

200pF

1000pF

0.01µF0.1µF

Figure 12. Pulse Width versus Resistance at V CC = 4.5V

1.0E+06

1.0E–03

1.0E–04

1.0E–05

1.0E–06

1.0E–07

1.0E–02

1.0E+03 1.0E+04

PULS

E W

IDTH

(sec

)

RESISTANCE (Ω)

1.0E+05

10pF

100pF

200pF

1000pF

0.01µF

0.1µF



CHAPTER 5Case Outlines and Ordering Information

Device Nomenclature 398. . . . . . . . . . . . . . . . . . . . . . . Case Outlines 398. . . . . . . . . . . . . . . . . . . . . . . . . . . . ON Semiconductor Distributor and WorldwideSales Offices 405. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Definitions 406. . . . . . . . . . . . . . . . . . . . . .


High–Speed CMOS FamilyDevice Nomenclature

ON SemiconductorCircuit Identifier

Temperature Range• 74 Series (–55 to +125°C)

High–Speed CMOSSpecification Identifier

• HC = Buffered High–Speed CMOS• HCU = Unbuffered High–Speed CMOS*• HCT = High–Speed CMOS TTL Compatible

*Not Available On All Devices

Package Type• D for 150 mil Plastic SOIC• DT for TSSOP• DW for 300 mil Plastic SOIC• F for 200 mil EIAJ SOIC• N for Plastic PDIP

Function Type• XX(X) Same Function and Pin Configuration

as LSTTL• 4XXX Same Function and Pin Configuration

as CMOS 14000• 7XX(X) Variation of LSTTL or CMOS 14000

Device

MC VV WWW XXXX Y

PDIP–14N SUFFIX

PLASTIC DIP PACKAGECASE 646–06

ISSUE M

1 7

14 8

B

A DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.715 0.770 18.16 18.80B 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53F 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43LM ––– 10 ––– 10 N 0.015 0.039 0.38 1.01

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

F

H G DK

C

SEATINGPLANE

N

–T–

14 PL

M0.13 (0.005)

L

MJ

0.290 0.310 7.37 7.87


SO–14D SUFFIX

PLASTIC SOIC PACKAGECASE 751A–03

ISSUE F

MIN MINMAX MAXMILLIMETERS INCHES

DIMABCDFGJKMPR

8.553.801.350.350.40

0.190.10

0° 5.800.25

8.754.001.750.491.25

0.250.25

7°6.200.50

0.3370.1500.0540.0140.016

0.0080.004

0° 0.2280.010

0.3440.1570.0680.0190.049

0.0090.009

7° 0.2440.019

1.27 BSC 0.050 BSC


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

–A–

–B– P 7 PL

GC

KSEATINGPLANE

D 14 PL M J

R X 45°

1 7

814

0.25 (0.010) T B AM S S

B0.25 (0.010) M M

F

TSSOP–14DT SUFFIX

PLASTIC TSSOP PACKAGECASE 948G–01

ISSUE O

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C ––– 1.20 ––– 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.50 0.60 0.020 0.024J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASHOR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE –W–.

SU0.15 (0.006) T

2X L/2

SUM0.10 (0.004) V ST

L–U–

SEATINGPLANE

0.10 (0.004)–T–

ÇÇÇÇ

SECTION N–N

DETAIL E

J J1

K

K1

ÉÉÉÉ

DETAIL E

F

M

–W–

0.25 (0.010)814

71

PIN 1IDENT.

HG

A

D

C

B

SU0.15 (0.006) T

–V–

14X REFK

N

N


SO–14 EIAJF SUFFIX

PLASTIC EIAJ SOIC PACKAGECASE 965–01

ISSUE O

HE

A1

DIM MIN MAX MIN MAXINCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.0080.35 0.50 0.014 0.0200.18 0.27 0.007 0.0119.90 10.50 0.390 0.4135.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC7.40 8.20 0.291 0.3230.50 0.85 0.020 0.0331.10 1.50 0.043 0.0590

0.70 0.90 0.028 0.035––– 1.42 ––– 0.056

A1

HE

Q1

LE 10

0 10

LEQ1


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.


5. THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).

0.13 (0.005) M 0.10 (0.004)

DZ

E

1

14 8

7

e A

b

VIEW P

c

L

DETAIL P

M

A

bcDEe

0.50

M

Z

PDIP–16N SUFFIX


ISSUE R


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

–A–

B

F C

S

HG

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE–T–

MAM0.25 (0.010) T

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.740 0.770 18.80 19.55B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.021 0.39 0.53F 0.040 0.70 1.02 1.77G 0.100 BSC 2.54 BSCH 0.050 BSC 1.27 BSCJ 0.008 0.015 0.21 0.38K 0.110 0.130 2.80 3.30L 0.295 0.305 7.50 7.74M 0 10 0 10 S 0.020 0.040 0.51 1.01


SO–16D SUFFIX

PLASTIC SOIC PACKAGECASE 751B–05

ISSUE J

0.25 (0.010) T B AM S S

MIN MINMAX MAXMILLIMETERS INCHES

DIMABCDFGJKMPR

9.803.801.350.350.40

0.190.10

0°5.800.25

10.004.001.750.491.25

0.250.25

7° 6.200.50

0.3860.1500.0540.0140.016

0.0080.004

0° 0.2290.010

0.3930.1570.0680.0190.049

0.0090.009

7° 0.2440.019

1.27 BSC 0.050 BSC


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

1 8

916

–A–

–B–

D 16 PL

K

C

G

–T–SEATING

PLANE

R X 45°

M J

F

P 8 PL

0.25 (0.010) BM M

SO–16 WIDEDW SUFFIX

PLASTIC SOIC PACKAGECASE 751G–03

ISSUE B

D

14X

B16X

SEATINGPLANE

SAM0.25 B ST

16 9

81

hX

45

MB

M0.

25

H8X

E

B

A

eTA

1

A

L

C

NOTES:1. DIMENSIONS ARE IN MILLIMETERS.2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 TOTAL IN EXCESSOF THE B DIMENSION AT MAXIMUM MATERIALCONDITION.

DIM MIN MAXMILLIMETERS

A 2.35 2.65A1 0.10 0.25B 0.35 0.49C 0.23 0.32D 10.15 10.45E 7.40 7.60e 1.27 BSCH 10.05 10.55h 0.25 0.75L 0.50 0.90 0 7


TSSOP–16DT SUFFIX

PLASTIC TSSOP PACKAGECASE 948F–01

ISSUE O

ÇÇÇÇÇÇÇÇÇ

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C ––– 1.20 ––– 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.18 0.28 0.007 0.011J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.


4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.




SECTION N–N

SEATINGPLANE

IDENT.PIN 1

1 8

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

HG

ÉÉÉÉ

DETAIL E

F

M

L

2X L/2

–U–

SU0.15 (0.006) T

SU0.15 (0.006) T

SUM0.10 (0.004) V ST

0.10 (0.004)–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

HE

A1


––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.0080.35 0.50 0.014 0.0200.18 0.27 0.007 0.0119.90 10.50 0.390 0.4135.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC7.40 8.20 0.291 0.3230.50 0.85 0.020 0.0331.10 1.50 0.043 0.0590

0.70 0.90 0.028 0.035––– 0.78 ––– 0.031

A1

HE

Q1

LE 10

0 10

LEQ1






M

L

DETAIL P

VIEW P

cA

b

e

M0.13 (0.005) 0.10 (0.004)

1

16 9

8

DZ

E

A

bcDEe

L

M

Z



ISSUE O


PDIP–20N SUFFIX


ISSUE E

1.0700.2600.1800.022

0.070

0.0150.140

15° 0.040

1.0100.2400.1500.015

0.050

0.0080.110

0° 0.020

25.666.103.810.39

1.27

0.212.80

0° 0.51

27.176.604.570.55

1.77

0.383.55

15°1.01

0.050 BSC

0.100 BSC

0.300 BSC

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAXINCHES MILLIMETERS

DIMABCDEFGJKLMN


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

-A-

C

K

NE

G F

D 20 PL

J 20 PL

L

M

-T-SEATINGPLANE

1 10

1120

0.25 (0.010) T AM M

0.25 (0.010) T BM M

B

SO–20 WIDEDW SUFFIX

PLASTIC SOIC PACKAGECASE 751D–05

ISSUE F

20

1

11

10

B20X

H10

X

C

L

18X A1

A

SEATINGPLANE

hX

45

E

D

M0.

25M

B

M0.25 SA SBT

eT

B

A

DIM MIN MAXMILLIMETERS

A 2.35 2.65A1 0.10 0.25B 0.35 0.49C 0.23 0.32D 12.65 12.95E 7.40 7.60e 1.27 BSCH 10.05 10.55h 0.25 0.75L 0.50 0.90 0 7

NOTES:1. DIMENSIONS ARE IN MILLIMETERS.2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALLBE 0.13 TOTAL IN EXCESS OF B DIMENSION ATMAXIMUM MATERIAL CONDITION.


TSSOP–20DT SUFFIX

PLASTIC TSSOP PACKAGECASE 948E–02

ISSUE A

DIMA

MIN MAX MIN MAXINCHES

6.60 0.260

MILLIMETERS

B 4.30 4.50 0.169 0.177C 1.20 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.27 0.37 0.011 0.015J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,


4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED 0.25 (0.010)PER SIDE.




ÍÍÍÍÍÍÍÍÍÍÍÍ

1 10

1120

PIN 1IDENT

A

B

–T–0.100 (0.004)

C

D GH

SECTION N–N

KK1

J J1

N

N

M

F

–W–

SEATINGPLANE

–V–

–U–

SUM0.10 (0.004) V ST

20X REFK

L

L/22X

SU0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

––– –––

SU0.15 (0.006) T



ISSUE O


––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.0080.35 0.50 0.014 0.0200.18 0.27 0.007 0.011

12.35 12.80 0.486 0.5045.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC7.40 8.20 0.291 0.3230.50 0.85 0.020 0.0331.10 1.50 0.043 0.0590

0.70 0.90 0.028 0.035––– 0.81 ––– 0.032

A1

HE

Q1

LE 10

0 10






HE

A1

LEQ1

cA

ZD

E

20

1 10

11

b

M0.13 (0.005)

e

0.10 (0.004)

VIEW P

DETAIL P

M

L

A

bcDEe

L

M

Z

http://onsemi.com 405

ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICESUNITED STATES

ALABAMAHuntsville (256)464–6800. . . . . . . . . . . . . . . . . .

CALIFORNIAIrvine (949)753–7360. . . . . . . . . . . . . . . . . . . . . . San Jose (408)749–0510. . . . . . . . . . . . . . . . . .

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http://onsemi.com 406

ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS

REFERENCE MANUAL

A Reference Manual is a publication that contains a comprehensive system or device–specific description of the structure and function(operation) of a particular part/system; used overwhelmingly to describe the functionality of a microprocessor, microcontroller, or someother sub–micron sized device. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).

USER’S GUIDE

A User’s Guide contains procedural, task–oriented instructions for using or running a device or product. A User’s Guide differs froma Reference Manual in the following respects:* Majority of information (> 60%) is procedural, not functional, in nature* Volume of information is typically less than for Reference Manuals* Usually written more in active voice, using second–person singular (you) than is found in Reference Manuals* May contain photographs and detailed line drawings rather than simple illustrations that are often found in Reference Manuals

POCKET GUIDE

A Pocket Guide is a pocket–sized document that contains technical reference information. Types of information commonly found inpocket guides include block diagrams, pinouts, alphabetized instruction set, alphabetized registers, alphabetized third–party vendors andtheir products, etc.

ADDENDUM

A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in theprimary publication it supports. Individual addendum items are published cumulatively. Addendums end with the next revision of theprimary document.

APPLICATION NOTE

An Application Note is a document that contains real–world application information about how a specific ON Semiconductordevice/product is used with other ON Semiconductor or vendor parts/software to address a particular technical issue. Parts and/or softwaremust already exist and be available.

A document called “Application–Specific Information” is not the same as an Application Note.

SELECTOR GUIDE

A Selector Guide is a tri–fold (or larger) document published on a regular basis (usually quarterly) by many, if not all, divisions, thatcontains key line–item, device–specific information for particular product families. Some Selector Guides are published in book formatand contain previously published information.

PRODUCT PREVIEW

A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The ProductPreview exists only until an “Advance Information” document is published that replaces it. The Product Preview is often used as the firstsection or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer at the bottom of the firstpage: “ON Semiconductor reserves the right to change or discontinue this product without notice.”

ADVANCE INFORMATION

The Advance Information document is for a device that is NOT fully MC–qualified. The Advance Information document is replacedwith the Technical Data document once the device/part becomes fully MC–qualified. The Advance Information document displays thefollowing disclaimer at the bottom of the first page: “This document contains information on a new product. Specifications and informationherein are subject to change without notice.”

TECHNICAL DATA

The Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces the Advance Informationdocument and represents a part that is M, X, XC, or MC qualified. The Technical Data document is virtually the same document as theProduct Preview and the Advance Information document with the exception that it provides information that is unavailable for a productin the early phases of development (such as complete parametric characterization data). The Technical Data document is also a morecomprehensive document that either of its earlier incarnations. This document displays no disclaimer, and while it may be informallyreferred to as a “data sheet,” it is not labeled as such.

ENGINEERING BULLETIN

An Engineering Bulletin is a writeup that typically focuses on a single specific solution for a particular engineering or programming issueinvolving one or several devices.

DL129/DRev. 7, Mar-2000

ON Semiconductor

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DL129/D