High Speed Digital Signal Path Design for a 40 Gb /s Optical Receiver

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-cadIX

Karsten Drögemü[email protected]

ixpanding bandwidth

European ADS User’s Group MeetingBoeblingen, May 14-15 2009

High Speed Digital Signal Path Design for a 40 Gb/s Optical Receiver

1KD 04/22/2023

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-cadIXixpanding bandwidth

Contents

2

Trends in Fiber Optics Optical Receiver Modul with 4x 10Gb/s High Speed Signal Path

• Transimpedance Amplifier (TIA) Output stage• IC Bondwire• Package Feedthrough• Flex Foil Circuit• Test board interconnection & Test Board

RF Path in Frequency Domain RF Path in Time Domain Measurement Data: Eye diagram & TDR Conclusion

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3

Trends in Fiber Optics

Standardization Activities

IEEE HSSG 10G 40 G 100 G

QSFP – MSA 4x 5 G; 4 x 8 G; 4 x10 G

USB 3.0 5G

XMD – MSA ROSA/TOSA up to 10 G

XLMD –MS ROSA/TOSA up to 40 G Active Optical Cable 12 x 10G

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4

Trends in Fiber Optics

100 G and 40 G Form Factors for Transceivers

4x10Gb/s

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5

Optical Receiver Module with 4x 10Gb/s

Fiber

Flex FoilPackage

www.cubeoptics.com

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6

High Speed Signal Path

RX ModuleBottom side up

Flex foil

Test BoardSMD Connector

Flex foil – Test Board transition

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7

High Speed Signal Path

Signal path divided in section to create models

50O

hm50

Ohm

Testboard

Flex toTest Boardtransition

Flex foilcircuit

Package toFlex Foiltransition

Bond wire

V0 Vpkg Vflex Vtb Vout

TIA outputstage

Vtia Vbw

RF in RF out

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8

TIA Output Stage: Linear Circuit Model

Vcc

Vcc

V_DCSRC3Vdc=3.3 V

PortP1Num=1

PortP2Num=2

Term_DiffTerm_Diff1Load=100 Ohm

Tx_DiffTx_Diff1

ExcludeLoad=yesMode=Maximal Length LFSRRiseFallTime=35 psecVlow=-140 VVhigh=140 mVBitRate=10 Gbps

Tx

ChannelSimChannelSim1

EnforcePassivity=yesToleranceMode=AutoNumberOfBits=1000

ChannelSim

EyeDiff_ProbeEyeDiff_Probe1

V+

V-

ONET8501T_transistorQ1

ONET8501T_transistorQ2

RR1R=50 Ohm

I_DCSRC1Idc=3 mA

I_DCSRC2Idc=3 mA

RR3R=22 Ohm

RR2R=50 Ohm

linear transistor model

Channelsimulationsource

TIA Chip

CML output stage

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9

Bond Wire Model: 3D EM Simulation Model

TIA

Bond wire

Glass

Metal pin(differential feedthrough)

S-Parameter extractedfrom EM simulation 3D Model

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10

Package Feedthrough: 3D EM Simulation

S-Parameter extractedfrom EM simulation

Metal base

Flex foil circuit

Metal Pins

Glass

Mag (SDD11)

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11

Flex Foil Circuit: 2.5D EM Simulation Model

Flex foil circuit layout in ADS one RF path copied and simulated in Momentum

Polyimide: 50um, Cu T=36um, 50um Cover layerCoupled microstrip: w=70um, s=250um, Zdiff=100

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12

Test Board Interconnection

Layout in Allegro PCB

RF critical section copied to Momentum (use Utility)

Momentum 3D viewTest board

Flex circuit on top

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13

Test Board: ADS Line Models

differential lineMicrostrip lineline splitter(*)

(*) Line splitter modelcreated with Momentum

Vtb1

Vtb2

Vflex1Vflex2

TOflex_hfss40G! Port[1] = WavePort1:T1 flex side! Port[2] = WavePort1:T2 flex side! Port[3] = WavePort2:T1 glass side! Port[4] = WavePort2:T2 glass side

TIA9_TO40G! Terminal data exported! Port[1] = LumpPort4:T1 IC side to WP1 T1! Port[2] = LumpPort9:T1 IC side to WP1 T2! Port[3] = WavePort1:T1 glass side! Port[4] = WavePort1:T2 glass side

S4PSNP4File="Mom_RFflexRFthickHCMRloss60G_mom_a.ds"

4

1 2

3 Ref

MSUBRO4350

Rough=1.4 umTanD=0.005T=43 umHu=1.0e+033 mmCond=5.7E+7Mur=1Er=3.5H=0.17 mm

MSub

MLINTL1

L=24 mmW=0.35 mmSubst="RO4350"

MLINTL2


Gabel_CMSLtoSE_MSLX2

2

4

1

3

MCLINCLin3

L=63 mmS=0.4 mmW=0.32 mmSubst="RO4350"

S4PSNP5File="ROSA410testbrd_1V0_final_start3small_MWthickHCMR40Gmom_a.ds"

4

1 2

3 Ref

TermTerm2

Z=50 OhmNum=2

TermTerm4

Z=50 OhmNum=4

TermTerm1

Z=50 OhmNum=1

S4PSNP3File="TOflex_hfss40G.s4p"

4

12

3Ref

TermTerm3

Z=50 OhmNum=3

S4PSNP2File="TIA9_TO40G.s4p"

4

1 2

3 Ref

S_ParamSP1

Step=0.1 GHzStop=40.0 GHzStart=1.0 GHz

S-PARAMETERS

PCB cut view

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14

RF Path in Frequency Domain



Vflex1

Vflex2

Vtb1

Vtb2MLINTL1


MLINTL2



2

4

1

3

MCLINCLin3


MSUBRO4350


MSub


4

1 2

3 Ref

S4PSNP4File="Mom_RFflexRFthickHCMRlossNi40G_mom_a.ds"

4

1 2

3 Ref


4

12

3Ref

TermTerm3

Z=50 OhmNum=3

TermTerm4

Z=50 OhmNum=4


4

1 2

3 Ref

TermTerm1

Z=50 OhmNum=1

TermTerm2

Z=50 OhmNum=2

S_ParamSP1

Step=0.1 GHzStop=40.0 GHzStart=1.0 GHz

S-PARAMETERS

Simulation set up in ADS

TIA Output stage omitted

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15

RF Path in Frequency Domain

5 10 15 20 25 30 350 40

-20

-15

-10

-5

-25

0

freq, GHz

dB(S

DD21

)

Readout

m2

db(S

DD12

)m2freq=dB(SDD21)=-5.300

10.00GHz

Vout

5 10 15 20 25 30 350 40

-16

-14

-12

-10

-8

-6

-4

-2

-18

0

freq, GHz

dB(S

DD21

)

Readout

m2

db(S

DD12

)

m2freq=dB(SDD21)=-3.491

10.00GHz

Vtb

5 10 15 20 25 30 350 40

-10

-8

-6

-4

-2

-12

0

freq, GHz

dB(S

DD21

)

Readout

m2

db(S

DD12

)


10.00GHz

Vflex

5 10 15 20 25 30 350 40

-8

-7

-6

-5

-4

-3

-2

-1

-9

0

freq, GHz

dB(S

DD21

)

Readout

m2

db(S

DD12

)


10.00GHz

Vpkg

5 10 15 20 25 30 350 40

-5

-4

-3

-2

-1

-6

0

freq, GHz

dB(S

DD21

)

Readout

m2

db(S

DD12

)


10.00GHz

Vbw

50O

hm50

Ohm

Testboard


Flex foilcircuit


Bond wire

RF in


TIA outputstage

Vtia Vbw

RF out

each section ideal terminated

+1.2dBloss

+1.8dBloss

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16

RF Path in Time Domain

Vtb1

Vtb2

Vflex1

Vflex2



MCLINCLin3



2

4

1

3

MLINTL2


MLINTL1



4

1 2

3 Ref

S4PSNP4File="Mom_RFflexRFthickHCMRlossNi40G_mom_a.ds"

4

1 2

3 Ref


4

12

3Ref


4

1 2

3 Ref

ChannelSimChannelSim2

EnforcePassivity=yesToleranceMode=AutoNumberOfBits=500

ChannelSim

EyeDiff_ProbeEyeDiff_Probe1

V+

V-

Tx_DiffTx_Diff2

ExcludeLoad=yesMode=Maximal Length LFSRRiseFallTime=35 psecVlow=-140 mVVhigh=140 mVBitRate=10 Gbps

Tx

ONET8501T_outputstageX3

2

4

1

3

Term_DiffTerm_Diff1Load=100 Ohm

MSUBRO4350


MSub

Models defined in frequency domainand simulated in time domain using convolution

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17

RF Path in Time Domain

50O

hm50

Ohm

Testboard


Flex foilcircuit


Bond wire

RF in


TIA outputstage

Vtia Vbw

RF out

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

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18

Eye Diagram Measurement Setup

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19

Measurement Data: Eye Diagram

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

20 40 60 80 100 120 140 160 1800 200

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

-0.20

0.20

time, psec

Dens

ity

Flex line with Cu

Flex line with Ni/Au plating

Flex line has Ni/Au platingNi is a ferromagnetic conductor smaller skin depth = higher loss

receive opt. Power -12dBmsensitivity -18dBm (BER=10E-12)

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20

Measurements Data: TDR

30

40

50

60

70

0 20 40 60 80 100L(Er=3.38)[mm]

Z[oh

m]

J5J7

SMA

Test Board

Transition to Flex

Flex ctr

AC Cap.

V1

V2

! Terminal data exported! Port[1] = WavePort1:T1! Port[2] = WavePort1:T2! Port[3] = WavePort2:T1! Port[4] = WavePort2:T2

Vtb1

Vtb2

SIMULATION OF THE TDR RESPONSE OF THE DUT-BOARD

MSUBRO4350


MSub

TranTran1

LimitStepForTL=yesMaxTimeStep=Trise/6StopTime=1.4 nsecStartTime=0.0 nsec

TRANSIENT

RR1R=50 Ohm

VtStepSRC1

Rise=TriseVhigh=VscrVlow=0 Vt

VtStepSRC2

Rise=TriseVhigh=VscrVlow=0t

RR2R=50 Ohm

VARVAR1

Vscr=1 VTrise=20 psec

EqnVar


2

4

1

3

S4PSNP4File="FlexfoilcoverL18mmAuNi.s4p"

4

12

3Ref

MCLINCLin3

L=63 mmS=0.4 mmW=0.32 mmSubst="RO4350"MLIN

TL2


MLINTL1



4

12

3Ref

Z0239.442

Z0148.973

0.2 0.4 0.6 0.8 1.0 1.20.0 1.4

0.420.440.460.480.500.520.540.560.58

0.40

0.60

time, nsec

V1, V

541.0p494.8m

m1

1.048n440.9m

m2

-V2

m1time=V1=494.8mV

541.0psec

m2time=V1=440.9mV

1.048nsec

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Conclusion

21

First samples: full functional, acceptable sensitivity Bond wire interconnection & package ok Issues identified by measurements and simulations:

- Test board to flex circuit transition too much reflection- Flex circuit loss to high- Test board traces too long

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22

Results after Redesign

Test board to flex circuit transition improved (new concept)Flex circuit loss improved (no cover layer)Test board traces shorted (approx. half length)

sensitivity < -19.0dBm @ BER = 1E-12 (1 to 1.5dB improvement)

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23

Product Design Methodology

Predict performance early in the design cycle by creating models for each component, critical net and entire system and by performing local and system simulation.

Use measurements throughout the design cycle to reduce risk and increase confidence to the quality of predictions.

Eric Bogatin

Documents

High Speed Digital Signal Path Design for a 40 Gb /s Optical Receiver