High Switches Utilization Single-Phase PWM Boost-Type PFC Rectifier Topologies Multiplying the Switching Frequency

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 11, NOVEMBER 2014 5749

High Switches Utilization Single-Phase PWMBoost-Type PFC Rectifier Topologies Multiplying

the Switching FrequencyMarcio Silveira Ortmann, Member, IEEE, Thiago Batista Soeiro, Member, IEEE,

and Marcelo Lobo Heldwein, Senior Member, IEEE

Abstract—Decades of research have seen single-phase boost-type pulse-width modulation converters be employed as front-endpower factor correction (PFC) rectifiers in commercial power sup-plies. The benefits of employing this technology to comply withpower quality standards while assuring high efficiency, low vol-ume, and weight have been observed. However, this paper showsthat further efforts can be driven toward new topologies. In thiscontext, novel single-phase rectifier circuits are introduced. Theseare able to double or triple the ripple frequency present at theinput components. Furthermore, a high utilization of the switchesis observed during both positive and negative grid half-cycles. Thetheoretical analysis of the proposed topologies as well as their op-eration in PFC applications are presented and different operationmodes are proposed and a comparison with a state-of-the-art PFCrectifier is presented. Finally, experimental verification of a PFCrectifier doubling the switching frequency is presented in a 1-kWprototype employing a current self-control strategy.

Index Terms—High switching frequency, power factor correc-tion (PFC), power supplies, pulse-width modulation (PWM), PWMrectifiers.

NOMENCLATURE

Dx Diode xSx Switch xCo dc-link capacitorLb Boost inductorvx Voltage xVx Constant voltage xix Current xisw Switched currentIx Constant current xfg Grid-side fundamental frequencyfs Switching frequencyxg Subindex g denotes grid-side parameters

Manuscript received October 24, 2013; revised December 18, 2013; acceptedJanuary 17, 2014. Date of publication January 21, 2014; date of current versionJuly 8, 2014. Recommended for publication by Associate Editor J. M. Alonso.

M. S. Ortmann and M. L. Heldwein are with the Department of Electron-ics and Electrical Engineering (EEL), Federal University of Santa Catarina(UFSC), Florianopolis, SC, 88040-970, Brazil (e-mail: [email protected];[email protected]).

T. B. Soeiro is with the Power Electronics Group, ABB Corporate Re-search, CH-5405, Baden–Daettwil, Switzerland (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2014.2301814

xo Subindex o denotes dc-side parametersxpk Subindex pk denotes peak valuexmax Subindex max denotes the maximum valuexGaN Superscript GaN denotes a Gallium Nitrate semicon-

ductor parameterxOp.X Superscript Op.X denotes a parameter with respect

to converter operation mode Xω Grid angular frequencyT Switching periodsx Switching function for switch xδ Duty-cyclei Index ij Index jXavg Average value of XXrms Root mean square (RMS) value of XM Modulation indexΔIg Ripple value of the boost inductor currentn Switching frequency multiplierωtcrit Phase angle where the maximum current ripple occursrD Bridge diode conduction resistancerDS Series connected diode conduction resistanceVon,D Bridge diode forward conduction dropVon,DS Series connected diode forward conduction dropRS MOSFET conduction resistancePcon,tot Total semiconductors conduction lossesPsw,tot Total semiconductors switching lossesPo Output powerWsw Lost energy during a switching transitionκx Switching losses coefficient x

I. INTRODUCTION

UNIDIRECTIONAL single-phase boost-type pulse-widthmodulation (PWM) rectifiers are widely employed in

commercially available power supplies featuring power fac-tor correction (PFC) circuits. During the last decades, a largenumber of research efforts [1]–[3] have pursued improvementsin all aspects of this technology. Works on topologies, con-trols, modulation strategies, noise propagation reduction, ther-mal management, components design, semiconductors, designoptimization, and so forth have been recently documented in theliterature [4]–[15] and/or implemented by the industry. It is theauthors’ opinion that more work is left to be done despite all theperformed research works and based on the importance of PFCrectifiers in today’s electronics.

0885-8993 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

5750 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 11, NOVEMBER 2014

Fig. 1. Single-phase PWM boost-type rectifier topologies: (a) rectifier as presented in [16], and; proposed circuit able to (b) double and (c) triple the ripplefrequency present in the input and output passive components. Note that the circuit depicted in (b), which employs S1 /S2 , could be also assembled with S1 /S3 orS2 /S3 , where the position of S3 is shown in (c).

The topology presented in [16] and shown in Fig. 1(a) is ableto reduce conduction losses when compared to the conventionalsolution employing a diode bridge followed by a single boostdc–dc converter, i.e., the conventional boost PFC rectifier. This ismainly accomplished at high-input voltages, where the currentsflow through the bridge diodes most of the time. Moreover, con-duction losses are further reduced in topologies like the bridge-less boost PFCs [1], [16], [17], at the expense of asymmetricconducted emissions generation leading to increased common-mode (CM) currents. Furthermore, even though the bridgelessPFC rectifier topologies are highly efficient solutions and rep-resent the state-of-the-art for higher power converters, mosttopologies suffer from low utilization of the power semiconduc-tors and magnetic devices. A detailed analysis of the topology inFig. 1(a) has been presented in [18], where the main advantagesand drawbacks are analyzed. A high switch utilization is listedamong the advantages of this circuit. Comparisons of the struc-ture of Fig. 1(a) with other topologies have been performedin [16], [19] and show the potential of this structure for PFCapplications.

In this paper, developments from the topology shown inFig. 1(a) are proposed as seen in Fig. 1(b) and (c). By addingauxiliary turn-off switch(es) to the circuit and through propermodulation strategies, the ripple frequency components seen atthe ac-side terminals can be doubled or tripled and, thus, leadto reduced boost inductor and line filter requirements. Further-more, some of the stresses in the semiconductors are lessened,allowing for reduced switching losses and better losses distribu-tion. With this, more compact/light solutions can be achieved.

This paper is organized as follows. Initially, the basic op-eration of the proposed structures [see Fig. 1(b) and (c)] arepresented along with the calculation of the current stresses onactive and passive components. The topology employing twoswitches [see Fig. 1(b)] is implemented in a 1-kW prototypeillustrating a practical PFC application employing digital con-trol and modulation. Finally, the main features of the proposedconverters are discussed in the conclusions and in a comparisonto existing topologies.

II. SINGLE-PHASE PWM BOOST-TYPE RECTIFIERS OPERATION

In order to evaluate the operating stages of the proposedsingle-phase PWM boost-type rectifiers depicted in Fig. 1(b)

and (c), initially the latter circuit is considered as this comprisesthe operation possibilities of both topologies. The following as-sumptions are made to simplify the analysis: all componentsare lossless; the ac-voltage source is purely sinusoidal; the con-verters present ohmic behavior; current ig is ripple free; andthe dc-link voltage is constant. These assumptions are valid ifthe ac current presents low ripple, the dc-link capacitor is largeenough to absorb the second harmonic pulsating power, and theefficiency is high. Furthermore, the series equivalent resistanceof the dc-link capacitor is assumed null, since its effect is typi-cally negligible, unless the switched currents are very high. Inthe latter case, the high-frequency current harmonics lead to anincreased voltage ripple.

The possible operating stages for this converter during thepositive half-cycle of the grid voltage vg are shown in Fig. 2.It is seen in Fig. 2(a) that the input current flows through twodiodes D1,N and D2,N if all switches are turned OFF. ForPFC operation, this stage corresponds to most of the switchingperiods near the peak of the input current. This reduces thenumber of semiconductors in the current path and enables lowerconduction losses. The operation stages depicted in Fig. 2(b)–(f) correspond to alternative energy storing stages in the inputinductor Lb . The operation stages shown in Fig. 2(b)–(d) occurif one of the switches S1 , S2 or S3 is solely turned ON. Thesestages can be used to implement a modulation responsible fordoubling or tripling the effective switching frequency harmoniccomponents at the input and output currents when comparedto a conventional boost-type converter. For the operating stagesdepicted in Fig. 2(e) and (f), S3 is switched ON together with S1or S2 in order to reduce conduction losses as the input current igwill be shared between two power semiconductor paths. TurningS1 and S2 simultaneously ON is a forbidden switching stateas this leads to a short-circuit of the dc-link capacitor. As theoperating stages are complementary during the negative gridhalf-cycle, these are omitted here for the sake of brevity.

The main waveforms for the proposed converter depicted inFig. 1(b) during a switching period T = 1/fs are shown inFig. 3(a), where the modulation pattern leading to symmetricwaveforms and doubling of the effective switching frequency ispresented for switches S1 and S2 . As a reference, this circuit andmodulation will be referred to as Op.I . For the circuit shown inFig. 1(c), two operating modes are possible. The first, referredto as Op.II , is presented in Fig. 3(b), where the auxiliary switch

ORTMANN et al.: HIGH SWITCHES UTILIZATION SINGLE-PHASE PWM BOOST-TYPE PFC RECTIFIER TOPOLOGIES MULTIPLYING 5751

Fig. 2. Operation stages for the proposed single-phase PWM boost-type rectifier for the grid positive half-cycle when, (a) no switch is ON; (b) switch S1 is ON;(c) switch S2 is ON; (d) switch S3 is ON; (e) switches S1 and S3 are ON; and (f) switches S2 and S3 are ON.

Fig. 3. Main waveforms for the proposed single-phase PWM boost-type rectifiers during a switching cycle and positive vg : (a) circuit in Fig. 1(b) doubling theeffective switching frequency of the converter (Op.I); (b) circuit in Fig. 1(c) doubling (Op.II), and (c) tripling (Op.III) the effective switching frequency of theconverter.


TABLE IPOWER SEMICONDUCTORS, NORMALIZED BY Ipk , AVERAGE, AND RMSCURRENT VALUES FOR THE CONVENTIONAL SINGLE-SWITCH TOPOLOGY

[SEE FIG. 1(a)], WITH i = 1, 2 AND j = A, N

S3 is used to reduce conduction losses by switching simultane-ously with S1 or S2 . Finally, in Fig. 3(c), S3 is solely used asS1 and S2 to triple the converter effective switching frequency.This operation mode is referred as Op.III . Independently ofthe modulation strategy, it can be seen that by alternating be-tween the possible energy storing stages, the switches S1−3 anddiodes DSi,j , with i = 1, 2 and j = A,N , share the ac inputcurrent and can be rated for lower currents than those expectedin conventional boost-type converters, e.g., Fig. 1(a).

A hybrid operation based on different operation modes couldalso be advantageously used. In such hybrid operation, the con-verter would operate with a different number of turn-off switchesdepending on the output power level to reduce losses. For in-stance, the three-switches topology [see. Fig. 1(c)] could operatein any of the proposed operation modes at high output power,whereas only two switches would operate at lower power levels,and a single switch could be used at very low power. The aimhere is to flatten the efficiency curve of the rectifier.

A. Power Semiconductor Devices Stresses

The switched voltages across all semiconductors of the pro-posed topologies are clamped to the voltage Vo across the dc-linkcapacitor Co .

Defining the input current ig , the input ac voltage vg , and theoutput voltage Vo as ripple-free results in

ig = Ipk sin(ωt) (1)

vg = Vpk sin(ωt) (2)

where Ipk and Vpk are, respectively, the peak values of the acsource current and voltage, and ω = 2πfg is the grid angularfrequency.

Considering PFC operation and neglecting the voltage dropacross the ac inductor Lb , the duty-cycle variation δ is definedas

δ = 1 − M sin(ωt) (3)

with 0 ≤ ωt ≤ π where

M =Vpk

Vo(4)

is the modulation index. With these assumptions, the averageand RMS currents through the semiconductors for PFC opera-tion result in the expressions compiled in Tables I– IV.

The ratio from the derived current efforts expressions bythe input current peak value Ipk dependent on the modulationindex is plotted in Fig. 4 for the proposed topologies and inFig. 5 for the single-switch rectifier. It is observed that the moststressed components strongly depend on the modulation index.

TABLE IIPOWER SEMICONDUCTORS, NORMALIZED BY Ipk , AVERAGE, AND RMSCURRENT VALUES FOR THE TWO-SWITCHES TOPOLOGY [SEE FIG. 1(b)]

OPERATING TO DOUBLE THE EFFECTIVE SWITCHING FREQUENCY,WITH i = 1, 2 AND j = A, N

TABLE IIIPOWER SEMICONDUCTORS, NORMALIZED BY Ipk , AVERAGE, AND RMSCURRENT VALUES FOR THE THREE-SWITCHES TOPOLOGY [SEE FIG. 1(c)[OPERATING TO DOUBLE THE EFFECTIVE SWITCHING FREQUENCY AND

WITH S3 COMMANDED IN ORDER TO ENHANCE THE SYSTEM

CONDUCTION LOSSES, WITH i = 1, 2 AND j = A, N

TABLE IVPOWER SEMICONDUCTORS, NORMALIZED BY Ipk , AVERAGE, AND RMS

CURRENT VALUES FOR THE THREE-SWITCHES TOPOLOGY [SEE FIG. 1(c)]OPERATING TO TRIPLE THE EFFECTIVE SWITCHING FREQUENCY,

WITH i = 1, 2 AND j = A, N

For low-line operation, and consequently low-modulation index,the switches are more utilized, whereas for high-input voltages,the bridge rectifier diodes Dij present higher currents. Thischaracteristic is similar to other boost-type topologies.

Numerical simulations employing the software PSIM havebeen carried out in order to verify the accuracy of the derivedcurrent stresses. The circuit of Fig. 1(a)–(c) have been simulatedand the observed relative errors are below 0.1% for all currentefforts showing that the expressions are well correlated to thesimulation results.

B. Passive Components Stresses

The input inductor current switching frequency ripple ΔIg

can be approximated with good accuracy through a triangularwave with varying amplitude as in other boost-type PFC topolo-gies. Taking the intervals when the switches are on [see Fig. 2]and considering that the frequency of the voltage across the in-ductor is doubled (n = 2) or tripled (n = 3), the local averagepeak-to-peak ripple is

ΔIg∼= vg (1 − δ)

n fs Lb=

Vpk

nLb fs·[sin(ωt) − M sin2(ωt)

](5)

which is seen in Fig. 6 for varying modulation index and gridphase angle. Therefore, the proposed circuits present the sameexternal characteristics of a conventional single-switch boost-type PFC rectifier with n times the switching frequency.


Fig. 4. Current efforts shown as the ratio from the switch/diode/capacitor current values over the input current peak value Ipk : (a) two-switches rectifier as inFig. 1(b) doubling the effective switching frequency of the converter (Op.I); (b) three-switches rectifier as in Fig. 1(c) doubling (Op.II); and (c) tripling (Op.III)the effective switching frequency of the converter.

Fig. 5. Current efforts shown as the ratio from the switch/diode/capacitorcurrent values over the input current peak value Ipk for the single-switch rectifierin Fig. 1(a).

Finding the maximum of the current ripple leads to the criticalphase angles

∂ΔIg

∂ωt= 0 ⇒ ωtcrit =

⎧⎪⎪⎨

⎪⎪⎩

arcsin(

12M

); M ≥ 1

2π

2; M <

12

(6)and the maximum current ripple value is given by

ΔIg,max =

⎧⎪⎪⎨

⎪⎪⎩

Vpk

4 · n · fs · Lb · M; M ≥ 1

2

Vpk · (1 − M)n · fs · Lb ·

; M <12.

(7)

As for typical single-phase boost-type rectifiers, the outputcapacitor voltage ripple ΔVo is mainly defined by the low-frequency component with twice the grid frequency fg . It canbe computed with [20]

ΔVo =Po

2π fg Vo Co. (8)

The high-frequency current through the dc-link capacitor willbe the same as in a conventional single-switch boost-type PFCrectifier with n times the considered switching frequency.

(a)

(b)

Fig. 6. Normalized ac current ripple peak-to-peak value ΔIg as a function ofthe modulation index M and the grid phase angle ωt for: (a) doubled (n = 2),and (b) tripled (n = 3) equivalent input switching frequency.

The total output current io RMS value is found with

Io,rms =

√12π

∫ 2π

0(1 − δ) i2g dωt =

2 Ipk

3

√3M

π(9)

and its average value is

Io,avg =12π

∫ 2π

0(1 − δ) ig dωt =

M Ipk

2∼= Iload . (10)

Assuming that the load current presents a pure dc component,the output capacitor current absorbs all ac components. Thus,there is no correlation between these currents and the following


Fig. 7. Conducted emissions voltages resulting from computer simulations: (a) DM voltage vdm at the converter A and N terminals with the two-switchesrectifier [see Fig. 1(b)]; (b) DM voltage vdm in a single-switch rectifier [see Fig. 1(a)] and the bridgeless rectifier; (c) CM voltage vcm with the two-switchesrectifier; and (d) CM voltage vcm in a bridgeless rectifier. The reference is placed at the middle of the dc-link for both rectifiers. The 〈·〉 symbols denotes the localaveraged valued. Left graphs show the voltages for a complete fundamental cycle. Center graphs show a detail near the peak of the ac-side signals. Right graphsshow a fast Fourier transform (FFT) of the vdm or vcm voltages.

expression holds,

I2o,rms = I2

Co,rms + I2load . (11)

Consequently, the output capacitor RMS current is given by

ICo,rms =Ipk

6

√3M (16 − 3π M)

π(12)

which is plotted in Fig. 4 as a function of the modulation index.

C. Conducted Emissions Generation

The noise voltage sources that generate differential (DM)and common (CM) mode conducted emissions in the proposedrectifiers can be modeled based on the voltage levels that appearat the converter terminals A and N . Thus, the DM voltage sourceis here defined as

vdm = vA − vN (13)

and the CM voltage as

vcm =12

(vA + vN ). (14)

These voltages must be finally attenuated by line filters inorder to comply with relevant electromagnetic compatibility(EMC) regulations. Therefore, vdm and vcm are valid parame-ters to compare different topologies and/or modulation strate-gies. The proposed two-switches PFC rectifier DM and CMvoltages are depicted in Fig. 7 along with the same voltagesfor a single-switch rectifier [see. Fig. 1(a)], which presents

the same DM and CM voltages as a conventional bridgelessrectifier [1]. These simulation results were obtained with thefollowing considerations: the dc-link is modeled as two sym-metric dc-voltage sources with Vo/2; the boost inductor, andthe ac-voltage source were modeled as a sinusoidal currentsource in phase with the modulation signals; and, no parasiticelements were included. The resulting DM voltages are equalsince the same apparent frequency is exemplarily used, i.e.,fs = 140 kHz. However, the CM voltages differ. The conven-tional bridgeless rectifier presents a unipolar CM voltage withsteps equal to one half of the dc-link voltage. Whereas, theproposed two-switches topology shows a bipolar voltage alsowith steps of Vo/2. The CM voltage in the proposed rectifierpresents the groups of harmonics and side-bands at fs(i − 1

2 ),with i = {1, 2, 3, . . .}, while the conventional bridgeless hasharmonics centered at i fs , with i = {1, 2, 3, . . .}. This leads todifferent considerations regarding the choice of the switchingfrequency based on EMC regulations. For instance, whereas as-suming an EMC standard that has limits from 150 kHz on andconsidering CM emissions, choosing fs = 140 kHz is a reason-able for the bridgeless rectifier, but it is not the best choice for theproposed two-switch topology regarding CM voltage. However,assuming 150 kHz ≥ fs ≥ 300 kHz, the new two-switch recti-fier might be a better solution. A more careful analysis wouldbe required beyond fs = 300 kHz. An important considerationregarding noise generation is that the proposed converter is in-herently more symmetrical than a bridgeless or a single-switchtopology.


III. POWER SEMICONDUCTORS LOSSES

A. Conduction Losses

The forward voltage drop characteristics for the turn-offswitches are approximated with vS (iS ) = RS iS , where RS isthe switch on-state resistance. This assumes MOSFET powerdevices. The diodes have their forward voltage drop modeledas a linear resistance in series with a voltage source as invD (iD ) = rD iD + Von .

The total conduction losses across the semiconductors for thetwo-switches topology shown in Fig. 1(b), doubling the effectiveswitching frequency of the converter (Op.I), can be computedwith

P O p.Icon ,tot = I2

pk

[rD

(12

+4M

3π

)+ (RS + rD S )

(12− 4M

3π

)]

+ Ipk

[Von ,D

(2π

+M

2

)+ Von ,D S

(2π− M

2

)](15)

while for the circuit shown in Fig. 1(c), doubling and triplingthe effective switching frequency of the converter (Op.II andOp.III), the total conduction losses can be determined, respec-tively, with

P O p.I Icon ,tot = I2

pk

[rD

(14

+2M

π

)+ rD S

(34− 2M

π

)

+ RS

(14− 2M

3π

)]+ Ipk

[Von ,D

(1π

+3M

4

)

+ Von ,D S

(3π− 3M

4

)](16)

P O p.I I Icon ,tot = I2

pk

[rD

(13

+16M

9π

)+ (RS + rD S )

(23− 16M

9π

)]

+ Ipk

[Von ,D

(43π

+2M

3

)+ Von ,D S

(83π

− 2M

3

)].

(17)

There, rD and rDS are, respectively, the linearized resistancefor diodes Di,j and DSi,j ; Von,D and Von,DS are, respectively,the voltage sources for diodes Di,j and DSi,j . The total conduc-tion loss is given by (15) for the single-switch topology depictedin Fig. 1(a).

B. Switching Losses

Following the approach presented in [21], the switching lossenergy is approximated with a second-order polynomial func-tion of the switched voltages and currents. A further simplifica-tion adds the switching loss energy contributions for all switchesinto only three coefficients κ0 , κ1 , and κ2 , which represent thesum of the coefficients that model the switch turn-on and turn-off losses for the active switches and for the reverse recoverylosses of diodes Di,j . The switching loss energy as a functionof the switched current isw for a given diode and switch pair isdefined by

Wsw (isw ) = κ0 + κ1 isw + κ2 i2sw . (18)

Assuming ripple free ac current, the total switching losses forthe active switches for the circuits in Fig. 1(a) (n = 1), (b), and

Fig. 8. Two-switches PFC rectifier laboratory prototype.

(c) for operation modes Op.I (n = 2) and Op.III (n = 3) areobtained with

Psw,tot =1π

∫ π

0n fs Wsw (ig ) dωt (19)

which results in

Psw,tot = nfs

(κ0 +

2κ1

πIpk +

κ2

2I2pk

). (20)

The total reverse recovery losses of the diodes Di,j is given by

Psw,tot = fs

(2κ0 +

4κ1

πIpk + κ2 , I

2pk

). (21)

For the circuit in Fig. 1(c), under operation mode Op.II , theswitching losses of S3 are determined with

Psw,tot = 2fs

(κ0 +

2κ1

πIpk +

κ2

2I2pk

)(22)

while for both switches S1 and S2 , the sum of the turn-on andoff losses are calculated with (20) and n = 2. However, theswitched currents are ideally divided by two and the effectivevalues of the losses depend on parasitic components, gate driverdelays, and the power devices. An attractive option would be touse low-current fast-switching devices for S1 and S2 , in additionto high-current slow-switching S3 and guarantee that only S1or S2 assumes the full current during the commutations. Thiswould lead to reduced conduction losses. Another option wouldbe to remove either S1 or S2 and use this commutation strategywithout multiplying the switching frequency.

IV. CLOSED LOOP PFC OPERATION AND PRACTICAL

IMPLEMENTATION

A prototype of the two-switches topology presented inFig. 1(b) operating to double the effective switching frequencyof the converter was built and tested. This is seen in Fig. 8.In order to achieve rectification with PFC, the control strategy


Fig. 9. (a) Current self-control strategy implemented for PFC operation ofthe proposed rectifier [22]; and, (b) timing diagram for the modulation, controlupdate, and sampling implemented in the TMS320R2812 for the two-switchestopology.

employed in the practical implementation is shown in Fig. 9(a).It is a current self-control strategy as proposed in [22].

The control algorithm was implemented on a fixed point 32-bit digital signal controller TMS320R2812 [23] from TexasInstruments. The 16-bit timer/counter of the modulator hasbeen configured to generate a symmetrical PWM waveform,i.e., as triangular carrier modulation, with twice the switch-ing frequency (2 × fs = 90 kHz), generating interruptions atthe overflow and underflow events. The interrupt service rou-tine (ISR) is called by these events, where the sampling of thecontrolled variables, the processing algorithm, and the updateof control computations take place. In this context, the ISRis called twice per timer period, performing in double updatemode, as shown in Fig. 9(b). The duty-cycle computed by thecontrol law is managed by software before feeding the compareregisters in the modulator, so that each switch operates at thenominal switching frequency. A 250-ns dead time has been setin the gate driver circuitry to avoid simultaneous conduction ofswitches S1 and S2 . Fig. 10 shows experimental results for thePWM generation as described here.

The main components employed in the prototype are listedin Table V. The system has been designed for the followingspecification:

1) Output rated power Po,rated = 1 kW;2) Input voltage Vg,rms = 220 V (±15%) / 60 Hz;

Fig. 10. PWM signals for switches S1 and S2 experimentally obtained forthe PWM modulator operating at approximately 45-kHz switching frequency.

TABLE VSPECIFICATION OF THE MAIN COMPONENTS EMPLOYED

IN THE BUILT PROTOTYPE

3) Output dc voltage Vo∼= 370 V;

4) Switching frequency fs = 45 kHz.During the experiments, the input voltage was supplied by an

adjustable switching ac power supply from California Instru-ments, leading to input voltage waveforms with very low har-monic contents, so that the designed prototype could be testedagainst IEC-61000-3-2 harmonic requirements. The total har-monic distortion (THD) of the input voltage was measured lowerthan 0.47% for all load conditions and Class A limits were met.

Rated power PFC operation is proven in Fig. 11(a), wherethe input voltage and current waveforms are shown along withthe output voltage. It is seen that high-quality input current isdrained from the input supply. The measured input current THDwas lower than 2% for load above 400 W with a power factorhigher than 0.99. IEC-61000-3-2 harmonic requirements werealso met at these conditions. Fig. 11(b) shows the boost inductorcurrent and the current across switch S2 for the same conditions.The boost inductor current ripple is in good agreement with thetheoretical analysis. The current across S2 shows current peakswith values up to 14 A in the region close to the input voltagepeak that result from the reverse recovery of diodes Di,j .

During the standard operation of the rectifier, the voltageacross the switches Si are subject to higher stresses than pre-dicted in the simplified theoretical analysis. Voltages close to80 V higher than the output dc voltage are observed in the volt-age waveforms depicted in Fig. 12. These higher voltages occurduring the time intervals where the switch in opposite phase con-ducts. This happens due to two phenomena, namely: 1) voltagecharge and discharge processes between the equivalent parallelcapacitances of the semiconductors, which is dependent on the


Fig. 11. Experimental waveforms for (a) the mains current ig , input voltagevg , and output voltage vo obtained at rated power; and (b) current across S2and current iL b through the boost inductor.

ratio between the capacitance of the MOSFETs with respect tothe capacitance of the diodes DSi,j connected to each MOS-FET; and 2) voltage charge and discharge processes generatedby the reverse recovery of diodes Di,j . Diodes DSi,j isolatethe switches from the clamping effect of the dc-link capacitorswhen the switches do not conduct. Fig. 12(a) shows that theover-voltage levels are different for the positive and negativemains half-cycles depending on the equivalent parallel capaci-tances of DSi,j and Si and on the reverse recovery parametersof Di,j . This behavior can be drastically improved if diodeswith very low reverse recovery and parallel capacitance are em-ployed, for instance, SiC or GaN diodes. Another solution tothese over-voltages is to use clamping circuits. The built proto-type did not require any measure to be taken, since the observedover-voltages were well within the components ratings.

Fig. 12(b) shows that the boost inductor current ripplepresents the double of the switching frequency of the switches.Therefore, the provided theoretical analysis of the proposedtopology is validated.

Fig. 12. PFC operation showing: (a) current iL b through the boost inductorand voltage over S2 ; (b) current iL b through the boost inductor, current, andvoltage for switch S2 , where the doubling of the switching frequency is seenat the input terminals A and N through the high frequency ripple at the boostinductor current.

V. DISCUSSION ON SEMICONDUCTOR LOSSES

The operation stages of the proposed converter show thatdiodes Di,j present reverse recovery during their turn-off tran-sitions. On the other hand, diodes DSi,j are always in series withtheir respective switch Si , so that the turn-off of these diodes isdominated by the turn-off behavior of the switches. This analysisshows that the employment of diodes for Di,j with low reverserecovery, such as SiC or GaN diodes, is advantageous froma switching losses perspective as in other boost-type topolo-gies [24]. Diodes DSi,j do not profit much from changing theirtechnology due to two characteristics, namely that current SiCdiodes that are typically optimized for switching losses presenthigher conduction losses than Si diodes of same ratings and,finally, SiC diodes are more expensive. At the present moment,600-V GaN devices are not commercially available.

Fig. 13 shows the commutation waveforms for S2 . Currentand voltage across the switch are shown for a current of ap-proximately 7 A and a dc-link voltage of 370 V. It is seen that


Fig. 13. Current and voltage across switch S2 for rated power operation closeto the peak of the mains voltage.

(a)

(b)

Fig. 14. Curves for the: measured efficiency employing the built prototype;calculated efficiency for ultrafast Si diodes as in the prototype; and calculatedefficiency for GaN 600-V devices for the converters shown in Fig. 1(a) and (b).The assumed GaN devices are a GaN HEMT and a GaN diode from TransphormInc., where the loss data was obtained from [25], [26]. Loss calculation param-eters are specified in Table VI.

the turn-on of the switch presents high switching losses result-ing from the reverse recovery current peak, while the turn-offpresents relatively low losses due to the short switching timesof the employed CoolMOS transistor.

In order to quantify the potential losses reduction by replac-ing diodes Di,j with state-of-the-art GaN diodes, the theoreticallosses of the built prototype were computed for the employedSi switches. Fig. 14 shows the measured efficiency with varying

TABLE VILOSS PARAMETERS EMPLOYED TO COMPUTE THE LOSSES IN FIG. 14

load along with three theoretical curves, one for the currentlyemployed ultrafast Si diodes, a second curve showing the effi-ciency achievable by replacing diodes Di,j and switches with600-V GaN devices and increasing the switching frequency tofs = 140 kHz (turn-off devices switch at fs/2), and, finally,a third curve considering the conventional rectifier shown inFig. 1(a) employing the same GaN devices with fs = 140 kHz(turn-off devices switch at fs). The last configuration uses twoGaN transistors in parallel in S since two devices are also usedin the proposed converter [see Fig. 1(b)]. Thus, the double ofthe switching losses and half of the conduction losses are con-sidered for a given current level. The loss models coefficientsused in the losses computations are listed in Table VI. The com-parison is performed considering that the conventional and theproposed converters present the same waveforms with respect tothe boost inductor voltage and dc-link capacitor current. Higherefficiency can be achieved throughout the whole output powerrange and approximately 2% improvement is expected at ratedpower.

Another important aspect of the proposed converter regardingswitching losses is that the same number of switching transi-tions occur for a given apparent frequency in the voltage vA,N

as in other boost-type converters. This could lead to the ideathat the switching losses might be the same. However, it is im-portant to notice that components with lower current ratingscan be employed in the proposed approach. These switchestypically present lower switching losses than components withhigher ratings. This becomes obvious by considering that twoparallel connected MOSFETs present higher switching lossesthan a single one. Furthermore, the losses can be better dis-tributed among the semiconductors, potentially leading to lowerefforts for cooling the system. The main disadvantages of theproposed systems are the cost for a higher number of semi-conductors and the necessity of an insulated gate driver. The


additional losses of the insulated gate driver and its power sup-ply must also be considered. In addition, the insulated gatedriver must withstand the dv/dt achieved with the employedsemiconductors and the full dc-link voltage, which is typicallynot a challenging requirement as in insulated dc–dc converterapplications.

VI. CONCLUSION

This paper introduces new topologies for single-phase boost-type unidirectional rectifier applications. These circuits are char-acterized by good losses distribution among well utilized powersemiconductors and for providing a doubling or a tripling of theswitching frequency of a single switch at the input and outputcurrent ripples. Thus, the topologies are suitable for compactPFC designs. The disadvantages of the proposed circuits arerelated to the increased number of power devices with addi-tional isolated gate driver(s) and the need for a more complexmodulation that leads to increased computation efforts. Thesecan be offset by the volume reduction of the ac-side passivefiltering components, an overall reduction of losses and, thus,cooling requirements, and the use of integrated power modulesin higher power and switching frequency designs. The theo-retical analyses of current and voltage stresses in both passiveand active components and semiconductor losses have been pre-sented for the proposed circuits and validated through simulationresults. Digital control and modulation has been employed inone of the presented circuits leading to a modern and effec-tive implementation. Experimental results for a 1-kW prototypehave been presented showing that the topology is well suitedfor PFC applications, achieving high power factor, low-inputcurrent THD, and fair efficiency. The analysis of the semicon-ductor losses shows that the topology can profit from wide bandgap semiconductors from two perspectives, namely losses andover-voltages. In addition, one of the proposed converters wascompared to a state-of-the-art topology, where it was shownto achieve higher efficiency and similar to lower conductedemissions levels. These advantages are more prominent in highswitching frequency designs. Furthermore, good switch utiliza-tion is achieved since switches operate during the completemains period.

ACKNOWLEDGMENT

The authors would like to thank A. L. S. Pacheco for helpingwith the prototype.

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Marcio Silveira Ortmann (S’09–M’13) was born inSanto Angelo, Brazil, in 1981. He received the B.Sc.degree in electrical engineering from the NorthwestRegional University of the Rio Grande do Sul State,Ijuı, Brazil, in 2006, and the M.S. and Ph.D. degreesin electrical engineering from the Federal Universityof Santa Catarina, Florianopolis, Brazil, in 2008 and2012, respectively.

He is currently a Postdoctoral Researcher at thePower Electronics Institute, Federal University ofSanta Catarina. His research interests include PFC

rectifiers, digital control in power electronics, active filters, and power electron-ics for renewable energy sources.

Dr. Ortmann is a Student Member of the Brazilian Power Electronic Society.

Thiago Batista Soeiro (S’10–M’11) received theB.S. (Hons.) and M.S. degrees in electrical engineer-ing from the Federal University of Santa Catarina(UFSC), Florianopolis, Brazil, in 2004 and 2007, re-spectively, and the Ph.D. degree from the Swiss Fed-eral Institute of Technology Zurich, Zurich, Switzer-land, in 2012.

During the Master’s and Ph.D studies, he was aVisiting Scholar at the Power Electronics and En-ergy Research Group at Concordia University, Mon-treal, QC, Canada, and at the Center for Power Elec-

tronics Systems, Blacksburg, VA, USA, respectively. From 2012 to 2013, hewas a Researcher at the Power Electronics Institute, UFSC. He is currentlywith the Corporate Research of ABB Switzerland, Zurich, Switzerland. His re-search interests include power factor correction techniques and advanced powerconverters.

Marcelo Lobo Heldwein (S’99–M’08–SM’13) re-ceived the B.S. and M.S. degrees in electrical engi-neering from the Federal University of Santa Catarina(UFSC), Florianopolis, Brazil, in 1997 and 1999, re-spectively, and the Ph.D. degree from the Swiss Fed-eral Institute of Technology, Zurich, Switzerland, in2007.

He is currently an Adjunct Professor with the De-partment of Electronics and Electrical Engineering,UFSC. From 1999 to 2003, he worked with industries,including research at the Power Electronics Institute,

Florianopolis, Brazil and Emerson Network Power, Brazil and Sweden. He wasa Postdoctoral Fellow at the ETH Zurich and at the UFSC from 2007 to 2009.His research interests include power electronics, advanced power distribution,and electromagnetic compatibility.

Dr. Heldwein is a Member of the Brazilian Power Electronic Society.

Documents

High Switches Utilization Single-Phase PWM Boost-Type PFC Rectifier Topologies Multiplying the Switching Frequency