Proceedings of Asia-Pacific Microwave Conference 2007

A Highly Linear CMOS Power Amplifier with AM-AM andAM-PM Compensation for 2.3GHz Wibro/WiMax

ApplicationsHyun Jin Yoo and Yun Seong Eo

RF Circuits And Systems Lab, Kwangwoon University, Seoul 139-701, Korea,

Abstract- A highly linear 2.3GHz CMOS power amplifierapplicable to Wibro/Wimax RF transmitter with AM-AM andAM-PM compensation is presented. The varactors are used asa part of tuned circuits to correct the phase distortion and gatebias control circuit to compensate the amplitude distortion ofpower amplifier. The proposed CMOS PA has beenimplemented in 0.13um CMOS technology. The simulationresults show the improvement of P1dB of 5dB and the PAE from2.5% to 7.5% at the average power, respectively.

I. INTRODUCTION

The high power amplifier has been a critical bottleneckinto true single chip RF transceiver on CMOS technologybecause of its drawback such as a leakage through substrate,reliability problem of breakdown, and low power efficiency.However, nowadays the study of integrated CMOS poweramplifier has been intensively carried out due to thedisadvantages of external power amplifier such as expensivecost and its large volume. Especially, getting bad to worse,for RF transmitter based on OFDM signal, whose peak-to-average ratio (PAR) is so high, the power amplifier musthave much higher P1dB than the average power. If the poweramplifier is back off due to high PAR, then the power-added-efficiency (PAE) of power amplifier at the averagepower drastically decreases. This may cause the criticalproblem of reducing the battery lifetime of the system.Therefore, it is needed to improve the linearity andefficiency at the average power simultaneously.There has been reported a work where the nonlinearity

introduced by an additional PMOS transistor in parallelcancels the 3rd order nonlinearity of NMOS [1]. But thistechnology may reduce the gain of power amplifier and hasthe poor immunity to the threshold voltage variationdifference between NMOS and PMOS. Also anotherliterature has reported a harmonic control and biasoptimization for the nonlinearity based on the analysis ofdevice linearity [2][3]. But the improvement of the linearityof power amplifier is limited. The AM-AM distortion can bedecreased by controlling the gate bias of power amplifier [4].However, the improvement is not so much to enhance thepower efficiency and output power dramatically.

Recently, there has been a work that proposes to digitallycorrect the AM-PM distortion using correction table andcontrol of varactor capacitance [5]. The achieved results areuseful to adopt for increasing the efficiency and linearitysame time. But they used the digital correction method and

applied only AM-PM correction for improving performance.Moreover, it can be doubted that the digital look up tablemay cause delay time and limit the signal bandwidth.

This paper proposes a new correction method that reducesAM-AM and AM-PM distortions and improves the linearityand efficiency using analog compensation circuits to meethigh linearity for Wibro/Wimax applications. The analogAM-AM and AM-PM compensation blocks consist of RFpower detector and DC level shifter with gain control so thatthe distortion and efficiency of power amplifier can beadaptively tuned and optimized. Section II presents thedistortion compensated CMOS PA architecture and thecomposite blocks and section lI shows the AM-AM andAM-PM compensation method. The simulation results ofthe designed circuits are exhibited in section IV. Finallysection V presents the conclusion of this work.

II. THE DESIGN OF THE PROPOSED CIRCUITS

Fig.1 shows the proposed CMOS transmitter front endwhich consists of driver amplifier (DA), power amplifier(PA), power detector (PD), and control circuits.

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Fig. 1 The proposed CMOS transmitter front end (PA + DA)

The PD block detects the RF input power level and makesDC voltage to control the following DC level shifter circuits.The level shifter manipulates the DC level coming out fromPD and shifts up or down DC voltage level to properly

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control the varactors and PA bias. The shifted DC voltageand the DC control range can be controlled externally.

A. Power detector and level shifter

The schematic of designed power detector is shown inFig.2. In the PD operation, M2-M3 are differential pair andas the input power grows the fundamental component ofsource voltage of M2-M3 is cancelled. However, thecommon mode or second harmonic component of sourcevoltage is increased and then, the output voltage is filteredby LPF and the DC level proportional to input power levelis generated at the output.

BIAS2

RF_INP

BIAS1

Fig. 2 The schematic of power detector circuit

The acquired output DC voltage signal of the PD needs tobe adapted using DC level shifter circuits for proper controlof varactor and PA's gate bias. On the other hand, itsvariable range is also required to be retuned for controlrange ofDC value of varactor and PA bias.

INPUTED / R R2

OUT

VREF

INPUT [ N RI R2

Fig. 3 The DC Level shifter with DC gain control

The variable range of DC voltage can be controlled usingan op-amp inverting amplifier and the DC gain is decided tobe the ratio of R2 to R1 as shown Fig. 3. The low limit ofDCvoltage of output becomes VREF, which is output DC voltage

when the RF input power is zero. This is easilydemonstrated using the voltage superposition. The optimalVREF is different for varactor and PA bias. Therefore, phasecontrol path (to varactor) and amplitude control path (to PAbias) must be differently optimized with respect to VREF.The values of RI and R2 are also tuned and optimized forphase control and amplitude control respectively.

B. Driver amplifier design

The driver amplifier (DA) generates a proper signal todrive the power amplifier. Therefore, the margin of linearityof DA is very important because if DA is saturated earlierthan the following power amplifier, the linearity of totalamplifier chain is decided by DA rather than PA. Theproposed DA is designed in differential fashion with g.switched gain control as shown in Fig. 4. The M1-M3 areconnected in parallel and the gain of DA is controlled byswitching the MI-M3. The output load is the LC resonatortype and C is the parallel sum of shunt capacitor and inputcapacitor seen into the power amplifier input. The values ofL and C are selected so that the output voltage swing ofDAis marginally smaller than the maximum allowable DAoutput swing. Also, in order to drive the cascading poweramplifier sufficiently, the device size of DA transistor isdetermined by considering the size ratio between PA andDA.

VDD

Fig. 4 The schematic of the proposed driver amplifier with 3 stagecontrol

C. Power amplifier design

Fig.5 shows a simplified schematic of the differential PAused in this work. Thick gate devices, M2, were used toprevent the effect of oxide breakdown and hot carrierdegradation, and make it possible to use larger supplyvoltage. Moreover, the cascode configuration improves thestability of the PA due to better isolation. For the lower sidetransistors, the typical thin oxide NMOS is used because thevoltage swing across gate and drain oxide is not large and

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high transconductance g. is required for high gain. The PAinput stage consists of bias circuit and DC decouplingcapacitors. And the feedback resistor Rf, and bypasscapacitor Cf are used to improve the stability of PA circuit.The load line method for PA design is very clearlyexplained in [6]. In this work, the load line method is usedto design the output load matching network of PA. The loadmatching circuit is composed of the off-chip L and Ccomponents because on-chip spiral inductor causes highpower loss and drastically degrades the power efficiency.And all of the parasitic components such as pad parasiticcapacitance and wire bond inductance are also included inthe load matching network.

External Load Line Matching,Circuit

-1I IRF OUTN J----- ,- -E RE_OUTP

BIAS2 Cf M2 M2c

BIAS2

Rf Rf

RF INPE: M1Mlml RFINN

RI R2

BIAS1

Wire BondInductor

Fig. 5 The schematic of the proposed power amplifier

III. THE AM-AM AND AM-PM COMPENSATIONS

As shown in Fig. 6, the phase response of amplifier is notconstant, or in other word, not linear. As input power goesup, the phase may be distorted and shows the AM-PMdistortion. In this work, the power detector measures theinput power level and makes the DC voltage correspondingto measured power level. The DC level shifter tunes andscales up and down the DC voltage of PD output to makeadequate voltage for achieving phase compensation andamplitude compensation.

Phase

Compensatethe phase error

power

Fig. 6 The concept of the proposed phase compensation

AM-PM distortion can be corrected by introducing aninverse phase shift to cancel the input power dependentphase shift of the PA. The Fig. 7 shows the methods of thephase compensation. The various colored lines correspondto the phase response of overall amplifier chain for variousvaractor control DC voltages. The varactor is connected inparallel with DA load inductor and capacitor. If input powerincreases and varactor control voltage is not changed, thephase response decreases seemingly above the -5dBm.Instead, if the varactor voltage is adaptively controlledaccording to the RF power, the phase response can be keptnearly constant at any power level. With respect to AM-AMdistortion, the amplitude compensation is also achieved byPD and level shifter.

Fig. 7 The phase response ofPA vs input power and how tocompensate phase variation

As the input RF power grows, the bias point of PAgradually increases [4]. Therefore, as power grows up, theP1dB of PA is increased as well because boosting up gatebias of PA makes gain higher. In this manner, AM-AMdistortion can be compensated and linearization is achieved.

IV. SIMULATION RESULTS

In this work, the proposed simultaneous AM-AM/AM-PM compensation is simulated using Cadence Spectre RFtool and the simulation results are shown as follows. Thevaractor is used for phase compensation as shown in Fig. 1.Fig. 8 presents the corrected phase response comparing withthe uncompensated one. Above 3dBm input power the phaseerror may be more than 1.5°. With phase compensation, thephase error can be reduced under 0.7° and the linearity isimproved dramatically with respect to AM-PM distortion.The amplitude distortion is also corrected using gate biascontrol circuits. Though the P1dB is slightly affected byphase compensation, the P1dB of PA is mainly related toamplitude compensation.The P1dB, power gain and power-added-efficiency (PAE)

with and without AM-AM/AM-PM error compensation areshown in Fig. 9 and 10, respectively. In order to compare

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with the conventional PA, a same PA without phase andamplitude compensation is simulated in same conditions. InFig. 9 and 10, the simulated performances of two PAs arecompared in respect of gain, power, and efficiency. Thesimulated gain of compensated PA and conventional one are22.4 dB and 22.3 dB, respectively.

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Fig. 8 The phase variation ofPA with and without phase compenso

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Fig. 9 The PIdB, power gain and PAE without compensation

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The simulated P1dB is 19.7dBm and 24.7dBm for each PA.Using the AM-AM/AM-PM compensation the P1dB of PA isincreased by 5dB. And the power efficiency is alsoimproved from 14.6% to 22.6% at P1dB. The efficiency at8dB backed-off power from P1dB, which is the averagepower, is also increased from 2.5% to 7.50.

V. CONCLUSION

A 2.3 GHz Wibro/WiMAX CMOS power amplifier withthe proposed AM-AM and AM-PM compensation ispresented. The performance of power amplifier withcompensation method using only analog circuits such aspower detector and DC level shifter with gain control isevaluated using Cadence Spectre RF tool. Comparing withthe conventional PA without compensation circuit, the P1dB isimproved from 19.7dBm to 24.7dBm. Moreover, theachieved PAE at average power, which is 8dB backed offfrom P1dB point, is dramatically increased from 2.5% to 7.5°/O.

ACKNOWLEDGMENT

This work has been supported by Ministry of Commerce,Industry and Energy (MOCIE) and also supported by

r Development of Transceiver System for Next GenerationWireless Communication of Next Generation NewTechnology Business in 2007.

REFERENCES

[1] C. Wang, L. Larson, and P. Asbeck, " A nonlinear capacitancecancellation technique and its application to a CMOS class-AB power

5 amplifier." in IEEE Radio Frequency Integrated Circuits(RFIC)Symp. Dig. Paper, Jun. 2001, pp. 39-42

[2] Jongchan Kang, Jehyung Yoon, Kyoungjoon Min, Daekyu Yu,Joongjin Nam, Youngoo Yang, Bumman Kim, " A highly linear andefficient differential CMOS power amplifier with harmonic control",IEEE J Solid State-Circuits, vol. 44, Jun. 2006, pp. 13 14-1322

[3] Jongchan Kang, Daekyu Yu, Youngoo Yang, Bumman Kim, " Highlylinear 0.18um CMOS power amplifier with deep n-well structure.",IEEE J Solid State-Circuits, vol. 41, May. 2006, pp. 1073-1080

30 [4] YunSeong Eo, KwangDu Lee, "High efficiency 5GHz CMOS poweramplifier with adaptive bias control circuit", IEEE Radio Frequency

25 Integrated Circuits(RFIC) Symp. Dig. Paper, 2004, pp.

[5] Palaskas, Y. et al., " A 5-GHz 20-dBm power amplifier with digitallyassisted AM-PM correction in a 90-nm CMOS process", IEEE J

20 Solid State-Circuits, vol. 41, Aug. 2006, pp. 1757-1763

[6] S. Cripps, RF Power Amplifiers for Wireless Communications.

15 Boston, MA: Artech House, 1999

Input Power [dBm]

Fig. 10 The P1dB, power gain and PAE with compensation

---| Without phase compensationWith phase compensation

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