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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006 229

A High-Efficiency Fully Digital Synchronous BuckConverter Power Delivery System Based

on a Finite-State MachineDae Woon Kang, Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and James T. Doyle, Senior Member, IEEE

AbstractA fully digital, self-adjusting, and high-efficiencypower supply system has been developed based on a finite-statemachine (FSM) control scheme. The system dynamically monitorscircuit performance with a delay line and provides a substantiallyconstant minimum supply voltage for digital processors to prop-erly operate at a given frequency. In addition, the system adjuststhe supply voltage to the required minimum under differentprocess, voltage, and temperature and load conditions. The designissues of the fully digital power delivery system are discussedand addressed. This digital FSM scheme significantly reduces thecomplexity of control-loop implementation ( 1800 gates) andpower consumption ( 100 W at 1.2 V) compared to otherapproaches based on proportionalintegraldifferential control.The power delivery control system is fabricated in a 0.13- mCMOS process and its core die size is 160 110 m2.

Index TermsAdaptive voltage scaling, digital switcher, highyield, low-power dissipation.

I. INTRODUCTION

THE STRONG demand for low-power computing has beendriven by a growing variety of portable and battery-op-erated electronic devices. These span a broad range of perfor-mance and functions with respect to throughput. Power con-sumption is a limiting factor in VLSI integration for portableapplications. The resulting heat dissipation also limits the fea-sible packaging and performance of the VLSI chip. Since thedynamic power dissipation in synchronous digital integrated cir-cuits is determined by , reducing the supply voltage is aneffective way to reduce power consumption. However, the gatedelay of a digital gate is inversely proportional to the supplyvoltage. Therefore, the application operates at a reduced clockfrequency with a lower supply voltage at the cost of performancereduction to meet the low power requirement. This is not a desir-able solution to keep pace with the current demand for improvedperformance.

Adaptive voltage scaling (AVS) can decrease power con-sumption without sacrificing performance provided the tasksperformed are finished within the allowed time. If AVS isemployed to dynamically adjust both clock frequency and

Manuscript received December 14, 2004; revised October 29, 2005.D. W. Kang and J. T. Doyle are with National Semiconductor Corporation,

Longmont, CO 80501 USA (e-mail: [email protected]; [email protected]).Y.-B. Kim was with the University of Utah, Salt Lake City, UT 84112 USA.

He is now with the Department of Electrical and Computer Engineering, North-eastern University, Boston, MA 02115 USA (e-mail: [email protected]).

Digital Object Identifier 10.1109/TVLSI.2006.871764

supply voltage depending on the computational work load,the power consumption required for the given task can bedynamically and adaptively optimized. For instance, in manyportable-computing devices such as MP3-players and digitalcameras, the full processing capability of a processor is notalways required. There are certain times when the operatingfrequency may be reduced; and a lower frequency means alonger allowable delay. This increased time margin also allowsthe supply voltage level to be lowered albeit with an increasedpropagation delay. Since power consumption is quadraticwith supply voltage and proportional to operating frequency,reducing both allows excellent energy-efficient operation. Fromthe tradeoff between performance and energy consumption,supplying just enough voltage to a system at a given frequencyrepresents the optimum power consumption [1][9].

Techniques for minimizing power consumption using AVShave been proposed for digital applications at a fixed throughput[6], and demonstrated on silicon for microprocessor application[7]. Their performance is improved for variable-rate digitalsignal processing throughput [8] and [9]. Most previous worksused analog- or mixed-mode circuit techniques for these im-plementations, which caused yield and tuning problems dueto process, voltage, and temperature (PVT) variations. Thecontribution of this paper is to extend these efforts by consid-ering yield issues and the compensation of fabrication processparameter nonuniformity in a single die, reference voltagefluctuation, and temperature variation.

The conventional AVS system implemented using analog- ormixed-mode circuitry presents another practical issue in uti-lizing AVS systems. This is the reuse of predefined intellectualproperty (IP) along with fabrication process migration. Soft-IPtype is the only way to make the transition to deep-submicrom-eter technologies and multimillion-gate silicon systems in aneconomical and timely manner. As systems-on-chip (SOC) be-come larger and more complex, they perform many differentfunctions on a single piece of silicon. Unless predefined partsare used, the SOC is too expensive to produce and impossibleto bring to market in a timely manner. As one of these efforts,the fully digital self-adjusting minimum-power supply systemis implemented as a soft-IP form.

This paper presents a fully digital synchronous adaptive buckconverter power delivery system that compensates the impactof operational and intrinsic parameter fluctuations on circuitperformance and can be provided in soft-IP form. The imple-mentation of the fully digital self-adjusting minimum-powersupply system to regulate the supply voltage as the minimum

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230 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006

required operating value at given PVT and frequency is pre-sented along with the detail algorithm to compensate the PVTvariations. The methodology for compensating the impact ofoperational and parameter fluctuations on CMOS circuit per-formance is discussed in Section II. The implementation of thefully digital self-adjusting minimum supply system and analysisof measured results from fabricated test chips are described inSection III and Section IV, respectively.

II. METHODOLOGY FOR COMPENSATING THE IMPACTOF OPERATIONAL AND PARAMETER FLUCTUATIONS

A. Yield Improvement by Adjusting Supply VoltageWhile the operating frequency limits allowable propagation

delay, this delay strongly depends on intrinsic process parame-ters, supply voltage, and junction temperature. The propagationdelay in a MOSFET is proportional to the product of the activeresistance of the MOSFET and load capacitance as in (1)

(1)

where is the velocity saturation term, is the processtransconductance parameter, is the supply voltage, isthe threshold voltage, is the drain capacitance, is thegate capacitance, and is the interconnect capacitance.

In deep-submicrometer circuit design, variations due to theprocess variation cause differences in transistor and intercon-nect characteristics across a single die. They, in turn, impactthe performance of circuits since they generate deviations inMOSFET drive current, resulting in propagation delay distri-butions of the critical path across a chip. Furthermore, the dis-tribution of process parameters expands from die to die withina wafer as well as a lot. After fabrication, operating variationssuch as power supply voltage, and across-chip temperature alsoaffect the propagation delay. By combining both operationaland process induced variations, the propagation delay fluctuatesfrom 18% to 32% [10]. The yield of CMOS logic circuits satis-fying a specific performance requirement is significantly influ-enced by the magnitude of critical path delay deviations due toboth operational and intrinsic parameter fluctuations.

Process parameters and operating junction temperature arenot controllable, but supply voltage is. Therefore, if the supplyvoltage can be adjusted to guarantee the same propagation delayregardless of the other operating conditions, various simulationsare not needed to assure proper functionality. Instead, only onecase, the worst case simulation with small margin is needed toguarantee proper operation after fabrication. If a design is fab-ricated at the best process corner and is operating at low tem-perature, it needs less than 3/4 of the minimum supply voltagerequired to operate at the worst case [10]. This results in powersavings by reducing supply voltage with regard to process andtemperature. Moreover, the distribution of the variations can bemoved to the desirable position by increasing supply voltage asshown in Fig. 1 [10]. On the other hand, by dynamically ad-justing the supply voltage, the individual die is adjusted to the

Fig. 1. n critical-path delay distribution shift from the nominal delay(T ) due to an increase in V for a desired yield.

desirable performance. Typically the supply voltage should beraised for dies that are operating slowly and lowered for the diesthat are performing fast. Therefore, the yield of the chip is im-proved if an AVS system is employed.

B. Delay Monitoring Under Different Operating ConditionsThe propagation delay depends on PVT conditions which are

not determined before fabrication. Moreover, the junction tem-perature is determined at the moment of operation. Both are notcontrollable, only observable. Alternatively, the supply voltageis an adjustable factor to guarantee a desirable delay. Due to theobservability of process and temperature and the controllabilityof supply voltage for the propagation delay in digital circuit, itis possible to monitor and control critical path delay using itsreplica circuit. This guarantees the minimum propagation delayfor operation at a given frequency.

Since the performance of a digital system is limited by itsworst case critical path delay, an exact replica of this delay pathwithin a single chip is one of the most accurate ways to mea-sure delay variation with respect to different PVT variations.However, designers normally balance delay paths as much aspossible. Moreover, critical paths may differ depending on op-erating conditions; therefore, identifying a single path may bedifficult. Instead, a series chain of primitive cells is consideredto model the critical path delay. The delay of a simple delay cellproperly tracks the critical path of digital circuits under variousoperating environments [5]. Fig. 2 illustrates equivalent voltagesto guarantee the same propagation delay under different cornersof a 0.13- m process technology. By fabricating the critical pathreplica of a digital circuit on the same die, its propagation delayclosely tracks the critical path of a chip over variations of PVT.

In designing the critical path replica to compensate the supplyvoltage change due to PVT variations, the characterization datasuch as load current at the target supply voltage and operatingfrequency are considered since both will change as the load cur-rent changes. Fig. 3 shows the supply voltage changes due to theload current variations.

KANG et al.: A HIGH-EFFICIENCY FULLY DIGITAL SYNCHRONOUS BUCK CONVERTER POWER DELIVERY SYSTEM 231

Fig. 2. Function of supply voltage for a 0.13-m process delay transfer char-acteristic at the best (bottom line), typical (middle line), and the worst (top line)cases.

Fig. 3. Supply voltage level shift (55 mV, top wave) due to variations of loadcurrent change between 50 and 250 mA.

C. Prior Digital Control-Loops of DCDC ConverterFig. 4 shows a typical digital-controlled switching converter

which consists of an analog-to-digital converter (ADC), a PIDcompensator, a reference source, a digital pulse width modulator(DPWM) regulator, and a dcdc converter [5]. The low-pass in-duct-capacitor (LC) filter in a dcdc converter is a two-pole res-onant system to store energy. Since the response of a two-polesystem may have excessive energy, any transitions introducedin the system may cause damped oscillation with a long decaytime in the LC network. Thus, to maintain a roughly constantsupply voltage in response to changes in PVT, load, and fre-quency, a compensation circuit is necessary. The compensationcircuit eliminates the ringing effect by adding a zero that can-cels one pole in the LC network, resulting in a stable first-ordersystem.

To achieve fast stable response in the pulsewidth modula-tion (PWM) mode, a discrete-time PID controller is typicallyused. The PID control provides loop stability without sacrificingbandwidth and improves the loops transient response. How-ever, the implementation adds a heavy hardware burden becausea PID control equation is typically expressed in terms of the cur-rent and prior values of duty ratio, error between the current andreference voltage, and the gains of the proportional (P), integral(I), and differential (D) blocks that are multiplied by the errorsignal as shown in Fig. 4.

Fig. 4. Block diagram of a typical digital-controlled dcdc converter.

D. AVS Compensation Issues Over PVTand Frequency Variations

To provide an error signal for a PID control loop, prior ap-proaches require a reference source (constant voltage [11] orfixed frequency [3]) that occupies space reserved for a designand consumes power. Since the reference is implemented asan analog- or mixed-signal circuit, it is difficult to implementa fully digital AVS controller. Moreover, the pitfall of the ref-erence based supply voltage schemes [3], [4], and [11] with re-gard to only a given frequency, is that its supply voltage is usu-ally not the minimum voltage in which a chip operates properly.The reason is that the propagation delay strongly varies in re-sponse to PVT as in (1) while a frequency determines an allow-able propagation delay. In other words, if a chip is fabricatedat the best process corner and operates at low temperature, itsminimum supply voltage is only 3/4 of the minimum voltage toguarantee the proper function at the worst case. The minimumpower consumption at the best case is about half of the worstcase due to the quadratic dependency of power. Therefore, theadaptive-power supply system considers PVT and load condi-tions as well as operating frequency.

The presented AVS requires some additional restrictive con-siderations compared to prior AVS implementations due to bothdelay and parameter variations. First, higher digital-to-analogconverter (DAC) resolution is needed since AVS is prone to bein a limit-cycling mode. If the ADC has a 6-bit resolution at3.3 V, the worst case step voltage is about 50 mV. If DAC has7 bits, its resolution at 3.6 V is about 28 mV and may avoidlimit-cycling. However, the step voltage is about 26.5 mV at thebest case as shown in Fig. 2. This results in limit-cycling since7-bit DAC resolution at the worst case is less than that of 6-bitADC at the best case. Therefore, 8-bit DAC resolution is neededto prevent limit-cycling from occurring. The DACs higher reso-lution than the ADC often results in multiple DAC values in theADC. When a high to low transition occurs with a frequencychange, the highest DAC voltage level equal to the ADC levelmay be a settling point. Alternatively, during low to high, thelowest level may be acquired.


Fig. 5. Block diagram of all digital self-adjusting minimum power supply system.

Fig. 6. Circuit schematic of slacktime detector.

III. FULLY DIGITAL SELF-ADJUSTING MINIMUM SUPPLYSYSTEM DESIGN

A block diagram of the all digital self-adjusting minimumpower supply system is presented in Fig. 5. The system con-sists of a closed-loop controller, a fixed frequency clock signal(CLK), frequency information (FI), a dcdc buck-converter, anda processor as a load current source. The loop controller con-sists of a slacktime detector, a voltage adjuster, and a PWMmodulator. The presented controller performs the following dis-crete-time compensation:

(2)

where is the next value of the duty ratio, , ,and are the frequency compensation, the current valuesof the detected error, and the accumulated compensation, re-spectively, and is error scaling factor. As in (2), the controlapproach does not request any previous values, while an accu-mulated compensation factor is needed. The variations of PVT

and load are dynamically updated in the compensation factor.During updating, the duty ratio is controlled by a finite-statemachine (FSM) which maintains a substantially constant supplyvoltage. The scaling coefficient is used to increase the error res-olution and it is implemented by the shift-right function insteadof multiplication.

A. Slacktime DetectorSlacktime detection is the ability to determine the minimum

voltage required for a given operating frequency. It requires con-tinuous monitoring of a critical path delay through the digitalcircuitry with respect to PVT, load, and frequency. The pro-posed slacktime detector consists of a chain of delay cells and atap register as shown in Fig. 6. The principle of a delayline as anADC, is based on the relation between supply voltage and prop-agation delay. The slacktime detector determines the voltagelevel of the delaylines supply based on the propagation delaythrough the delayline. In other words, the delay, along with thesupply voltage, is converted to a digital value by sampling thedelayline.


Fig. 7. Timing diagram of delayline outputs and clocks.

There are three considerations for designing a delayline tomonitor the critical path timing over PVT variations. The first re-quirement is to avoid the worst case crossover effect on the non-linear characteristics between delay and voltage. The crossoverbecomes worse when the delay increases longer or the voltagedecreases. Therefore, the margin for proper circuit operation isapplied for high-crossover ratio. Determination of the resolutionof delayline is the second consideration. A fine step size resultsin very slow settling while a coarse step size can cause hystereticoscillation. The last requirement is to minimize the hardwareburden for delayline. As semiconductor fabrication technologyimproves, circuit delay is shorter and, in turn, the number ofneeded cells to implement a critical path delay is larger.

From the last delayline design requirement, the cell of a de-layline should have low performance. A NOR structure slowlytransits at high-to-low transition compared to a NAND circuitstransition. However, low-to-high transition time of a NOR gateis the same as that of a NOT gate and is faster than a NAND gate.Therefore, a pair of NOR and NOT gates is selected as the unitdelay cell. The number of delay cells between taps is determinedby increasing a step voltage so the accumulated voltage stepsrequire one more tap active than the prior accumulated stepsvoltage at the worst case. The number of delay cells betweentaps varies because the propagation delay is not a linear func-tion of supply voltage.

The inverted input of the delay cell (NOR-INV) receives theinput clock signal or the output of prior delay cell; and the non-inverted input is connected to a delayline enable signal. Thesampling clock signal lags the input clock signal by a 1/4 ofa period. The tap register samples the values of the delayline at1/4 period intervals after the input clock pulse begins to prop-agate through the delayline. Fig. 7 shows the timing of the in-puts DX12 DX27 at each tap, the input clock signal (ICLK),the sample clock signal (SCLK), and delayline enable signal(RSTN).

The magnitude of the supply voltage is inferred by deter-mining how far along the delayline the input clock pulse propa-gates in a 1/4 period. Therefore, a delayline in the negative feed-back path of a closed loop reflects variations in circuit perfor-mance in response to variations of PVT, load, and frequency,and adaptively scales the regulated voltage of a buck converter

via a loop controller. The delayline is characterized at the worstcase with regard to fixed-frequency input sources. Delay of thedelayline implies its process corner, junction temperature, andsupply voltage at a given work load. From this measurement, adesirable constant supply voltage is determined in response toPVT and load variations. This guarantees the propagation de-lays just less than the critical path delay limitation and assuresproper operation.

B. Voltage AdjusterThe voltage adjuster consists of an error compensator, a fre-

quency compensator, a process, voltage, and temperature com-pensator, and a control block as shown in Fig. 8. The majorrole of the voltage adjuster is to compensate a supply voltageerror at a given frequency from the measurement of the slack-time detector and to provide a desirable constant voltage levelagainst variations of frequency as well as PVT. In addition, forhigh-speed and low-overshoot/undershoot start-up, it controlssoft-start operation.

1) Error Compensator: The role of the error compensatoris to detect the voltage error, as in (2), and to generate aproportionally compensated value. It receives the propagationdelay word TX(27:12) from the slacktime detector and detectsthe position of one and zero pair of taps as shown in Fig. 9.The compensator converts the propagation delay position to anerror voltage by comparing it to the reference delay positionalong with supply voltage under worst case conditions. In turn,it generates a proportionally compensated propagation delayword ECW(5:0) that represents a reference value at a defaultfrequency plus a compensated error value.

2) Frequency Compensator: The frequency compensatoradjusts the duty cycle of the PWM pulse based on the desiredsupply voltage at a given frequency. The first subtractor, SUB1,in Fig. 10 generates a difference between the frequency in-formation, FI(5:0), and the internal reference voltage level,RFI(5:0). The difference implies the desirable voltage variationin response to a given frequency. The up/down counter (CNT)receives the difference and counts up or down at the load signal(LOAD) until the output of the counter is equal to the difference.This prevents the supply level and frequency variation fromabruptly changing and reduces ringing. The second subtractor,SUB2, receives the proportionally compensated propagationdelay word ECW(5-0) from the error compensator and theshift-lefted counter number for the subtrahend, and generates afrequency compensated propagation delay word FCW1(5-0).

The compensated error-step from the delayline is the same asthe resolution of the delayline (6 bits). However, the resolutionof the DAC is higher than that of the ADC, and the error step alsohas a higher resolution. To increase the control resolution, theproportionally compensated error-value should be scaled closeto the resolution of the DAC. The third subtractor, SUB3, pro-vides a reference supply voltage word FCW2(5:0) at a givenfrequency FI(5:0). The one-bit higher resolution compensatedword FCW(7:1) is generated by adding the frequency compen-sated word to the reference supply voltage word. However, a7-bit DAC for a 6-bit ADC is insufficient to avoid limit-cycling(Section II). Therefore, dither logic generates a least signifi-cant bit (LSB) of the frequency compensated word FCW(0).


Fig. 8. Block diagram of voltage adjuster against variations of frequency and PVT.

Fig. 9. One-zero edge detector and an example of encoding procedure.

The LSB is toggled (average value) unless the desired voltage isnot achieved. When the supply voltage reaches a target voltage,the LSB is set to zero. The frequency compensated word rep-resents the reference value plus half of the compensated errorvalue and an additional LSB. FCW is corresponding to asin (2).

3) Process, Voltage, and Temperature Compensator: Itconsists of an internal dynamic voltage reference source, apulsewidth generator, and a ringing stopper as shown in Fig. 11.The internal dynamic voltage reference source adds or subtractsone, two, or three steps according to the increment/decrementindicators U1, U2, U3, D1, D2, D3, and generates an internaldynamic voltage reference, IREF(7-0). The reference valuecompensates the fluctuations due to process and temperaturevariations as well as the quantization error of the external supplyvoltage. Fig. 12 illustrates the equivalent supply voltages whichensure the same propagation delay at different operationaland intrinsic parameters. The pulsewidth generator, ADD1,receives the frequency compensated word FCW(7:0) and theaccumulated compensation [ as in (2)] IREF(7-0), and

generates a normal PWM pulsewidth NPW(7-0). The ringingstopper receives three inputs: a shift-lefted PWM pulsewidth, anormal PWM pulsewidth, and a shift-righted PWM pulsewidth.It outputs a pulsewidth word PW(7-0) in response to selectionsignals UP, NR, and DOWN. Since the high-valued derivativedirection of supply voltage during frequency-changing orstarting-up is unchanged by the step-size compensated valueNPW(7:0), emphasized activation (double or half size of PWMpulse) is needed.

4) Control Block of Voltage Adjuster: The control block con-sists of a clock generator, a tap selector, an FSM, a control signalgenerator, and a false low-level detector. The clock generatoroutputs a 1/4 frequency input clock signal, ICLK, and a 1/4 pe-riod lagged SCLK from an external clock input, CLK, a 1/32frequency PWM LOAD and a delayline RSTN from the SCLK,and a frequency doubled clock (DCLK) from the external inputclock, CLK, as shown in Fig. 13.

The tap selector chooses one of 4-taps prior-tap INCSET,center-tap CNTTAP, next-tap DECSET, and next next-tapDECSET2 from 16-taps TX12TX27 of a slacktime detector in


Fig. 10. Block diagram of frequency compensator.

Fig. 11. Block diagram of PVT compensator.

Fig. 12. Supply voltages corresponding to the equivalent propagation delay atdifferent conditions: (a) best case, (b) typical case, and (c) worst case.

response to external frequency information FI(5:0). The controlsignal generator outputs increment or decrement indicators UP,UP3, DOWN, and DOWN3 in response to the status of the tapdetector, the state CS2-CS0 from a finite-state machine, andexternal frequency information.

The FSM in Fig. 14 receives monitor signals from the othercontrol modules and datapath block, and it outputs controlsignals to the datapath block. The monitor signals consist of thefirst tap TX12, the last tap TX27, the 4-taps INCSET, CNTTAP,DECSET, and DECSET2, two frequency-change indicatorsINC and DEC, and the external FI. The control signals consistof a current state CS(2-0), a low-voltage state signal LOW,

a high-voltage state signal HIGH, and a clear signal CLRof a PWM pulsewidth counter. The states from 000 to 011control a soft-start routine to avoid large overshoot/undershootwith high-speed saturation. In the states from 100 to 111, theFSM controls the duty cycle of the DPWM according to thecurrent-voltage status detected by the 4-taps varying over PVTconditions. The outputs of the FSM are used to change thecounter number of the PVT compensator at weighed steps andto double or halve the counter number. This accelerates thesupply voltage to the appropriate value for various PVT quicklyand stably in start-up as well as normal operation.

The DACs higher resolution than ADC gives multiple DACvalues for a given ADC output. During a high-to-low voltagetransition with frequency change, the highest DAC voltage levelequal to the ADC level may be a settling point. The false low-level detector steps down the voltage level until a true minimumDAC level at a given frequency is detected. As shown in Fig. 15,the supply voltage settles at the first high DAC level in an ADCbin by the FSM and, in turn, converges to the bottom DAC levelby the false low-level detector.

C. DPWM Pulse ModulatorThe DPWM pulse modulator in Fig. 16 consists of a loadable

down counter and a pulse generator. Counter loads the PWMpulsewidth PW(7-0) from the voltage adjuster by the LOAD,changing a binary output of counter as a count in response tothe DCLK. DPWM pulse modulator outputs a pulse modulatedsignal PWM defined by the binary input value PW(7-0) ofcounter.


Fig. 13. Block diagram of clock generator and a timing diagram of clocks.

Fig. 14. State diagram of the FSM.


Fig. 15. Supply voltage lock acquisitions.

Fig. 16. Block diagram of PWM modulator.

Fig. 17. Die photo and layout.

D. DPWM Driver

The single loop design eliminates most of the analog circuitincluding references, ramp generators, and ADC comparators,normally associated with analog synchronous buck converters.A driver chip less than 1 mm on a side can easily be devel-oped and placed in a low-cost SOT23-5 or a bump chippackage. A 0.5- m power CMOS process serves as an excellentchoice for the driver for supplies less than 5.5 V, which is thecase in virtually all cell phones today. Additional features suchas over and under voltage protection, thermal shutdown, anddead time (nonoverlapping phase) generation can be included.The driver can generate an arbitrarily large current (1 A) withoutsignificantly impacting stability and efficiency. Also, the driverchip can be directly driven at low voltage since level shiftersare included in the input. Furthermore, the need for trims andvoltage corrections normally associated with analog switchesare eliminated.

Fig. 18. Measured output voltage with tap value and supply voltage at the best(bottom lines), and the worst (middle lines) cases at room temperature. The topdashed line is the ideal case at the worst condition.

E. LC Filter Construction

The all-digital self-adjusting minimum power supply systemincludes a driver connected to PWM modulator drives filter.The filter generates a dc supply voltage on AVS powersupply node in response to a pulse modulated signal PMS. Be-cause the filter is an intermittently unstable system, it is im-portant to choose proper and values. First of all, from themaximum ripple requirement [9], product can be chosen asin (3)

(3)

where is the ripple voltage, is the input voltage, isthe duty ratio of , is the switching frequency, and

is a product of inductance and capacitance. For example,V, V, kHz, and mV,

then required .The next consideration is the minimum oscillation (damped

natural) frequency in (4)

(4)

where is the damped natural frequency, is the inductance,is the capacitance, and is the sum of resistances (switch TR

and ESR). From (4), the minimum condition is expressed in(5)

(5)

The widths of the field-effect transistor (FET) drivers aresized so that from (1). Therefore, . From

and , H and F.

IV. EXPERIMENTAL RESULTS

The fully digital self-adjusting minimum-power supplysystem provides a closed-loop automatic supply adjustment


Fig. 19. AVS supply voltage: (a) soft start of the worst process corner, (b) 50-mV supply voltage fluctuation (top signal) during load transition (bottom pulses)between 65 and 350 mA (1-grid: 200 mV, 1 ms), (c) low to high full swing (0.7 to 1.1 V) of worst process corner sample, (d) high to low full swing (0.9 to 0.6 V)of the worst process corner sample, (e) low to high 4-step swing (120 mV) of the best process corner sample, and (f) high to low 4-step swing (160 mV) of theworst process corner sample (1-grid: 200 mV, 40 s).

mechanism to generate the optimum operating voltage for coreprocessors in response to variations of PVT as well as thoseof frequency and load. The switching frequency of the bufferis 625 MHz. The DPWM resolution is 8 bits, and theoutput voltage resolution is about 12.5 mV. The frequencyinformation from the ADC has a 6 bit resolution (50 mV atworst case) to prevent output voltage-level overlapping due to

ripple and noise. Therefore, the output voltage of the presentedAVS converter can regulate any voltage at ADC resolutionsbetween 0.7 and 1.2 V. The peak ripple is 5-mV minimum.The power dissipation from the AVS controller is 100 at8-bit DAC resolution, which is a significant power reductionfrom the previous digital controller in the prior art [3] that has4.4 mW at 1.3 V. Fig. 17 shows the die photo and layout.


Fig. 18 shows measured output voltages of the sampled chipsfabricated at different process corners (best and worst). It illus-trates the equivalent tap voltages needed to guarantee the samepropagation delay at different corners of a 0.13- process.The slacktime detector is designed to provide a reference delaywith the 1.1 V reference (Ref) tap voltage at the worst processcorner and 135 . The tap voltage required to provide thesame delay at the worst corner (SSS) and the best corner (FFF)at room temperature become 1.025 and 0.8 V, respectively, asshown in Fig. 18. Therefore, the power consumption of the chipfabricated at the best corner is less than the chip fabricated atthe worst corner and operating at room temperature by at least35%. Fig. 19 demonstrates the presented AVS controllers per-formance on load transition, soft start, and frequency transitions.The maximum transition time for full swing is less than 80 .Measured data show that a digitally controlled AVS regulator issuitable for low-power applications that require energy-efficientoperation.

V. CONCLUSION

A fully digital adaptively adjusting high-efficiency supplysystem embedded within a digital system has been described.The presented approach provides a constant minimum supplyvoltage between 0.7 and 1.2 V with the maximum peak rippleof 5 mV, and guarantees less propagation delay than criticalpath delay over changes in PVT, load, and frequency. There-fore, the fully digital technique holds promise as a controller forAVS regulation in digital applications that present a hostile en-vironment for noise-sensitive analog circuits. Moreover, it con-tributes to the yield improvement since the propagation delayvariations due to the variations of intrinsic parameter and oper-ating condition are compensated by dynamically adjusting thesupply voltage.

ACKNOWLEDGMENT

The authors greatly appreciate the help that G. Walker, at theNational Semiconductor Corporation, provided in designing thedemo-boards.

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[9] A. Chandrakasan, V. Gutnik, and T. Xanthopoulos, Data drivensignal processing: An approach for energy efficient computing, inProc. IEEE ISLPED Dig. Tech. Papers, Aug. 1996, pp. 347352.

[10] K. A. Bowman, X. Tang, J. C. Eble, and J. D. Meindl, Impact of ex-trinsic and intrinsic parameter fluctuations on CMOS circuit perfor-mance, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 11861193,Aug. 2000.

[11] A. Consoli, F. Gennaro, C. Cavallaro, and A. Testa, A comparativestudy of different buck topologies for high-efficiency low-voltage ap-plications, in Proc. Power Elect. Spec. Conf., 1999, pp. 6065.

Dae Woon Kang (M03) received the B.S. andM.S. degrees in electrical engineering from YonseiUniversity, Seoul, South Korea, in 1991 and 1993,respectively, and the Ph.D. degree in electrical andcomputer engineering from Northeastern University,Boston, MA in 2003. His Ph.D. dissertation wastitled Low-power digital adaptive voltage controllerdesign based on hybrid control and reverse phasemode.

He was a summer intern for the National Semicon-ductor Corporation in 2002, when he designed a fully

digital adaptive voltage scaling (AVS) controller. He was a summer intern forCompaq Corporation in 2001, when he was involved in developing the latest ver-sion of the Alpha processor. His role was Alphas clock-tree and delay-lockedloop (DLL) analysis and migration to a 0.125-m SOI technology. He was alsoa Senior Application-Specified Integrated Circuit (ASIC) Design Engineer atSamsung Electronics from 1993 to 1998. He developed several ASIC designs.He is currently a Senior Circuit Design Engineer at the National SemiconductorCorporation, Longmont, CO. He has authored several papers and patents, issuedor pending. His research interests include AVSs, DLLs, and low-power digitalcircuits and methodologies.

Yong-Bin Kim (SM00) was born in Seoul, SouthKorea, in 1960. He received the B.S. degree inelectrical engineering from Sogang University,Seoul, in 1982. He received the M.S. degree fromthe New Jersey Institute of Technology, Newark, andthe Ph.D. degree from Colorado State University,Fort Collins, in 1989 and 1996, respectively, both incomputer engineering.

From 1982 to 1987, he was with the Electronicsand Telecommunications Research Institute, SouthKorea, as a Member of the Technical Staff. From

1990 to 1993, he was with Intel Corporation as a Senior Design Engineer andinvolved in micro-controller chip design and Intel P6 microprocessor chipdesign. From 1993 to 1996, he was with the Hewlett-Packard Company, FortCollins, CO, as a member of the Technical Staff involved in HP PA-8000 RISCmicroprocessor chip design . From 1996 to 1998, he was with Sun Microsys-tems, Palo Alto, CA, as an individual contributor involved in 1.5-GHz UltraSparc5 CPU chip design. From 1998 to 2000, he was an Assistant Professor inthe Department of Electrical Engineering at the University of Utah, Salt LakeCity, UT. He is currently the Zraket Endowed Professor in the Departmentof Electrical and Computer Engineering at Northeastern University, Boston,MA. His research focuses on low-power analog circuit design and high-speedlow-power VLSI circuit design and methodology.


James T. Doyle (SM03) received the B.S.E.E. de-gree from the University of Nebraska, Lincoln, NE,in 1972, and the M.B.A. degree from Nova South-eastern University, Fort Lauderdale, FL, in 1992.

He was a Chief Technologist for the CCG Divi-sion of the Intel Corporation, Chandler, AZ. He wasthe Chief Architect of the 3G Mitsubishi AnalogBaseband Chip and also the Technical Lead on theSolano 815 Chip Set project at Intel. He spent 13years in Motorolas Handheld Products Division,Fort Lauderdale, FL, and contributed to the HT, MX

Saber Radio Line. He is presently a Senior Member of the Technical Staff(SMTS) and Chief Technologist of the Nationals Portable Power ProductGroup (PPS). He is currently responsible for CMOS PA controller design atNational Semiconductor Corporation, Longmont, CO. Two national designsare currently being used in TriQuint GSM, GPRS, and EDGE PA modules,which are the smallest in the industry. He is a contributing author to theISO8803.3 Ethernet Standard. He is credited with approximately 50 patentsand has published approximately 10 technical articles, as well as, designed ormodified over 200 chips throughout his career.

Mr. Doyle is a Registered Professional Engineer in the State of Colorado.

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