HIGH PERFORMANCE, ALL DIGITAL RF RECEIVER TESTED AT 7.5 GIGAHERTZ

Jack Wong, Rick DunneganUS Army RDECOM CERDEC S&TCD,

Ft. Monmouth, NJand

Deepnarayan Gupta, Dmitri Kirichenko, Vladimir Dotsenko, Robert Webber, Robert Miller, Oleg Mukhanov, andRichard HittHypres, Inc.Elmsford, NY

ABSTRACT

Wireless applications would be less expensive, moreflexible, and more robust ifthey had more digital andless analog circuitry. The problem is implementingdigital signal processing at radio frequencies.Conventional data converters (ADCs and DACs) anddigital circuits are simply not fast enough, especiallyat SATCOMfrequencies. However, superconductorscan provide ultra fast mixed signal and digitalcircuits with the linearity and dynamic range requiredfor true direct, digital-RF processing. Thesesuperconducting circuits are digital ICs based onJosephson junctions and "rapid-single-flux-quantum"logic (RSFQ), where simple circuit switching speedsup to 750 GHz have been demonstrated. This permitsdirect conversion between analog RF and digitalbaseband signals, replacing frequency and protocol-specific analog hardware with flexible digitalprocessors. HYPRES recently developed anddelivered an X-band All Digital RF Receiver (XADR)prototype system for the US Army CERDEC and PMDCATS. The concept of this ADR is to replace theentire analog RF receive chain between the antennaand the baseband demodulator with a highperformance digital RF equivalent. The first XADRprototype system has been successfully demonstratedat the Joint SATCOM engineering Center (JSEC).End to end link testing, over the satellite has beensuccessfully completed using an existing ANIGSC-39X-band earth terminal, an XTAR satellite, the X-bandADR and a SATCOM modem.

INTRODUCTION

Future military and commercial radio frequency (RF)systems demand better utilization of the RF spectrum,moving towards higher frequency, greater bandwidth, andgreater flexibility to accommodate diverse modalities (e.g.voice, data, video, detection and ranging, electroniccountermeasures). This requires extension of digital

processing to the traditionally analog RF domain.Superconductor rapid single flux quantum (RSFQ)electronics, featuring ultrafast digital logic and high-linearity analog-to-digital converters, allows directconversion of RF signals and digital processing of thedigitized RF signal up to SATCOM frequencies [1].Recently, a family of digital-RF receivers (called ADRs),comprising an oversampled delta or delta-sigma modulatorperforming analog-to-digital conversion and a digitalchannelizer circuit performing digital down-conversionand filtering, have been realized using superconductorintegrated circuit technology [2]. Among these, the onewith the highest input frequency is the X-band digital-RFreceiver (called XADR).

Until now, these ADR chips were tested in the laboratory,primarily by immersion in a liquid helium dewar, andevaluated with input signals generated from test equipment.We have built a complete system prototype by integratingthe XADR chip with a commercial cryogen-free closedcycle refrigerator (called cryocooler). Here, we report thefirst demonstration of this superconductor digital-RFreceiver prototype with live X-band satellite signals at theJoint SATCOM Engineering Center (JSEC).

X-BAND DIGITAL-RF RECEIVER

Direct digitization of X-band SATCOM signals isperformed by a single 1-cm2 superconductor integratedcircuit, called the XADR chip (Fig. 1).

Digital Mixer-

Band passDelta-Sig ma

ADC Modulator

External Clock-

Clock Divider

OutputAm plifiers

DigitalDecimation

Filter (I)

DigitalDecim ationFilter (Q)

Fig. 1. Single-chip digital-RFX-band receiver (XADR).

1-4244-1513-06/07/$25.00 ©2007 IEEE I OF 5

Digital Channelizer Jutpul)Output Amplifiers

fd= Digital DecimationFilter

Digital I- gaIQ Mixer fLQ Lo

cccf Digital Decimation

n CCO Filter1/2n f fd= |fIf

:I Output Ampier- - - - - - I - - -

Fig. 2. Block Diagram ofthe XADR chip.Based on this XADR chip, we have developed a satellitecommunication digital receiver demonstrator. The chip iscooled by a commercial two-stage closed-cyclerefrigerator (Sumitomo SRDK-100) to about 4 K. The chip(Fig. 2) comprises a bandpass second-order delta-sigmaanalog-to-digital converter (AZ ADC) circuit, and a digitalchannelizer circuit, both clocked by a common high-frequency clock (fclk). Analog RF input is applied directlyto the AZ ADC modulator, and is converted into anoversampled single-bit data stream. The channelizer circuitdigitally down converts and filters this digital-RF datastream to produce a pair of digital in-phase (1) andquadrature (Q) words at a reduced (decimated) outputclock rate of fd =fc/k!2', where 2' is the decimation ratio.Digital I and Q mixing is performed by multiplying theADC output by two digital local oscillator streams withexactly 90° phase difference, derived from the ADCsampling clock. In this design, the local oscillatorfrequency is 1/4th of the clock frequency. The multi-bitdigital I and Q outputs of the decimation filters areamplified to about 2 mV with a set of on-chip drivers. Thechip consumes less than 4 mW of power, far less than thecooling capacity (200 mW @ 4.2 K) of the commercialcryocooler.

These mV-level digital I and Q outputs, along with thecorresponding clock signal (fd), are amplified by a set ofcustom-designed high-gain amplifiers to about 3.3 V. Thesignals are then acquired using a commercial circuit boardwith field programmable gate array (FPGA) chips. Wehave built a programmable data acquisition interface thatcan also function as a second-level channelizer forextraction of sub-bands. In addition to acquiring the digitalI and Q data, the interface board permits their transfer toany back-end signal processor, such as a digital MODEM.The block diagram of the XADR demonstrator unit isshown in Fig. 3.

Graphical External ToUser Digital l&Q * Digital

Interface Interface + Modem

Data Acquisitionand ProcessingBoard (FPGA)

Interface AmplifiE

Output tQClocklil

itI I

DCBrs

DC Bias Current

RF Input-External Clock-

Cryocooler TemperatureMonitor

Fig. 3. Block diagram ofthe XADR system prototype.

SUPERCONDUCTOR BANDPASS DELTA-SIGMAANALOG-TO-DIGITAL CONVERTER DESIGN

A bandpass ADC was chosen to minimize the quantizationnoise in the band-of-interest (7.25-7.75 GHz). The ADCmodulator is a continuous-time bandpass delta-sigmamodulator with two lumped LC resonators. In thisimplementation of the bandpass ADC, the first and thesecond resonators were designed to be 7.4 GHz and 7.6GHz respectively. The quality factor of the resonator wasestimated to be around 100. We introduced a string ofjunctions as a tunable inductor for possible tuning of theresonant frequency, but did not use it in this test.

One of the unique features of the superconductor delta-sigma ADC modulators is implicit feedback: when thebottom junction (J2) of the two-junction clockedcomparator switches, it subtracts a single flux quantum(SFQ, (Do = 2.07 fWb) from the input while producing adigital output SFQ pulse. Therefore, no explicit feedbackloop is needed to construct a first-order ADC modulator. Asecond-order modulator was designed to improve signal-to-noise ratio (SNR) by further suppression of quantizationnoise. Fig. 4 and Fig. 5 show a block diagram and thecorresponding schematic diagram of our second-orderADC modulator. The feedback path includes Josephsontransmission lines (JTLs) as active delay elements inaddition to a D flip-flop to control the phase of thefeedback signal.

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RFIn put

| Am plifier+ - Resonator2 +pT

Clock

;7 ComparatorI_

Implicit Feedback

tT

-C Clock

2nd-order Feedback IDigitalOutput

Fig. 4. Block diagram of the second-order bandpass D1ADC modulator.

RFInput

-F+

Clock

Resonator 1

JTL

.

Amplifier

2nd-order Feedback

ii/~.'.9

J2>\Fw

J

T

T ~~~~~LODJTL I- Clock

DigitalOutput

Fig. 5 Schematic diagram of the second-order bandpassDS ADC modulator.

In its simplest implementation, the clock frequency for abandpass AZ ADC is chosen to befk= 4fo, where fo is thecenter of the band-of-interest. For X-band, this clockfrequency is about 30 GHz. One can also use a lower clockfrequency with some performance penalty. In this scheme,called RF undersampling, we take advantage of thesampling process that replicates the input analog frequencyband, centered at fo, translated by multiples of thesampling frequency (fclk). In general, the sampled spectrumconsists of an infinite number of band replicas at

+fo nfclk, where n =0, 1, 2, ..., but we are primarilyinterested in the first Nyquist zone 0 <f<fc.k/2. Forfck >fo> fc. /2, the band center is shifted from fo to f/ck - fo.We will then need to apply a digital local oscillator at thatfrequency (L/ = fck -fo) to mix it down to baseband.Furthermore, the local oscillator should be a submultipleof the clock frequency to prevent unwanted mixer artifacts,preferably by a factor divisible by 4 to ensure convenientgeneration of in-phase and quadrature components. Underthese constraints, the clock frequency is given by fc/k -

fo =fclk4, or/clk=4fo13, which for X-band is about 10GHz. We designed two versions of the XADR chip, forfabrication using our first-generation (1 kA/cm2) and

second-generation (4.5 kA/cm2) processes, for target clockfrequencies of 10 GHz and 30 GHz respectively.

DIGITAL-RECEIVER DEMONSTRATIONIn collaboration with L-3 Communications, we havesuccessfully interfaced the superconductor X-band digital-RF receiver with L-3's 3rd generation digital modem,which was specially configured to accept and demodulatedigital I and Q digital data. The complete receiver systemdemonstrator unit was tested with live satellite signals atHYPRES first, and then at the Joint Satellite EngineeringCenter (JSEC) in Ft. Monmouth, NJ, where it receivedsignals from the XTAR satellite at the GSC-39 terminal.

XTAR Satellite8326MHz Waveguide \/

FrequerncypUponverter s Combiners HPA7676 MHz

11i Transmitter 11-m Dish WaveguidePatch Panel Room AN/GSC-39

RF Splifter

TAttenuators

T

70 MHz 1'

L-3 CommunicationsSatellite ModemModel 3501-01

Mod ul ator + Rou ter

L-3 CommunicationsLaptop

(Data Transmitter aridDisplay)

L-3 CormmunicationsLaptop

(Data Receiver andKDisplay)

t UDPClock L-3 Coimunications Clk

-3Cornmmunication s <Gen3DigitalSatellite XRouter ModeModem

lDemodulated Demodulator 3Data P

A-bancU uIgIlal-Kr Keceiver

Fig. 6. Configuration for the X-band Digital-RF.

The setup for the demonstration is shown in Fig. 6 above.We started by generating a data enriched RF stream,originating from a typical user data stream from acomputer feeding into a modulator through a typical router.We chose an uncoded binary phase shift keying (BPSK)modulation onto a 70-MHz intermediate frequency (IF)carrier at a modulation rate of 1544 kbps (TI). From there,the signal was injected into a two-stage frequency up-converter. The first stage heterodyne mixer performedmixing of the 70 MHz (modem output) with an internallyoscillated 630 MHz, producing the sum (700 MHz) and thedifference (570 MHz) frequencies in addition to frequencycomponents at the inputs of the mixer. The signal was thenband pass filtered to allow only the sum (700 MHz) tocontinue. The signal then traversed to another heterodynemixer that again produced the sum, the difference and thetwo original inputs but having one primary difference: theinternal oscillating input for this second stage mixer wastunable ranging from 7.2 GHz to 7.7 GHz with the filteredoutput ranging from 7.9 GHz to 8.4 GHz. From here theanalog signal is data enriched X-band. For our test, wechose the center frequency to be 8326 Mhz.

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L-

L-

The modulated X-band RF signal was amplified to highpower using a traveling wave tube (TWT) amplifier. Theamplified signal then traversed a low-loss waveguide to anantenna, with an effective gain of 57 dB, and was radiatedto space with a circular polarization. The loss to thesatellite, approximately 22,380 miles away, is 202 dB. Onthe satellite, the signal was amplified, frequency shifteddown by 650 MHz, to a range of 7.25 to 7.75 GHz, andamplified again before being transmitted back down toearth. Departing the satellite, the signal underwent circularpolarization again and another 202 dB of loss. The signalwas collected by the 57 dB gain aperture much in the samefashion as it was transmitted except its lower frequencyand opposite polarization. Immediately upon arrival, thesignal was amplified by a 73 dB low-noise amplifier(LNA). The signal then traversed more waveguide to abank of RF splitters and a set of fixed and variableattenuators before being applied to the X-band digital-RFreceiver. For our chosen carrier, the input RF signal wasfo= 7676 MHz.

The XADR chip sampled the 7.676-GHz analog RF inputdirectly with an applied/f/k 4fo /3 = 10.234667 GHz, anddigitally down converted down to baseband. Thedecimation filter ratio was 256, and consequently, theoutput (decimated) clock rate was fd = f/Ik!256 = 39.98MHz. The output digital I and Q data at 39.98 Msample/swere amplified and passed through the FPGA dataacquisition board and interface to the L-3 digital modem.Upon demodulation, the signal was passed through therouter in its packet form to be acquired and displayed bythe destination computer. We also acquired the data fromthe data acquisition and processing board and performed

(SFDR) over the 40 MHz band with a single-tone RF inputsignal. In addition to testing with pseudo-random patterns,we demonstrated the XADR system with live transmissionand reception of a video file. The spectrum (Fig. 8) showsthe digitally down-converted signal-of-interest on eitherside off= 0.

During this demonstration, there were othercommunication signals present in the same band. Theclosest in frequency was a transmission centered at 7679MHz, from GSC-39 to a small mobile terminal, with 10 dBmore power than our signal-of-interest. These signals werealso digitized by the XADR chip, and could be extractedfrom the same digitized data using a set of second-levelchannelizers [2]. In other words, the ADR permitsextraction of multiple sub-bands from a broad digitizedband. Also, the XADR chip supports much higher datarates than the 1.544 Mbps used for the live demonstrationbased on available satellite bandwidth. In the laboratory,we have digitized X-band carriers modulated at rates up to6.5 Mbps, limited by the available modulator equipment.

0 ±fdI2 0

Normalized Frequency (f/fd)

1.544 Mbps with a packetized video file. The XADR alsocaptured other signals in the same transmitted band, at7.679 and 7.684 GHz respectively. The clock-frequency is10234.667 MHz.

0 ±fd/2 0

Normalized Frequency (f/fd)

Fig. 7 The graphical user interface displays the spectraof the digital I (top left) and Q (top right) outputs shownalong with that ofI+jQ (bottom).

Fig. 7 shows the performance of the XADR chip in termsof signal-to-noise ratio (SNR) and spur-free dynamic range

We also noted that the level of noise received from theantenna was significantly higher (by about 20 dB) than theADC quantization noise floor. We estimated the totallosses between the receive LNA and the RF input port ofthe cryopackage unit to be 70-72 dB. This does not includethe RF cable loss inside the cryopackage, between theinput port at room temperature and the 4-K chip, whichwas not minimized to keep the conductive heat load on thecryocooler low. Therefore, we expect that this XADRsystem could be placed directly behind the antenna,eliminating the need for amplification.

Finally, better performance is expected from an XADRchip clocked at higher frequency. Fig. 9 shows thespectrum of a 7.653 GHz RF input signal that has been

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digitized at fclk=4fLo = 30.592 GHz and digitally down-converted to 5 MHz. The decimation ratio is 256 and theoutput sampling rate is 119.5 MHz. Compared to theresults obtained with 10 GHz clock, both SNR and SFDRare higher over a larger bandwidth.

m-

a1)0~

N

m0z

software-defined platform from RF to baseband. In termsof increased capability, this will allow us to haveprogrammable and flexible multi-band multi-modecommunications across multiple satellite transponders ordifferent satellite payloads simultaneously. In terms ofincreased performance, this will allows us to have greaterG/T improvement on the receive-side and greater powerefficiency on the transmit side, due to the intrinsic lownoise temperature and direct digital-RF processing usingsuperconducting digital circuits. In terms of programacquisition and logistic cost, this will eliminate multipleracks of legacy equipment, such as, IF cablings, analog RFswitch panels, analog IF up/down converters, and analogIF modems. Fig. 10 below shows the concept of the multi-band All Digital-RF transceiver architecture for futureSATCOM earth terminal.

0 Normalized Frequency (f/fd)

.r~~~~~~~~~~~~~~~~~~~~~~~~~~~I 'T ...F

I~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11>TdiL

Fig. 9 Spectrum of the digitized output from an XADRchip clocked above 30 GHz. The applied analog inputsignal is 7.653 GHz.

CONCLUSIONWe have developed and demonstrated a complete digitalreceiver prototype system, featuring direct digitization ofX-band Military Satellite Communications(MILSATCOM) signals. A superconductor integratedcircuit chip, consisting of a bandpass delta-sigma ADCmodulator and a digital channelizing circuit both clockedabove 10 GHz, was used to convert RF signals in the 7.25-7.75 GHz range to digital and perform down-conversionand filtering completely in digital domain. This systemwas interfaced with a MIL-STD-188-165A modem, andwas used to demonstrate live data and video traffic in anexisting Army Earth Terminal, i.e., AN/GSC-39 terminalover a live Satellite link. It has achieved initialTechnology Readiness Level (TRL) 6 capability byoperating in a relevant environment. More testing will beperformed in the near future when the optimized version ofthe XADR chip to be clocked at 30 GHz is ready forsystem integration.

The X-band ADR concept is just a first stepping stonetoward an All-Digital-RF Transceiver (ADT) architecturefor future SATCOM Earth Terminals. The overall goal ofthe ADT is a true software-defined SATCOM EarthTerminal, which will provide direct RF digitization of thewhole satellite payload bandwidth for all incoming signalcarriers from the antenna and consolidate all digital-RFdistributions from the antenna into a single all-digital

Band-1 VIuADC

Band-2A,DC2

Band-m -

r... ......

ADC

Band 2P-Pedistotert _IDAC I

P-Predistorter

Band-m

m - ID0ACM

Fig. 10 Multi-band,architecture.

Digital Channelizer Unit I

Digital l&Q Digital l&Q- Down Decimation

Converter Filter

Digital Channelizer Unit n

Digitall&Q Digital l&QDown Decimation

Converter Filter

D ig tal Transmitter Un it IDigital l&Q Digital l&Q

- Up InterpolabonConverter Filter

D ig tal Transmitter Un it h- Digital l&Q Digital l&Q

Up - InterpolabonConverter Filter

multi-channel digital-RF receiver

ACKNOWLEDGMENTThe work was supported in part by CERDEC SmallBusiness Innovation Research (SBIR) Contracts, and bythe Project Manager Defense Communications ArmyTransmissions System (PM DCATS). The authors thankMr. John Deewall for his encouragement and support.

REFERENCES[1] 0. A. Mukhanov, D. Gupta, A. M. Kadin, and V. K.

Semenov, "Superconductor Analog-to-DigitalConverters," Proceedings of the IEEE, vol. 92, pp.1564-1584, Oct. 2004.

[2] D. Gupta, T. V. Filippov, A. F. Kirichenko, D. E.Kirichenko, I. V. Vernik, A. Sahu, S. Sarwana, P.Shevchenko, A. Talalaevski, and 0. A. Mukhanov,"Digital channelizing radio frequency (RF) receiver,"IEEE Trans. Appl. Supercon., June 2007, to bepublished.

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