H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba, T.Takashima, T.Takahashi, H.Tomita JAXA

May 17-20, 2006 6th FEE meeting @Perugia, Italy 1

Front-end circuit with deep-submicron FD-SOIHirokazu Ikeda

[email protected] of space and astronautical science

Japan aerospace exploration agency

Y.AraiA, Y.IkegamiA, H.UshirodaA, Y.UnnoA, O.TajimaA, T.TsuboyamaA,

S.TeradaA, M.HazumiA, K.HaraB, H.IshinoC, T.KawasakiD, G.VernerE,

E.MartinE, H.TajimaF

KEKA, U.TsukubaB, TITC, Niigata UD, U. HawaiiE, SLACF

H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba,T.Takashima, T.Takahashi,H.TomitaJAXA


　 Employing a 0.15-um fully depleted SOI process from OKI, we are developing front-end circuits for radiation detectors in collaboration with JAXA, KEK and related universities. SOI devices are free from parasitic PNPN structure, and, hence, intrinsically immune to the single event latch-ups. Moreover SOI devices are located on a very thin silicon layer,the energy deposit by impinging 　particle is relatively small, and, then, the single event upsets and/or single-event transients are manageable with an appropriate design strategy. Utilizing these benefits, space agencies have been employing SOI devices for their spacecrafts. The application area has been, however, virtually restricted in data processing and telecommunications.

Abstract

When designing front-end circuits with the FD-SOI, we can take benefits such as small floating-body effect, superior sub-threshold characteristics and small temperature coefficient as well as common nature of SOI devices, i.e. small parasitic capacitance, low junction leakage, decrease in substrate coupling noise, and reduction of silicon area. In order to confirm these benefits and to identify possible issues concerning front-end circuits with FD-SOI, we have submitted a small design to OKI via the multi-chip project service of VDEC, the university of Tokyo. The design includes charge sensitive preamplifier circuits with exponential and linear decay configurations, and a trans-impedance amplifier with an active feedback configuration. There also included are comparators with a limiting amplifier scheme. The initial test results and future plan for development are presented in this talk.


Team organization

Possible application forSuper-B, SLHC, ILC andmaterial science

Y.AraiA, Y.IkegamiA, H.UshirodaA, Y.UnnoA, O.TajimaA, T.TsuboyamaA,

S.TeradaA, M.HazumiA, K.HaraB, H.IshinoC, T.KawasakiD, G.VernerE,

E.MartinE, H.TajimaF

KEKA, U.TsukubaB, TITC, Niigata UD, U. HawaiiE, SLACF

H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba,

T.Takashisma, T.Takahashi,

H.TomitaJAXA

Possible applicationfor solar system exploration,and deep-space observation

JEM/ISS


Contents for talk

1. Introduction2. TEG fabrication3. Circuit and operation4. Towards radiation-hardness assurance5. Conclusion


1. Introduction

・ Full dielectric isolation: Latchup free, Small area・ Low jucntion capacitance: High speed, Low power・ Low leakage, low Vth shift: High Temp. application・ High soft error immunity: Rad-hard application

Entering into late 1990's, the trend curve of a bulk CMOSprocess tends to go behind the Moore's law, and, hence, the manufactures are eager to find a way to recover development speed.

There exists a general trend :Post-scaling technology…..SOI/SOS, strained-Si,3D-tr, Cu, High-k, Low-k…..

SOI CMOS is then revisited toreveal its performance over an existing bulk CMOS; the SOI CMOS eventually shows up as a successor of the CMOS process inheriting well-matured fabrication technologies for a bulk CMOS.


FD-SOI

DepletionLayer

Kink effect


2. TEG fabrication

4,5,6 inch wafer,CMOS/Bipolar 6,8 inch wafer

Mass production

Research

VDEC route(0.15 um) VLSI design & education center,

The university of Tokyo

JAXA/MHI route(0.2 um)

c/o K.Hirose

KEK route(0.15 um W/ pixel implant)

c/o Y.Arai

ISAS, JAXA

0.15-um FD-SOIProcessed by Oki Elec. Ind. Co., LtdSOI: 50 nm, BOX: 200 nm, 6”wafer(UNIBONDTM,SOITEC)Vdd: 1.0 V(core)/1.8 V(I/O), Vth: 0.18(n)/-0.25(p) for LVTMetal: 5-layers, Capacitor: MIMOption: Thick metal for inductors


2.4 mm

Charge amplifier

TOT amplifier-1

TOT amplifier-2

Trans-impedance amplifier

In order to identify possible issues when appliedfor analog FE circuits…….


3. Circuit and operation

nMOS (LVT) inputId=100-500 uAW/L=5/0.5 M=360Cox*W*L=12.5 pFgm= 11.5 mS


Short decay

Long decay

The leakage current of the FBcircuit determines the slowest decay.

Chain1


Shot noise dominant

Adjustment to balanceleakage current

nchl,pchlnchv,pchv

Noise slope is too large!200 mV

500 mV

Good dynamic range



4 fC40 fC

Chain2


18

Pulse width is sensitive to the leakage currentassociated with the ESD pad!

The leakage current is adjusted by moving the VSS voltage for the ESD pad.


4 fC

Small overshoot40 fC

Chain3

Small overshoot as expected


Large dynamic range


-8 fC

8 fC

Chain4

D/A interference is very severe.


Total dose:radiation hard? Not necessarily the case for gate edge and/or BOX.H-gate, Enclosed gate: ready to useDouble gate: No effect from BOX

4. Towards radiation-hardness assurance

Single event(SEU,SET): radiation hard? Not necessarily the case.

TCAD 　 simulationis in progress


As a first step…..DUT

DUT


5. Conclusion

1) FD-SOI 　 analog front-end circuits are examined under a joint effort of JAXA , KEK and related institutes as a part of the SOI-pixel detector development and/or future solar system/deep-space exploration.2) The FD-SOI TEG circuits are proved to work even with very low Vdd voltage thanks to stable low threshold transistors.3) Minor issues are identified, and fixed to be submitted to the second MPW run. 4) Radiation hardness is still an issue to be examined carefully in terms of total dose and single event.5) Road-map for the SOI technology is on the way of the post-scaling technology, which conforms with application in a harsh environment in space and high energy physics.

Documents

H.Ikeda, K.Hirose, H.Hayakawa, Y.Kasaba, T.Takashima, T.Takahashi, H.Tomita JAXA