Hiren Majmudar - SiFive · 12/3/2019 · Hiren Majmudar VP Corp Biz Dev Sunil Shenoy SVP, GM RISC-V BU Jeff Mulhausen Chief Evangelist Thomas Xu CEO, SiFive China The SiFive Management

1PageCONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Hiren MajmudarVP, Corporate & Business Development & Israel Country Manager


September 2019

Company Overview


SiFiveGlobal Presence and Reach

CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Worldwide Presence

o 15 Global Sites o 490+ employeeso 300+ tapeouts

San Mateo, CABoston, MA

Tel Aviv, Israel

Pune, India

Bangalore, India

Kaohsiung, Taiwan

Yokohama, Japan

Milpitas, CA Austin, TX

World Class Expertiseo Inventors of RISC-Vo Silicon as a Serviceo SOC IP, PD, RTL, FPGAo Verification, Validation

Shanghai, China

Beaverton, OR

Seoul, South Korea

Marseille, France

Hsinchu, Taiwan


TeamInventors, Founders, Industry Leaders


Shafy EltoukhySVP, GM Silicon BU

Yunsup LeeCTO

Naveed SherwaniCEO

Mohit GuptaVP, IP BU

Krste AsanovicChief Architect

Andrew WatermanChief Engineer

Hiren MajmudarVP Corp Biz Dev

Sunil ShenoySVP, GM RISC-V BU

Jeff MulhausenChief Evangelist

Thomas XuCEO, SiFive China

The SiFive Management Team combines the inventors of the RISC-V ISA with seasoned industry executives.

Brandon ChoCEO, SiFive Korea

Jack KangSVP, CX

Jay VyasCFO

Megan WachsVP Engg

Jaspi SandhuVP Sales


TimelineFrom Invention to Today


Raven-1Raven-2

Raven-3

Raven-3.5

EOS14 EOS16 EOS18 EOS20

EOS22

2011 2012 2013 2014 2015

May Apr Aug Feb Jul Sep Mar Nov

2010

May

StartedRISC-V Project

Jul Aug

2016 2017

Nov Oct

Freedom UnleashedMulticore Linux

Freedom EverywhereShipping in 60+ Countries

Started Development of RISC-V Core Generator

Foundation

2018 2019

$125M Raised

125 Design Wins

SiFive E3 in Amazfit

COPYRIGHT 2019 SIFIVE. ALL RIGHTSRESERVED.6

SiFive RISC-V Core IP Product Series

High performance 64-bit Application Cores

SBC

Networking

ConsumerOptimized High-Performance

Low Cost Linux

Industrial

GatewaysMulti-Core RISC-V Linux

Industry leading 32-bit and 64-bit Embedded Cores

Storage

Networking

AutomotiveHigh Performance Embedded

Industrial

Modems

StorageSmall, Efficient, Performance

Microcontrollers

IoT

WearablesSiFive’s Most Efficient Series S21 >125 Design wins


September 2019

The RISC-V Revolution


AcademicAdoption


• RISC-V architecture and implementation are already taught/researched at UC Berkeley, Stanford, MIT, Technion and other top universities

• The next cohorts of engineers will enter the job market knowing RISC-V


Industry and NationalAdoption


• ISA appropriate for all levels of computing systems, from MCU’s to supercomputers

• Large companies are adopting RISC-V for deeplyembedded controllers in their SoCs

• >35 silicon companies have embraced RISC-V

• NVIDIA has publicly announced that all future GPUswill use RISC-V

• Western Digital publicly announced their transitionof all 1 billion+ cores per year to RISC-V

• India has adopted RISC-V as its national ISA

• US DARPA has mandated RISC-V in recent securityproposals


RISC-V Ecosystem Momentum: Phenomenal



September 2019

Current Challenges

12

Why RISC-V, Customization and Verticalization?

Moore’s Law Has StalledGeneral-purpose CPU performance (vs. VAX-11/780)

Customization is the only way to get performance01

Innovation is desperately needed to meet the needs of new applications running on billions of devices

03

One-Chip-Fits-All no longer applies02

Time for a Paradigm Shift

13

In hardware, Minimum Viable Products (MVPs) face 3 Significant Problems

Cost

Chip Development Too Costly

$500M+ for 7nm

Time

Development Cycle Too Long

2 – 4 years

Expertise

Too Many Experts Needed

14+ Disciplines


September 2019

Industry Trends

15

Intelligence is Migrating to the Edge

AI Edge Device Shipments by Category, 2017-2025

Source: Tractica

Cloud serversEdge Compute

Regional serversEdge devices

Training +inference

Training +inference

Sensing, training, inference & actuation

AI moving from Cloud to Edge

Processing closer to data improves latency, bandwidth,energy use and reduces stress on network

16

So is the money: Investment deal flow for two specific semiconductor applications — IoT and AI/ML

Source: Pitchbook

25%

20%

15%

10%

5%

0%2009 2010 2011 2012 2013 2014 2015 2016 2017 2018

Perc

enta

ge o

f to

tal d

eals

2.4%1.2%

2.3%

4.8%3.5%

2.6%2.8%

6.8%

13.2%

19.2%

AI/ML IoT

8.9%7.1%

10.5%

12.7%

9.2% 9.6%

12.6%

17.8%

11.5%

12.5%

17

Inference at Edge & End-points Has Been Expanding

Inference at Edge & End-points

(On-Device AI)

Low-Power, Low Cost and Low

Latency

Trade performance for cost

Compressed models to reduce

system cost and power

Reduce energy use and stress

on Network

Cloud-based Inference:

Latency, throughput, cost

Serve user requests fast and

predictably

Keep cost/user down

Cloud-based Training:

Performance, Performance, and

More Performance

Value in data models justifies high

cost & power

State of the Arch Tech, advanced

node, interconnects, cooling

18

RISC-V in Design Across Various Markets…Si

lico

n

7nmLinux & Embedded RISC V

HBM2, Interlaken2.5G Interposer

Customer IP

14/16nmLinux & Embedded RISC V

LPDDR, PCIe Gen4 100G Ethernet

Customer IP

14/16nmLinux & Embedded RISC V

LPDDR, PCIe Gen3HEVC, ISP, GPU, 1GE

Customer IP

28nm Embedded RISC V

Non Volatile MemoryEmbedded FPGA

Customer IP

MCUs& Wearables

A-IOT Edge Inference DC Training/Inference

19

The Opportunity

20

The Silicon Business is Ripe for Disruption!

Moore’s Law is stalling, and customization is the only path forward for improved performance

And yet, the hardware innovation cycle is too slow, too expensive, and require too many experts under the same roof

We are leading the charge on enabling a new era of processor innovation with a free and open instruction set architecture

RISC-V

We are simplifying the custom silicon design process by encapsulating the complexities in Templates

Custom Silicon

We are empowering Software and Systems innovators with easy access to Templates via Designers on the cloud

Verticalization

21

RISC-V ISA is ideal for Domain Specific Architecture

Legacy ISA’s Are Decades Old

RISC-V ISA is Open Source

RISC-V Unlocks the Architecture & Enables Innovation

Why RISC-V?

Source: Martin Fink, CTO, WDC

Benefits of RISC-V?

CleanSlate

DesignModular

StableSimple

Designed forExtendibility/Specialization

22

AMAZFIT Smart Watch 2 w/o ECG

AMAZFIT BIP Watch

E3 core inside

AMAZFIT Smart Watch 2 w/ ECG

RISC-V Enabled Smart Watch with Integrated AI

• Multiple AI Engines for Fitness Applications• RISC-V based Always-on Architecture • 38% better power efficiently vs. ARM Cortex-M4

23

One Size “Silicon” Does NOT Fit All

End Point Edge Cloud

Earphone Always-on IOT

Smart Phone

Access Control

AR/VR, Drones

Surveillance

Laptop,

Desktop

Industrial PC

ADAS

Edge Server,

Autonomous

Data Center

20 MOPS 500 GOPS 0.5-10 TOPS 4-20 TOPS 10-20 TOPS 10-100 TOPS 200+ TOPS

1 mW 10 mW 1-3 W 3-10 W 3-10 W 10-100 W 200+ W

10 KB 100 KB 10 MB 10-100 MB 10-100 MB 100+ MB 300+ MB

<10ms ~ 10 ms 10-50 ms 10-100 ms 10-100 ms 10-100 ms > 500ms

Y Y Y Y Y Y Y

N N Y Y Y Y Y

28nmRISC V

Non Volatile MemoryComplex Power Gating

10/12, 14/16nm RISC V

1xLPDDR x32, PCIe x1/x2ISP, GPU, 1GE

10/12, 14/16nmRISC V

4x LPDDR, PCIe x8/x1610-100G, Compression

5/7nmRISC V

HBM2, Interlaken2.5G Interposer

Power Budget

Application

Compute

Model Size

Latency

Inference

Training

SiFive Silicon Enablement

24

Why Another Model for Chip Design

Wafer Fabrication

Product Requirement &

Specification

Physical Design

Test & Prod Engineering

Package & Assembly

Architecture Analysis,RTL Design & Verification

IP Development, Selection & Integration

Board Design

FPGA & EmulationSoftware Design, Development &

Test

Post Silicon Validation &

Software Bring-up

Challenges with traditional SoC model:

1. Long IC development cycles often lead to missing opportunity window

2. Designers “re-inventing the wheel” on many aspects of chip design which are generic/standard

3. Business and Legal teams waste long periods of time over contract negotiations

Typical Cycle ~ 3 years


The SiFive Solution: Template SOCsSeptember 2019

26

How SiFive Can Enable Next Generation Computing

RISC-V CPU IPM

icro

-co

ntro

ller

up

to

Ap

plic

ati

on

Pro

cess

or

wit

h o

ne

com

mo

n IS

A

64-bit Application Processors

64-bit Embedded Processors

32-bit Embedded Processors

Ind

ust

ry’s

Bro

ad

est

RIS

C-V

CP

U P

ort

folio

Cloud-Based CSoC & Templates

Inn

ova

tive

Ch

ip D

esig

n f

or

Fast

TTM

Foundational IP

RISC-V Cores

Design Automation & Cloud resources enabling chip delivery in 12 Weeks !

Custom SoCs(Traditional ASICs)

Turn

key

Cu

sto

m S

oC

So

luti

on

s

Physical Design

Package & Assembly

IP Dev, Selection & Integration

Board Design

Software Design, Development & Test

Chip bring-up

Product Req. & Specifications

Test & Production Engineering

Wafer Fabrication

Arch. Analysis, RTL Design &

Verification

FPGA & Emulation

Post Silicon Validation

300+ Tape-outs!

27

Traditional Approach: Iterative Addition

Build individual building blocks and add them to a chip

The SiFive Approach:Iterative Subtraction to Reconfigure Cores, Blocks, and Chips

Subtract from Templates (Predesigned Supersets)

Templates

Diplomacy Protocol

Template Methodology used acrossCores, Blocks and Chips

Block Templates

Core Complex

TileLink Interconnect

HBM Controller

Core Templates

E2 Series

E3 Series

U7 Series

Chip Templates

AI accelerator

SmartNIC

IoT Hub

U54 Core Complex

Tilelink over Ethernet

Custom HBM

E20/E21

E31

U74

Custom AI Chip

Optimized NIC

Voice IoT Hub

We Simplify the Design Process by Encapsulating Complexities in Templates

28

SiFive Leverages Cloud & Templates to Accelerate Chips to Market!

World’s 1st Cloud Tape-out with Microsoft

28nm TSCM1.5GHz 5x RISC-V CoresDDR4, GE, Peripherals

…

Machine Learn-ing Segment

EdgeSegment

IoT Sensor Segment

DesignShare Partners20+ in the Pipeline….

29

All RISC-V core products are delivered via web-based GUI SiFive Core Designer

Customers can choose preset Standard Core options or create and save their own configurations

Release Candidates are generated with a single click and available in 24 hours after verification

Ultimately, all custom silicon will be delivered via web-based GUI SiFive Chip Designer

Customers can add their IPs and 3rd party IPs from DesignShare to a Chip Template of their choice

Custom SoC will be in their hands in 12 weeks with a single click

Cloud Delivery: Core Designer & Chip Designer

30

Cloud Delivery: Core Designer & Chip Designer

Core Designer

Chip Designer (Templates)

Standard CoresE21E24

Custom CoreCustomer Core 1Customer Core 2

IOT Template

Edge Compute

Computer Vision

Standard InstantiationReal SoC !

Custom InstantiationDerivatives

31

SiFive Platforms Reduce Cost and TTM for Customers

Embedded AI Platform Edge Computing & Storage Data Center Accelerator IOT

SiFive IP & Platforms

• SiFive IP Blocks for Platform Designs

– Industry’s Broadest Portfolio of RISC-V Cores & Peripherals

– Various Templates for Different Markets

– Design Share IP Partners Supplying IP blocks for Templates

– Ability to customize for differentiation

– Attractive Economics and TTM Advantage


In SummaryOpen standards and automation is unshackling silicon innovation

Industry needs new methods to do rapid custom silicon

SiFive is leading with auto generated CPU cores, Template based cloud enabled SOC design while also supporting traditional ASIC customers

Its not too late to join RISC-V movement! Come talk to us.

Documents

Hiren Majmudar - SiFive · 12/3/2019 · Hiren Majmudar VP Corp Biz Dev Sunil Shenoy SVP, GM RISC-V BU Jeff Mulhausen Chief Evangelist Thomas Xu CEO, SiFive China The SiFive Management