How to design an ASIC: a case study for the BLM project

How to design an ASIC: a case study for the BLM projectLuca Giangrande

11/12/2019

12/10/2019 1Luca Giangrande | How to design an

ASIC: the BLM case study

Part 1 : ASIC DESIGN FLOW

• Microelectronics section EP – ESE – ME

• ASIC design procedure

• Circuit design

• Chip integration

Part 2 : THE BLM CASE STUDY

• BLM application requirements

• BLM ASICs

• Delta Sigma model

• Delta Sigma schematic hierarchy

• Test bench schematics and simulations

• Delta Sigma layout hierarchy

• ASICs test setup

• ASICs measurements repeatability

• Summary

Presentation outline

12/10/2019Luca Giangrande | How to design an ASIC: the BLM

case study2

ASIC DESIGN FLOW

12/10/2019 Luca Giangrande | How to design an ASIC: the BLM case study 3

Custom ASIC design for experiments and machine:

https://ep-dep.web.cern.ch/organisation/ese.

Expertise in radiation tolerant ASIC design from conception toproduction: analog, digital, power conversion.

Current projects :

• ATLAS ITK silicon tracker upgrade: ABCSTAR front end ASIC

• CMS outer silicon tracker upgrade: PS module chip set {MPA (pixelfront end), SSA (strip front end) , CIC2 (concentrator)}

• CMS GEM muon upgrade: VFAT3 ASIC

• RD53: Pixel chips for Atlas/CMS

• LHCb upgrade: VELOPIX pixel ASIC

Microelectronics section EP-ESE-ME


https://ep-dep.web.cern.ch/organisation/ese

• ALICE upgrade: ALPIDE front end ASIC monolithic activesensor

• Medical imaging and timing application: Medipix and Timepixfamily ASICs

• lpGBT: electrical and optical (digital) communication standardfor LHC upgrade

• DCDC converters: bPOL12V (step down from 12V to 2.5V)and bPOL2V5 (step down from 2.5V to 0.6V)

• Pico TDC: time to digital converter with pico-second resolution

Microelectronics section EP-ESE-ME


ASIC design procedure

Application requirements

System emulation (optional):

• FPGA for digital

• Discrete components for analog

Pre-development study

Architecture choice Technology selection

Chip design

Schematic Layout

Fabrication and testing


Circuit design

Chip architecture definition


Schematic drawing and

components sizingRTL description and gate level synthesis

Test benches drawing Test benches coding

Simulations for optimal sizing Simulations for optimal architecture

Layout drawing Place and route

Post layout verification Post layout verification

Analog Flow Digital Flow

Chip integration


Digital part instantiation Analog part model in Verilog(AMS)

Schematic simulation (full

analog or mixed mode)Verilog simulation of the chip

Manual layout integration Place and route of top IP blocks

Manual layout verification Layout verification

Density rules (DRC) compliance

Analog on top Digital on top

Masks description file generation

GDSII

THE BLM CASE STUDY


The existing module is based on CFC (current to frequency conversion) principle and employs (mostly) commercial components.

Application requirements in view of Hi-Lumi upgrade:

• Signal range from 1pA to 1mA (180dB Dynamic Range)

• Radiation tolerance above 100 Mrad (1MGy)

• Integration window (i.e. acquisition time) of 10μs

• Robustness against Single Event Upsets (SEU) and E.M. Interference

• Saturation for out of range signals and fast recovery

Design choices:

• Compatibility with lpGBT

• Compatibility with 50m coaxial cable (~5nF)

BLM application requirements


Switch

Iin(t)

Reference

current

Treshold

comparator

One-shot

T

Iref

Integrator

fout

Switch

Iin(t)

Reference

current

Treshold

comparator

One-shot

T

Iref

Integrator

fout

The development of a prototype involves trade-offs betweenfailure-risks and time (i.e. cost) expenditure.

It was decided to produce two separate chips that implementtwo different architectures (CFC and Delta Sigma). Thisallows:

• Redundancy for higher success probability

• Major differences from system point of view

• No clear advantage from simulations

• Allow to verify the behaviour in a realistic environment

• The two designs fit in the minimum MPW area

• Several blocks (schematic and layout) are shared.

BLM ASICS


In the pre-study phase the computational model serves to:

• validate the architecture choice

• derive the circuit level requirements (such as gain,bandwidth, delay, offset, etc.)

• investigate the effects of the circuit limitations on the systemlevel performance.

Delta Sigma model


1/Ci z-1Qin Vin E Y

Nq

Voutα

Delta Sigma Z-domain schematic

Delta Sigma waveformsNoise TF for different integrator gains

Delta Sigma schematics

Descending the ΔΣ ASIC schematic hierarchy from top to the transistor level.


Top level

Analog part Digital

part

Pad ring

Channel 1 Channel 2

Local digitalADC

Integrator Comparator

Level shifters

Bias current

Amplifier

Simulations are run to strengthen theconfidence on the design (in terms offunctionality, performance and robustness).Different types of simulations are performedthroughout the hierarchy:

• DC operating point

• DC sweep

• AC linearization (for signal and noise TF)

• Transient (with inclusion of band-limitednoise)

Each simulation can be run under eitherparameters, PVT (process voltage andtemperature) or mismatch variations.

Test bench schematics and simulations


A

Each layout view is checkedwith design rules check(DRC) and layout versusschematic (LVS) softwaretools.

The critical blocks and sub-blocks are re-simulated withparasitic elements (C+CCand/or R+C+CC) extractedfrom the layout view.

Delta Sigma layout hierarchy


Test bench setup to verify the main functionality (digital and analog), such as:

• receiving instructions,

• transmitting data,

• current digitizer characteristic in the high current range (1μA ~ 1mA),

• linearity error.

ASICs test setup


Current to digital conversion effective resolution in the high current range (1μA to 1mA):

• ΔΣ from 10 bits with 10μs integration time to 15 bits with 400ms

• CFC from 8.4 bits to 15.5 bits

ASICs measurements repeatability


• The development of the two ASICs took ~30 months FTE from pre-study to submission.

• Three months for fabrication, packaging and delivering

• Costs of ~ 50k for 160 chips (80 CFC and 80 Delta Sigma)

• Measurements ongoing and look very promising. Remaining tests:

• TID X-ray irradiation up to 100 MRad

• Heavy ions irradiation (digital SEUs and performance degradation)

• Digital verification with dual e-link connection

• Develop the rad-hard BLM module prototype (4x BLM ASICs, 2x lpGBT, 1x bPOL2v5)

• Depending on the measurement results design an upgraded version of the ASICs

• Select one architecture and go for production

Summary


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How to design an ASIC: a case study for the BLM project