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[M2] Huffman Encoder Project. Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee. Overall Project Objective : Design a Low Power Huffman Encoder. Presentation #3 February 7 th , 2007. Huffman Encoder Project. Status. - PowerPoint PPT Presentation
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Howd - Zur HungEric Lai
Wei Jie LeeYu - Chiang Lee
Design Manager: Jonathan P. Lee
[M2] Huffman Encoder Project
Presentation #3February 7th, 2007
Overall Project Objective:Design a Low Power Huffman Encoder
Design ProposalChip Architecture
Behavioral Verilog ImplementationSize estimates/floorplanningBehavioral Verilog simulated
Gate Level DesignComponent Layout/Simulation
Chip LayoutComplete Simulation
Huffman Encoder Project
Status
Implement Huffman compression portion of GZIP on a single chip
Provide fast & energy efficient compression for network devices
About …
Huffman Encoder Project
• Based on the DEFLATE algorithm, which is a combination of LZ77 and Huffman coding • Widely used in the HTTP/1.1 protocol and general purpose data compression
• GZIP software compression speed(100 Mbits per second)
What is GZIP?
Huffman Encoder Project
Huffman Encoder Project
Currently in Market:
AHA362-PCIX 3.0 Gbits/sec GZIP Compression/Decompression Accelerator
PCI-X, 64-bit, 133 MHz edge card interface
Ideal for SAN servers, virtual tape emulation backup and recovery systems
Huge, power hungry, require built-in processor
Huffman Encoder Project
Our Target Market
Network Server, on chip solution for network card and motherboard
Portable Devices
Huffman Encoder Project
Design Constraints
Clock Speed >= 133MHz
Hard to get benchmark for size and power in the market
Optimize for power once speed constraint is met
Huffman Encoder Project Detailed Block Diagram from Week 2
5
SRAMFrequency / Group
MU
X
+1
Dat
a
Count Frequency Total Groups
Find 2 Lowest
Groups / Frequency
Combine Groups
+1
Add
er
Cho
ose
Gro
upOutput Tree
SRAMCode / Length Buffer
Lookup Code
Control Logic
Current Group
New Freq
Enable
Tree CodeTree Length
Code Length
Code
Code Ready
Code Length
Code Output
Inpu
t D
one
Input Request
5
16
531
16
5
31 5
5
31
16
Upd
ate
Cod
e
Huffman Encoder Project
Design Decision (week 3)
• Add MemSelect module • Add TraverseAddr module• Serial Output
Huffman Encoder Project
16 bit register
0 1
1 bit reg
1 bit incrementor1 bit reg
reset
1
reset
en
reset
en
were
en
err
countFrequencycountFrequency
we re err
clk reset en
16
freqency
Huffman Encoder Project
5 bit incrementer
5 bit Reg
ready
enreset
address
traverseAddr
Huffman Encoder Project
16 bit comparator
Reg A16 bit
Reg B16 bit
16 bit comparator
Reg C5 bit
Reg D5 bit
5 bit XOR 5 bit XOR
freqGroupIn
enen
ready ready
freqGroupA freqGroupB
find2LeastFrequency16
Huffman Encoder Project
5-bit subtractor
31-bit Left Shift Register(code)
5-bit incrementer
01
16-bit adder
freq1 freq2
codeLength
315
36
groupgroup1
5 5
5-bit subtractor
groupgroup2
5 5
516
21
21'bZ
we
36'bZ
we
updatedFreqGroup updatedLengthCode
combine
enable enable
Huffman Encoder ProjectSRAM CodeLength
32:1 Mux
2:1 mux
5bit register
-1
decrementer
Count >= 0 ?
Flip flop n
Flip flop N+1
Ld_LShift_H
CodeWord0 CodeWord1
clock
out
5bitInput
FSM
counterSel
Serial Output
Huffman Encoder Project
DataIn
5 5 5
CountFrequency Combine
AddressLine
5
CountFrequency Combine
ReadLine
Find 2Least
2addrSel reSel
21 21
CountFrequency Combine
Data WriteLine
21 dataInSel
Combine
WriteLine
weSel
CountFrequency
21
SRAMoutput
DataIn
21 21 21
CountFrequency Combine
Data ReadLine
dataOutSel2
MemSelectFrequencyGroup
Huffman Encoder Project
5 5
Output Combine
AddressLine
5 addrSel
Output Combine
ReadLine
reSel
36
SRAMoutput
36 36
Output Combine
Data ReadLine
dataOutSel
MemSelectLengthCode
Huffman Encoder Project
Transistor Count (week 2)SRAM (Freq / Group) ~ 4,000SRAM (Code / Length) ~ 7,000Adders ~ 1,000Comparators ~ 1,000FSM Control Logic ~ 1,000Registers ~ 1,000Buffer ~ 2,000Others (mux, demux, etc.) ~ 4,000
Total ~21,000
Huffman Encoder Project
Updated Transistor Count
SRAM (Freq / Group) ~ 4,000SRAM (Code / Length) ~ 7,000CountFrequency ~ 650Find2Least ~ 2,500Combine ~ 1,530TraverseAddr ~ 440SerialOutput ~ 1,300MemSelect ~ 1,370FSM Control ~ 500Total ~19,290
Huffman Encoder Project
Initial Floorplan
Frequency/Group
SRAM
MemSelectLength/Code
MemSelectFrequency/Group
Tra
vers
eA
dd
r
Tra
vers
e
Ad
drFind2Least
Combine
CountFrequency
Code/Length
SRAM
FSM Control
SerialOutput
Huffman Encoder Project Behavioral Verilog
`include "SRAM_freqGroup.v"
`include "countFreq.v"`include "control.v"module top(input clk, reset, en, start, done, input [4:0] dataIn, output ERR);
wire [20:0] freqGroup, freqGroup1, freqGroup2;wire [3:0] enPhase, resetPhase;
control control1(clk, reset, start, done, findReady, combineReady, oneGroupLeft, finish, enPhase, resetPhase);
SRAM_freqGroup SRAM_freqGroup1(re, we, clk, reset, dataIn, freqGroup);countFreq countFreq1(clk, reset, start, freqGroup[20:5], freqGroup[4:0], re, we, ERR);find2Freq find2Freq1(freqGroup1, freqGroup2, freqGroupIn, ready, clk, reset, en);
endmodulemodule topT(output reg clk, reset, en, start, done, output reg [4:0] dataIn, input ERR);
always#10 clk = ~clk;
initial begin$monitor($time,, "clk=%b, reset=%b, dataIn=%b, ERR=%b", clk, reset, dataIn, ERR);clk = 0;reset = 0;done = 0;en = 0;#20;reset = 1;#20;reset = 0;start = 1;dataIn = 5'b01101;#10;en = 1; // enPhase[0] should be on at time = 50#10;dataIn = 5'b01111;#40;dataIn = 5'b01101;#40;dataIn = 5'b11001;#80;dataIn = 5'b01111;#80;$finish;
endendmodule
Huffman Encoder Project
Behavioral Verilog Simulation Waveform
Huffman Encoder Project
Problems
Timing IssuesMultiple Clocks???