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~ Advanced Micro Devices

Developing and Debugging anISDN Terminal Adapter

Jean Anne Booth

Advanced Micro Devices5900 East Ben White Blvd., MS 561Austin, Texas 78741Tel: (512) 462-5879Fax: (512) 462-5051

1993High Speed DigitalSymposium

© Hewlett-Packard Company 1993

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Abstract

The Integrated Services DigitalNetwork digitizes voice signals atthe telephone and sends bothvoice and control signals to thePABX or central office switchdigitally. An ISDN tenninaladapter interfaces between ISDNand non-ISDN equipment,typically at the subscriber looplevel that interfaces between thecustomer's equipment and the

Author

Jean Anne Booth

Current Activities:Jean Anne Booth is a SeniorTechnical Marketing Engineer atAdvanced Micro Devices. She hasbeen with AMD for 6 years, andis currently responsible fortechnical marketing of currentand future high perfonnance29K"M RISC microprocessors.

local telephone network office.This presentation introducesISDN, describes an ISDNterminal adapter, and shows howto implement an ISDN tenninaladapter in hardware andsoftware. Using an evaluationboard, PC, JTAG emulator, andHP 16500 logic analyzer, thepresentation also shows how todevelop and debug the ISDNtenninal adapter presented here.

Background:Prior to joining 29K Marketing,she managed the 29K TechnicalSupport Center, providinghardware and software technicaland applications support to29K Family customers. Beforejoining AMD, Jean Anne was adevelopment engineer involved inthe software implementation ofreal-time control systems. JeanAnne holds a BS in ElectricalEngineering and an MS inComputer Engineering.

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Developing and Debugging an ISDNTerminal Adapter

Slide #1

Developing and Debuggingan ISDN Terminal Adapter

Advanced Micro Devices

Slide #2

Developing and Debugging anISDN Terminal Adapter

• Introduction to ISDN• An ISDN Terminal Adapter

- Am79C30Al32A Digital Subscriber Controller (DSC)- Am29200™ 32-bit RISC microcontroller- Am85C30 Serial Communications Controller (SCC)

• Developing an ISDN Terminal Adapter- Hardware- Software

• Debugging the ISDN Terminal Adapter- PC, JTAG emulator, HP 16500 logic analyzer,

SA-29200 evaluation and expansion boards


Slide #3

The Integrated Services DigitalNetwork (ISDN)

• All-digital network standard: voice, data, controlsignals

• Replaces subscriber loop with digital voice anddata capability

• Global communications network benefits:- increased reliability

- increased functionality- lower cost- worldwide standardization

The Integrated Services Digital Network, orISDN, digitizes voice signals at the telephone andsends both voice and control signals to the PABXor central office switch digitally. Thus, ISDNreplaces the last analog component of telephonecircuitry, the subscriber loop, with a digitalcomponent capable of handling both voice anddata information. ISDN brings the benefits ofdigital technology - increased reliability, newfunctionality, lower cost, and increased securityand privacy - and worldwide standardization tothe global communications network.

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Slide #4

ISDN Classes of Service

() Basic~ : } Information: voice, data at 64-kbps

o } call control, low speed packet data192 kbps Overhead

Slide #5

ISDN Standards• CCITT responsible for ISDN standards

• Basic structure defined in CCITT 1.411recommendation

• Utilizes Open Systems Interconnection (OSI)communications model

051 Model

ISDN service t--__L_a-'-ye_r_7_:....;AP:...:p_li_ca_t_io_n---lLayer 6: Presentation() Prim",,~: I

1.544/2.048 Mbps

Information: voice, data at 64-kbps

call control

1.544 Mbps: 23 B channels, 64 kbps1 0 channel, 64 kbps

2.048 Mbps: 30 B channels, 64 kbps1 0 channel, 64 kbps

send voicepacket

Layer 5: Session

Layer 4: Transport

Layer 3: Network

Layer 2: Link

Layer 1: Physical

ISDN service is divided into two classes - primaryrate, an expensive high-bandwidth connection, andbasic rate, the type of subscriber connection mostcommonly used. The focus here is on the basic rateservice, which provides three communicationschannels. The two B (or bearer) channels provideeither voice or data service at 64 kbps. The D (orsignaling/data) channel provides call control servicesand low speed packet data transmission (up to9600 bps). Primary rate service is provided at either1.544 Mbps (US, Canada, and Japan) or 2.048 Mbps(Europe). The channel structure for the 1.544-Mbpsrate is typically 23 B channels and one D channel;the 2.048-Mbps rate is typically composed of 30 Bchannels and one D channel.


The group overseeing the definition of ISDN is theCCITT, and the basic structure of the ISDN isspecified in the CCITT 1.411 recommendation.ISDN functions are further subdivided by the OSI(open systems interconnection) seven-layercommunication model. The OSI model definesphysical and logical services provided by each layer;a vertical "slice" of the model encompassing at leastlayers 1 through 3 provides one ISDN function, suchas a user data transfer.

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Slide #6

CCITT Recommendations forISDN

I Series• Complete set of recommendations for all

standardization aspects of ISDN• Cross references specifications from other

series (0 Series for protocols, and VIX series fornon-ISDN terminals)

Slide #7


I Series1.420/1.421 - Introduction to ISDN concepts

and other I Series recommendations

1.430 - Layer 1 interface specification ('S'and 'T' interface recommendations)

1.431 - Layer 1 primary rate interface

1.440/1.441 - Layer 2 protocol specification(LAPD) Cross references 0.920/0.921

1.45011.451 - Layer 3 protocol specification.Cross references 0.930/0.931

The CCITr I Series of recommendations is acomplete set of recommendations for all aspects ofISDN. The I Series recommendations cross-referencespecifications from other series, like the Q Series forprotocols, and the V and X series for non-ISDNterminals. CCITr has defined many more I Seriesrecommendations than the ones listed here.


Slide #8


a Series0.920/0.921 - Defines the Layer 2 protocol

(LAPD) used by ISDN

- Ensures error-free andcorrectly sequenced datatransmission between Layer 3entities

- Specifies syntax of messageformat used within HDLCframes at Layer 2

The Q.920/Q.921 recommendation defines theLayer 2 protocol used by ISDN, also known asLAPD. The LAPD protocol ensures error-free andcorrectly-sequenced data transmission betweenLayer 3 entities. The services provided by the LAPDprotocol include both unacknowledged and acknowledged information transfer on the ISDN D-channel.The Q.920/Q.921 recommendation also specifies thesyntax of the message format used within HDLCframes at Layer 2.

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Slide #9


Q Series0.930/0.931 - Defines internationally agreed

portion of Layer 3 (network layer)protocol for ISDN

- Provides packetizing andblocking of Layer 4 messagesfor Layer 2 conformance

- Does not address supplementaryservice (defined by nationalcommittees)

The Q.930/Q.931 recommendation defines theinternationally agreed-upon portion ofthe Layer 3protocol used by ISDN. It details packetizingand blocking of Layer 4 messages for Layer 2conformance, but does not address supplementaryservices, such as call waiting, call transfer, creditcard calling, etc. Supplementary services are definedby national committees.

Slide #10

Band D channels share the physical interface, thesestandards apply to both types of channels. Abovethis layer, the protocol structure differs for the twotypes of channels.

For the D channel, the LAPD protocol defined inQ.920 and Q.921 is employed in the data linklayer. For the B channel, the 1.46X series ofrecommendations defines alternative protocols forinterfacing existing equipment to the ISDN.Because the B channel can also be packet-switched,the LAPD protocol can also be used, in addition tousing the more common LAPB protocol for data linklayer transfers.

At the network layer, Q.930 and Q.931 define callcontrol for the D channel. Ifthe D channel is used toprovide packet switching services, the X.25 level 3protocol is used. For the B channel, the X.25 level 3protocol provides network layer services for packetswitching.

Slide #11

ISDN Network Topography

The network topography from the desktop to theswitch is shown here, identifying certain classes ofequipment that make up the network. "Referencepoints" are defined that represent various interfaceswith CCIT!' standards for both hardware andsoftware. In developing a terminal adapter, we willbe dealing with the R and SIT interfaces.

CCITT Recommendations for ISDNApplicability of I/Q Series

recommendationsApplication End

Presentation toEnd

Session UserSignaling

Transport

Network Call Controlx.2sl ~0.93010.931

Data Link LAPD II 46X I LAPBI0.92010.921 . LAPD

Physical 1.4301431

D-Channel I B-Channels

This is another look at the relationship between OSIand ISDN. As a network, ISDN is primarily unconcerned with layers 4 through 7, which you employfor exchanging information. Layer 1, defined in1.430 and 1.431, specifies the physical interface forboth basic and primary rate access. Because both the

"R" "S" "T" "U"

PacketSwitchedNetwork

FrameRelayNetwork

B, HO,Hll, Hl2CircuitSwitchedChannels

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Slide #12

ISDN Terminology

• TE1: ISDN compatible voice and/or dataterminal

• TE2: Non-ISDN compatible terminal (such asV.24, X.21, X.25, SNA terminal

• TA: Terminal adapter providing physicaland/or protocol conversion between aTE2 and the ISDN

• NT2: Network termination providing switchingand/or concentration (such as PBX) not present in single line installations

In the ISDN network topography, a TEl (terminalequipment type 1) refers to devices that support thestandard ISDN interface, such as digital telephones,integrated voice/data terminals, or digital facsimilemachines.

A TE2 (terminal equipment type 2) refers to anynon-ISDN compatible terminal, typically existingequipment. Examples ofTE2 are terminals with anRS-232 interface, host computers with an X.25interface, and SNA terminals. TE2 devices require aTA (terminal adapter) to plug into an ISDN interface.TAs may provide physical conversions, protocolconversions, or both.

All terminal equipment, whether TEl or TE2,provides protocol handling, maintenance functions,interface functions, and connection functions toother equipment.

An NT2 (network termination 2) is an intelligentdevice that provides switching and/or concentrationfunctions. Examples ofNT2s include digital PBX,terminal controllers, and LANs. An NT2 performslayer 2 and layer 3 protocol handling, layer 2 andlayer 3 multiplexing, maintenance functions, andinterface termination, in addition to switching andconcentration.


11-7

Slide #13

ISDN Terminology

• NT1: Network termination providing physicaland/or protocol conversion between the'S'/'T' interface and the network-provided'u' interface

• LT: Line termination performing physicaland/or protocol conversion between 'u'interface and central office exchangeinternal highways

An NT1 (network termination 1) provides physicaland electrical termination of the ISDN. It may alsoprovide protocol conversion between the SIT interface and the network's U interface. The NT1 may becontrolled by the ISDN provider, and forms a boundary to the network. The functions provided by anNT1 include line transmission termination, linemaintenance and performance monitoring, timing,power transfer, layer 1 multiplexing, and interfacetermination, including multidrop terminationemploying layer 1 contention resolution.

An LT (line termination) provides physical and/orprotocol conversion between the U interface and theprovider's network.



Slide #14 Slide #15

Characteristics of '5' and 'T'Reference Points

• 4 wire interface• 192 kbps full duplex

- 48 bit frame each 250 msecs• Optional remote power feed• Pseudo-ternary line coding

N =Bit set to a binary value N =FAB1 = Bits within B-channel1B2 =Bits within B-channel 2A =Used for activation5 =Reserved for future standardizationM = Multiframing bit

F =Framing bitL = DC balancing bitD =D-channel bitE =D-echo-channel bitFA = Auxiliary Framing bit

'S' Interface Frame Structure

101001100011DataSignal

The Sand T reference points contain a 4-wireinterface with optional remote power feed. Two64-kbps B channels and one 16-kbps D channelproduce a load of 144 kbps, and they are multiplexedover the 192-kbps S or T interface. The remainingcapacity of 48 kbps is used for framing andsynchronization overhead.

The synchronous time-division multiplexed (TDM)scheme used by the S and T interfaces is composed of48-bit frames transmitted at a rate of one every250 microseconds.

To prevent loss of synchronization and signaldegradation, pseudo-ternary line encoding is used atthe Sand T interfaces. In pseudo-ternary lineencoding, a binary 1 is represented by no line signaland a binary 0 is represented by a positive ornegative pulse. The binary 0 pulses must alternatein polarity to prevent signal degradation.

The S interface frame structure, 48 bits repeated ata rate of one frame every 250 microseconds, includes16 bits from each of the two B channels and 4 bitsfrom the D channel. The upper frame is transmittedfrom the network (NT1 or NT2) to the terminalequipment (TE); the lower frame is transmittedfrom the terminal equipment to the network. Theframe from a TE to NT follows the frame from NT toTE by 2 bit-times.

Consider the frame from TE to NT first. Eachframe begins with a framing bit (F) that is alwaystransmitted as a positive pulse, followed by a dcbalancing bit (L) that is a negative pulse to balancethe voltage. This F-L pattern synchronizes thereceiver on the beginning of the frame. After thesynchronization, the first zero bit will be encoded asa zero, and then pseudo-ternary encoding rules arefollowed for the remaining bits.

The next eight bits (B1) are from the first B channel.This is followed by another dc balancing bit (L).Next is one bit from the D channel and its dcbalancing bit. This is followed by the auxiliaryframing bit (FA), which is set to zero unless it isbeing used in a multiframe structure. Anotherbalancing bit (L) follows, then eight bits from thesecond B channel (B2), and another balancing bit(L). This entire sequence is duplicated again totransmit another eight bits from the first B channel,a single D channel bit, another eight bits from thesecond B channel, and another D channel bit, withbalancing bits following each group of channel bits.

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The frame structure in the NT to TE direction issimilar, except that some ofthe dc balancing bits arereplaced by D-channel echo bits (E), which are aretransmission by the NT of the most recentlyreceived D bit from the TE. The echo bits are used toprovide D-channel contention resolution in a networkwith multiple TEs in a passive-bus configuration.The activation bit (A) is used to activate a TE (bringit on-line). The N bit is set to one unless it being usedin a multiframe structure. The M bit indicates amultiple frame. Multiframing is defined in 1.430, andconsists of 20 frames as defined here, where theauxiliary framing bit carries the Q multiframe datain the TE to NT direction, and S carries the Qmultiframe data in the NT to TE direction.

Slide #17

Terminal Adaption

• Bit stuffing - ECMA102IV.110, DMI Mode 2- Low cost- No error detection/re-transmission

• Packetizing - V.120, DMI Mode 3- Error detection/re-transmission- Statistical multiplexing- Higher throughput

Slide #16

The 'R' reference point alows non-ISDN terminalsto be connected to the ISDN.

Characteristics of the 'R' andReference Point

Standard

V.120

DMI Mode 2

DMI Mode 3

V.110/ECMA 102

Protocol

LAPD packet protocol

Bit stuffing

LAPDIX.25

Bit stuffing

An ISDN terminal adapter is the interface betweenISDN and non-ISDN equipment, typically at thesubscriber loop level that interfaces between thecustomer's equipment and the local telephonenetwork office.

An ISDN data-only terminal adapter will interfaceeither a bit-stuffing protocol or a packetizihgprotocol to the ISDN. A terminal adapter forbit-stuffing terminals has the advantage of low cost,but also has no error detection or retransmission.Terminal adapters for packetizing protocols aremore expensive but also more reliable, with errordetection and retransmission included in the protocolconversion. In addition, packetizing systems have ahigher throughput.

The R reference point allows non-ISDN terminals tobe connected to the ISDN. Some common non-ISDNinterfaces and their protocols are listed here.

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Slide #18

Terminal Characteristics

• High volume products• Severe cost constraints

- Low component cost

• Power constraints for voice products- Efficient CMOS devices

• High feature content- Complex software, powerful MPU

• Switch specific versions- Multiple software variants

An ISDN terminal adapter is a high-volume productbecause the installed base of non-ISDN compatibleequipment is nearly the size of the entire installedterminal market. Like all high-volume products, theyoperate under severe cost constraints, requiring alow component count to maintain competitivenesswith other vendors. Voice terminal adapters alsohave a strict power budget, so solutions with powerefficient CMOS devices are required. Becauseinterfacing a non-ISDN terminal to the ISDN usuallyinvolves adding ISDN features that aren't a part ofthe existing analog solution, terminal adaptersrequire powerful processors to implement these newfeatures in software. To broaden the market potential for an adapter, manufacturers prefer to createspecific versions ofthe same basic adapter that differonly in software to handle different protocols orimplement required ISDN features not present in thenon-ISDN terminal.


Slide #19

ISDN Voice and DataTerminal Adapter

Data ProtocolController

This shows a block diagram of an ISDN terminaladapter.

Our case study will build a terminal adapterusing an Am79C30A Digital Subscriber Controller(DSC) for basic ISDN services and an Am29200™RISC microcontroller for control of the DSC andISDN protocol. An Am85C30 Serial CommunicationsController (SCC) provides the serial interface tothe R reference point. Using an Am79C30A allowsISDN-compatible transmission of both voiceand data.

Slide #20

ISDN Data-only Terminal Adapter

II s

An ISDN data-only terminal adapter could be builtusing an Am79C32A ISDN Data Controller (IDC)instead of the Am79C30A, as shown here.

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Slide #21

Am79C30A Digital SubscriberController

The Am79C30Al32A provides a 192-kbps full duplexdigital path over four wires between the TE (tenninalequipment) located on the subscriber's premises andthe NT (network terminal) or PABX linecard.All physical Layer functions and procedures areimplemented, including framing, synchronization,maintenance, and multiple tenninal contention.The Am79C30Al32A processes the ISDN basic ratebit stream. The B channels are routed to and fromdifferent portions of the DSC under software control.The D channel is partially processed and then passedto the microcontroller for further processing.

The B-channel multiplexer routes the 64-kbps fullduplex B channels between the LID, MAP, MPI, andperipheral port. Routing control is programmed bythe microcontroller.

The 16-kbps D channel is time multiplexed withinthe frame structure of the S interface. The datacarried by the D channel is encoded using the LinkAccess Protocol D-channel (LAPD) fonnat shownhere. The LID controls the multiplexing anddemultiplexing of the D-channel data between the Sinterface and the D-channel data link controller(DLC).

destination registers for read and write operations onthe data bus. The data bus is used to exchangeinfonnation with the controlling processor. Aninterrupt input infonns the processor that the DSCneeds service, and chip select and read/write signalsare provided for system interfacing.

The Am79C30Al32A will generate a maximum of oneinterrupt every 125/-ls. Once asserted, the interruptwill remain asserted until the microcontrollerreads the DSC's interrupt register. Events thatgenerate interrupts include DLC receive FIFO full,DLC transmit FIFO empty, LID change of state(on hookloffhook), packet errors, and packet status(last byte, etc.).

LOUT1LOUT2L1NlL1N2

RESET

SBIN SBOUT SCLK SFS HSW

07-00 ·INT A2-AO

AINAAREFAINB

EARlEAR2

LSlLS2

MCLK

·CS·WR

·RO--E~====+==~~=I==~===---.J

XTALlXTAL2

This is a block diagram of the Am79C30A DSC.The main audio processor, or MAP, is the onlyportion ofthe Am79C30A that is not present on theAm79C32A. The MAP uses DSP to implement ahigh perfonnance codecJfilter function. The MAPsupports a loudspeaker, an earpiece, and twoseparate audio inputs. Gain, frequency response,and tone generation are programmable.

The srr line interface unit, or LID, provides theinterface to an ISDN S or T reference point.It contains a hook-switch input and differentialsubscriber line inputs and outputs. The LID monitorsthe S interface and hook switch during power down,allowing the microprocessor to be shut down toconserve power during idle periods.

The microprocessor interface unit (MP!) communicates with the processor controlling the terminaladapter. The address line inputs select source and

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Slide #22

Layer-2 Frame Structure Formatsprocessor core is shown here. The processor corecontains a 4-stage instruction/execution pipeline,separate 32-bit instruction, address, and databuses, 192 32-bit general purpose registers, a 56-bittimer/counter, and special registers for processorcontrol. The instruction set is simple, with allinstructions being 32-bits in length and using a3-operand fonnat (one destination register and twooperand registers). The only addressing mode isregister-direct; data is moved on- or off-chip withLOAD and STORE instructions. Nearly all instructionsexecute in a single cycle.NN·1

OCTET 2

OCTET 3

SAPI

TEl

345 6

2,3

EA=O CIA

EA=1

General

L.;;.;..;.;.;..;...;.;;..r....;.;;.=..1-=.;;;.....1-....;,;.;;;,;;;.....,1,,;,;;.;;;,;;~;,,;,,;,;,.;.;MIPacketOCTET

EA =Address Field Extension Bit SAPI = service Access Point IdenttfierCIA =CommandIResponse Field Bit TEl = Terminal Endpoint Identifier

FCS = Frame Check sequence

Slide #24

29K~ Register File

The 192 general-purpose registers are split into twogroups, 64 global registers and 128 local registers.The local registers are organized internally as acircular queue. The register pointed to by globalregister 1 (grI) is local register 0 (lrO); the registerbelow lrO is IrI, and the register above is IrI27. Thelocal registers are used by compilers to implementdynamic register windowing, and are controlled bysoftware convention.

Ister 126127

Ister 125

Stack Pointer = 206

128 Local(Indirect addressing)

64 Global(absolute addressing)

64

127

29KTM Family Processor Core

...-r=-M Addre•• 192 X 32 Inst 1 F 0 E WPC Unit Register

FilelStack Inst 2 F 0 E WDola

rw Cache Inst 3 F D E W

ll,n~.Inst4 " 0 E F

Memory Special.,,,

PrefetchMgmt.Unlt Rag. IIALU,jI·

Cycle 1 2 3 ~j ...Buffer, FSU

PRIImp" '''\%'. 'I ',W_

II Channellntel1ace I

The DLC perfonns processing of Layer-1 and partialLayer-2 LAPD protocol, which includes flag detectionand generation, zero deletion and insertion, andFrame Check Sequence (FCS) processing for errordetection. Higher-level protocol processing is done bythe external microcontroller. The DLC contains two8-byte data FIFOs for receive and transmit data, andthree 2-byte status FIFOs that make it possible toreceive two back-to-back data packets.

Slide #23

Inst. Address Data

The Am29200 32-bit RISC microcontroller contains a29KTM Family 32-bit RISC processor core, memorycontrollers, and integrated peripherals. The 29K

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Slide #25

Am29200™ RiSe Microcontroller

Slide #26

29K~ Interrupt Processing

Tel( TroiSTot TOO

-mST

psmOBE'PBUSY 'POEPACK 'PWE

PAUOFO

UCLK TXORXC

'OSA 'OTR

velK VDATL5YNCPSYNC

PI0(15:D)

_INelK

MEMCLK

'AESET 'INTR(3:0)

I----t__ ~~::(~:O) "TRAp(1:0)

...-__-.!:::;----n=;=='====;j-A(23:0)'ROMCS(3:D) 'RSWE'ROMOE BOOTW'BURST

'RAS(3:0) 'CAS(J,OJ'WE 'TRRXW

DREQ(1 :0) 'OACK(l :0)TOMA 'GRED'GAel(

'P1ACS(5:0) 'PIAoe'P1AWE 'WAIT

10(31:0)

Supervisor Mode Handler

rFreeze Enabled

Supervisor Mode Handler

rFreeze Disabled

Supervisor or UserMode Handler

f nterrUPlS Enabled

ie-level't Handler

This is a block diagram of the Am29200microcontroller. The ROM controller and DRAMcontroller implement a glueless interface to memory.The DMA controller provides two channels fortransfer of data between the DRAM and internal orexternal peripherals. The peripheral interfaceadapter (PIA) implements a glueless interface to upto six generic peripherals, and will be used to connectto the DSC and SCC. The I/O port provides 16programmable signals that can be outputs, inputs, orinterrupt triggers. The 5-pin JTAG port is used fortest and debug control of the processor.

Internal peripherals in the Am29200 microcontrollerare addressed with LOAD and STORE instructions usinga pre-defined memory mapped address. In addition,special registers are programmable for control andstatus for each peripheral.


Interrupts in the Am29200 microcontroller aretriggered by external interrupt pins, programmedpins in the I/O port, and internal sources, such as theDMA controller or software traps. When an interruptoccurs, the processor completes or cancels currentbus activity, saves the Current Processor Status(cps) register into the Old Processor Status (ops)register, sets itself in Supervisor mode and freezesother processor status (so as not to corrupt theinterrupted application), decodes the interrupt,and fetches the first instruction of the applicableinterrupt handler. In keeping with the RISCphilosophy of machine simplicity, no state or statusother than the cps is saved. At the softwareengineer's option, the interrupt handler may executein Freeze mode, utilizing only registers set aside forthis purpose, or it may save more state and utilizemore of the processor's resources.


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Slide #27

Am85C30 Serial CommunicationsController

the Am29200 RISC microcontroller providingcontrol and error processing for both the SCC andDSC. Both the SCC and nsc will be connected tothe Am29200 microcontroller through them'crocontroller's PIAs.

CPU BusAddressControl

$erialData

ChannelControls

serialOats

ChannelControls

The DSC provides all voice and physical layer Sinterface functions and partial Layer 2 D-channelhandling. The remainder of Layer 2 and all Layer 3functions are provided by the microcontroller.

Slide #29

The Am85C30 Serial Communications Controller(SCC) is a dual channel multi-protocol data communications peripheral, handling both asynchronousand synchronous formats including SDLCIHDLCand BiSYNC. It contains two channels, and eachchannel has an independent oscillator, baud-rategenerator, and digital-phase locked loop for clockrecovery. The device is controlled by internalregisters read and written by a microprocessorthrough the 8-bit data bus. The SCC interrupts itscontrolling processor for transmit complete, receivecomplete, and error conditions.

Am29200 PIA Read Timing

'PIAWE

"WAIT I E

~~-i-~:,'i~v7n :10(31-0) ,. ' ~r-i-:----r-I ! number of cycles l f next access is:~ determined ~: del~yedonecyclel l by IOWAITx+l I If IOEXTx=l

Slide #28

ISDN Terminal AdapterFunctional Block Diagram

This is the timing of a PIA read cycle. The number ofcycles until the PIA Chip Select (*PIAcsx) andPIA Output Enable (*PIAOE) are deasserted isdependent upon the value of Input/Output WaitStates (IOWAITX) field of the PIA control register inthe microcontroller. The minimum access timefor a PIA read is 3 cycles (2 wait states). If theInput/Output Extend (IOEXTX) field of the PIAcontrol register is set, the next PIA access will bedelayed one cycle for an additional cycle of outputdisable time.

Am85C30Serial

CommsController

Am79C30ADigital

SubscriberController

Serial Port

Inst,uellonlDsls J.--........

Am29200Microcontroller

Address

This block overview ofthe ISDN terminal adaptershows the SCC connecting to the ISDN R interface,the DSC connecting to the ISDN SIT interface, and

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Slide #30 Slide #31

Am29200 PIA Write Timing Am29200 + Am85C30

'PIACSx

RrW

Am85C30Serial

CommunicationsController

PIACS(S:O) I-!.t;;':2:=P'A::c::so===1PIAOE I- & ~PIAWE 1-....::::l~&>--A-3)----<~IWRCh~~~~ 10

A(23:0)t~==~~~~;JCID and24 A(2 AlB StatusINTO INTO

'D(7'O)E~~IDl7contr:~:: ~DRAM~

Controller 10

Am292DO RESET

Microcontroller

4- JTAGTest Port

~ ParallelPort

~ VideoInterface

~ VOPort

..-;.,..-. SerialPort

~ 2 ChannelDMA Controller

j

'PIAOE "

*PIAWE -+--+--t---:,i\ V"""""";--;-I ,

I I I I

I : ( D~ta i>-+:....- number ~f cycles d~termlned --..: final cycle extended

: by IOWAITx+1 : ~l,~~~~~~':

'WAIT

ID(31-O)

This is the timing of a PIA write cycle. The number ofcycles until the PIA Chip Select (*PIAcsx) and PIAWrite Enable (*PIAWE) are deasserted is dependentupon the value of Input/Output Wait States (IOWAITX)

field ofthe PIA control register in the microcontroller.The minimum access time for a PIA write is 4 cycles(3 wait states). Ifthe Input/Output Extend (IOEXTX)

field ofthe PIA control register is set, the next PIAaccess will be delayed one cycle for an additionalcycle of data hold time.

This is the interface between the Am29200microcontroller and the Am85C30 SCC. Note that theSCC doesn't have an explicit RESET signal; to achievea reset, the device expects *RD and *WR to be assertedat the same time. This interface shows an interruptdriven communication mechanism between themicrocontroller and the SCC. Assuming a 16-MHzmicrocontroller and an 8-MHz SCC, the SCC's PCLK isgenerated from the microcontroller's MEMCLK signalwith a divide-by-2 circuit. A complicating factor is theaccess recovery time of the SCC. The minimum timefrom the leading edge of one command to the leadingedge of the next command is defined as 3.5 times thePCLK cycle time. The access recovery time can begenerated in software by inserting delay instructions,or in hardware by adding an external PAL with delaystates or by using the microcontroller's WAIT signal.This design assumes that software assures theminimum access recovery time for the SCC.

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Slide #32

Code Example for Am85C30

Slide #33

Am29200 + Am79C30A_5erlaISend:

Save 6 Registers (gr96-gr101);

Control :: Ox90000007

Data .. Ox9000000F

End :0: Start + Length ·1;

Current '" Start;

$3: store 0,1 ,gr98,Controi ; TxRdy1

oe18y_Macroload O,'.grl00,ControlDelay_Macro

all 9r1OO,gr100,31-2

jmpf 9r1OO,$3

nop

load O,l,grl00,Current ; Send datastore 0,1,gr1oo,081.

Delay_Macro

add Current,Current,lcpleu grl00,Current,End

jmpt 9rloo,$3 ; More?

nop

R••tore 6 Register. (gr96-grl01)

impl IrQ

nop

.macro Delay_Macro

mfsr gr98,lrumt.,. Iru,gr98

const gr98,5

$1: jmptdec gr98,$1

nop

.endm

Am29200Mlcrocontroller

Am79C30ADigital Subscriber

Controller

serial 9A(2:0) Interface

p<-------.,-!:...-10(7'0)1-------iiNTI---..,.--lli~-IRESET

Oscillstor

When the SCC interrupts the microcontroller forservice by asserting *INTO, the processor interrogates the SCC's status register RR2 to determine thesource of the interrupt. This pseudo-code shows howserial information is sent using the SCC. Sixmicrocontroller registers are saved before being usedin the _SerialSend routine. The microcontroller setsthe SCC control register for transmit mode, and thenchecks the SCC's response. When the SCC is ready totransmit, the microcontroller gets the address of thesend buffer, and sends bytes until the message iscomplete. Delay_Macro consumes 6 cycles to meetthe SCC's minimum access recovery time. Becausethe Am29200 microcontroller can overlap loads andstores in the pipeline for better performance, thedelay macro includes a serializing instruction (MTSR,or move to special register), which won't allow loadsand stores to overlap. The special register used in theserializing instruction doesn't matter; here specialregister lru (least recently used indicator) for thememory management unit is used.


This is the interface between the Am29200microcontroller and the Am79C30A DSC device.Note that the DSC RESET is an active-high signal,while the Am29200 microcontroller *RESET is anactive-low signal.

Slide #34

Code ExampleSignal Interrupt Handler

_OSClm:; Proc....Ig~1conll IO,SIGUSRl : u_ defined IIgnaI numbersub map,map,.lion D,O,IO,map ; pelt SlgNI numbersub mlp,msp,4Ilore O,O,gr1,mspJ.ub map,mlp,4Slore G,O,rlb,map ; N"" ribsub mlp,mt,p,4Coni' 10,128°.SlJb n1b,rlb,1O : flx rib

push'r PCO,PC1,PC2,CHA,CHO,CHC,ALU,0f'S ; ....... SfMICIaII

mI., IO,OPS

IEn.urea that Handler Is -1--'-" 040,10,01; En-.urelnt. dlNbIMIexecuted with Interrupts ..,....- mt... 0f'S,1Odlubled. ;

sub map,map,411_ O,O,tI<t.msp ; ...... tal"

mtstlm me,O ; enaure Ioedm/I.tONm does not restartmtsr pc:l,s;gnel~""

-eld I2,~Regl..,4rnbr peO,12

Iret ;Goto~.-w:lChandW,lntscfiNl*'d

The easiest method to handle the DSC's interruptsis to utilize C signalsO and C interrupt handlers.This minimizes the amount of code that must bewritten by hand in assembly language and allowsthe developer to take advantage ofTsLink3™software from TeleSoft International, Inc. Written in

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ANSI C, the TsLink3™ software provides the developer with a proven efficient solution through Layer 3ofthe OSI model, and is compliant with ISDNguidelines for Q.391/X.25 protocols at Layer 3 andthe Q.921 LAPDILAPB protocols at Layer 2.TsLink3™ also includes the v.no and V.120 rateadaption protocols with a command interpreter forthe popular AT command set. Kits are available forthe world's major switch specifications, including USNational ISDN-I, AT&T 5ESS, Northern TelecomDMS-I00, European ETSI NET3, French VN2 (withVN3 coming soon), German ITR6, and JapaneseNTT INSnet64.

This signals-based interrupt handler for *INTO setsup the signal frame, saves necessary microcontrollerspecial registers defining the current environment,and then passes control to the C-based signalinterrupt handler. The interrupt handler executeswith interrupts disabled.

Slide #35

Slide #36

Debugging the Application

The ISDN terminal adapter can be designed usingan IBM-compatible PC (Am386(r) microprocessorclass or better), an SA29200 Evaluation Board andSA29200 Expansion Board, a Corelis Am29200microcontroller JTAG-based emulator, an HP 16500logic analyzer, and the TsLink3 software.

Now in the C language signal handler, the actualinterrupt is processed. First, the DSC interruptregister is read to determine what caused theinterrupt, and then the condition (transmit FIFOthreshold reached, receive FIFO threshold reached,etc.) is handled. Two C macros are used to communicate with the DSC: Rd_dscO to read an interruptregister (thus clearing the interrupt), and Wr_dscOto write a register in the DSC. This code is takendirectly from the TsLink3 software.

...,.( ..-gI.... w.g;

..-gI..... dar2;unalgnedcn.,Nt.;

/I loop while 05RI, DfAI, LSRI. ORTHRESH, or DTT'HRSH bit, Mlln In. osc/I Int.......ptR'1I.stef

wh'Ie(~.Rd_dac(DSC~INT~REGJ)'(DSAII DERII LSRIIORTliRSti I DTTHRSH) {r Proc>tu TI'1lI\SIl'IIl FIfO Th..-hold AMdled Inttrnlpt·'If (I"'O" DTTHA$H) I

ProI'lIe(DSC_IHT,l);

r while TrMamil Bun. Empty'/wNle({(dIa. Rd_cIsc:(OSC~DSR2) a TBEJ'" RaIn-..Dl'fIIenc) (

r..,...~loAFO·J

W,_dsc(OSC_D_BUR'. ·~In-...rntnext_);

AIoIn->VIllCt'Il-:)

I,. Procna Recelve FIFO Thrnhold RlMChed Interrupt'J

If('~"ORTHASHj (Proi'IIe(OSC_IHT,2);aaf2. RcUtac(OSC_DSR2);,. .... "-'"BytI .............nF!FO·/whIl1o(dw2" ABA)l,..-d. byte ftDm FIFO'f.~.Rd_dsc(DSC_D_BUFF);

1f((dat2. RCUlsc(DSC_0SR2))" L.8RPIIIISfC ACV_IP 1IO_'t...,...,.bytft ftDmd_buff In EOAP eocMIIlncktl __

R.m->rcvatat I- ReV_I';-,

CodeExample

Signal Handler Slide #37

SA29200 Evaluation Platform

The SA29200 Evaluation Board is a small formfactor board containing an Am29200 microcontroller,DRAM, an EPROM with the MiniMON29I{TM debugmonitor, and a serial port connector.


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Slide #38

SA29200 Extension Board

Slide #40

PC Platform

'" ! ;

"[l " iiii,. ..

0

The SA29200 Evaluation Board plugs into anSA29200 Expansion Board which contains headersockets for extra memory, a parallel port connector,and a wire-wrap area in which the DSC and SCC canbe wired.

Slide #39

Corelis JTAG Emulator

The PC does triple-duty as a software developmentplatform, the host side of the MiniMON29K debugmonitor, and the host platform for the JTAG emulator.

Slide #41

HP 16500 Logic Analyzer

•~lnmounted JTAGemulator board

The Corelis JTAG emulator is a low-cost in-circuitemulator that clips onto the Am29200microcontroller and uses the 5-pin JTAG port tostart, stop, and single-step the Am29200microcontroller, and to request current statusinformation from the microcontroller. It is a boardthat plugs into the expansion slot of a PC. A specialcable connects the emulator board to the systemunder development.


The HP 16500 is used to analyze system activity ona signallbus level. It works with the JTAG emulatorto provide comprehensive information about thesystem under development.

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1o


Slide #42

HP 16500 Analyzer ListingILObel>IIADOR II AM29200 Disassembly I~IROMDE/I~Bose>~ . mnemonics ROP.~~~

~ =~ STD:~ In:t'~\~o'r:;PEr97 g ~ ~ ~ ~7 000AAD Byte #1 0 7 lIE8 000AAD R~ Inst. Read: 0x00 0 7 1 0 E9 000AAE Byte #2 0 7 lIE10 000AAE R~ Inst. Read: 0x60 0 7 1 0 E11 000AAF Byte #3 0 7 lIE12 000AAF R~ Inst. Read: 0x61 0 7 1 0 E13 000AB0 CDHST gr97 ,0x008C 0 7 lIE

21 000AB4 CDHSTH gr97,0x8000 1 122 000A84 IQo4 Inst. Read: 0xel 1"23 000AB5 Byte #1 1 124 000AB5 R()l Inst. Read: 0x80 1 025 000AB6 Byte'2 1 126 000AB6 R()l Inst. Read: 0x61 1 027 000AB7 Byte #3 1 128 000AB7 R()l Inst. Read: 0x00 1 029 000080 Idle Cycle 0 130 000080 Idle Cycle 0 131 000080 Internal data access: 0 1

Serial Port Control Register

~~ =~ LOA~ In:t'~:d:r9:;P6r97 g

This HP 16500 display shows a part of the startupcode for the Am29200 microcontroller. The startupcode is located in a byte-wide EPROM, so themicrocontroller does four byte fetches for each 32-bitinstruction word. The lines labeled 5 through 12show bus activity for the fetching of a single instruction (STORE 0,OxOO,GR96,GR97) from byte-widememory; each memory access takes two cycles. TheRDP field indicates which DRAM or ROM bank wasaccessed; in this case, the accesses were all to ROMbankO.

The microcontroller's three STAT (status) signals showwhat the microcontroller was doing during theprevious cycle. A status of 7 indicates that themicrocontroller was idle (data/instruction not valid).A status of 5 indicates that the microcontroller wasexecuting during the previous cycle. A status of 6indicates that the microcontroller executed aninternal data access (to an internal peripheral), inthis case to the serial port.

The R/*w signal indicates if a read access is takingplace (1) or a write access is taking place (0). The*ROMOE signal is asserted (0) when the output enableto the EPROM is asserted; the analyzer listing showsthat the microcontroller's ROM Controller wascorrectly programmed for two-cycle access memories.The ROMcs30 field shows the ROM chip selects thathave been asserted; there is one chip select for eachof the four allowed ROM banks. The startup code isall located in ROM bank 0, so this is the only chipselect asserted during this listing. Note that duringthe internal access to the microcontroller's serialport, no ROM banks are enabled.


Slide #43

HP 16500 Analyzer Listing

[Lebolj IAllOR I I "29200 Disass..bly rumiR?i'-~~ICAS30/jRAS30/1Bose>~ I "",,,,,,,,ics RD~~~ Hex~~~

16 000024 CONST lr3,0x40C417 000024 DIWl Inst. Read from 0x402418 000024 DIW4 Inst. Read from 0x402419 000028 CONSTH lr3,0x409020 000028 DIW4 Inst. Read frOll 0x462821 00004A Idle cycleZZ 00004A DRAM Write: 0x40000C50 to 0x96E8 323 9996E8 DRAM Wri. te: 0x40000C50 to 0x96E8 324 9006E8 DIW4 Wri. te: 0x40000CS0 to 0x96E8 325 000020 Idle cycle26 0000l{ CONST lrZ.0x004e27 00002C MAN Inst. Read froM 0x-402C28 00002C MAN Inst. Read frOlll 0x-40ZCZ9 099930 HALT30 000030 MAN lnst. Read fr'Olll 0x-402031 000034 ASNEQ 69,sp,sp32 099934 ClIWl lnst. Read frOlll 0x402433 000038 CONST lr3,0x40EC34 000038 ClIWl Inst. Read frM 0x40283S 000038 Idle cycle36 099938 Halted

This HP 16500 display shows the execution of asequence of code that includes a breakpoint set by theJTAG emulator. The code executes out of 3-cycle firstaccess, 2-cycle page mode access DRAM located inDRAM bank 3.

Again the STAT signals show what the microcontrollerwas doing in the previous cycle; a status of 4 indicates an external data access, in this case to DRAMbank 3. The *TR/*OE signal provides an output enablefor read accesses. The *WE signal provides a writeenable for write accesses.

The grouped signals *cAS3..0 and *RAS3..0 show thestate of RAS and CAS for each of the four DRAM banks.

In this listing, a software breakpoint was set ataddress Ox030 in DRAM bank 3 using the JTAGemulator. The emulator replaced the instruction ataddress Ox030 with a HALT instruction and assertedthe control signals necessary to have themicrocontroller report to the emulator when the HALTinstruction is encountered. Because themicrocontroller is pipelined, the fetch of the HALTinstruction occurs at lines 29-30 but isn't executeduntil line 36.

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Slide #44 Slide #45

IJ-~··~~:·II.. _. ' :"' ,

~~;;i>

Debugging the Application

Am85C30$erial

CommsControner

Am79C30ADigital

SubscriberController

serial Port

'n.trucllonlD.t.I.-___..............

Am29200Microcontroller

Address

ISDN Terminal AdapterFunctional Block Diagram

An ISDN terminal adapter has been developed usingan Am29200 microcontroller, an Am85C30 serialcommunications controller, and an Am79C30Adigital subscriber controller. This ISDN terminaladapter interlaces non-ISDN equipment to an ISDNnetwork between the R and Str ISDN referencepoints. With an ISDN terminal adapter, the user isable to send both voice and data informationdigitally, accruing the benefits of increasedreliability, new functionality, and lower cost overcurrent analog solutions.

This ISDN terminal adapter can easily be developedin the lab using an IBM-compatible PC (Am386(r)microprocessor-class or better), an SA29200 Evaluation Board and SA29200 Expansion Board, a CorelisAm29200 JTAG-based emulator, an HP 16500 logicanalyzer, and the TsLink3 software.

Glossary ofTerms and Conditions

Basic rate: The 192-kbps connection between thesubscriber and the network. It contains twoB-channels and one D-channel.

Bit Stuffing: A type of rate adaption that adds nondata dummy bits to bring the data rate up to64 kbps. In addition, multiple channels can bemultiplexed to bring up the data rate.However, bit stuffing does not supportstatistical multiplexing or error-checkingand retransmission.

BiSYNC: A synchronous character-oriented transmission protocol. BiSYNC is used primarily byIBM. A special "sync" character precedes andends the data being transmitted. The synccharacter is chosen such that its bit pattern issignificantly different than the other characters being transmitted.

B-channel: A 64-kbps channel that can be used foreither data or digitized voice communications.

CCnT: Consultative Committee on International Telegraphy and Telephony: Theorganization responsible for the ISDN standard, among others. The CCITT is part of theITU (International TelecommunicationsUnion), one ofthe oldest organizations in theUnited Nations.

Central office: The lowest level of switching in thepublic telephone network. A residentialtelephone or business PABX connects to thepublic network at a central office.

DLC: Data Link Controller: A functional block inthe DSC that perlorms processing of Layer-1and partial Layer-2 LAPD protocol for theD channel.


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DMI: Digital Multiplexed Interface: DMI is afreely licensed specification from AT&T thatcontains four modes, three of which arecommonly used in full data rate B channeltransmission.

DSC: The Am79C30A Digital Subscriber Controller. An integrated chip that handles basicrate ISDN services for both voice and data.

DSP: Digital Signal Processing: A softwaremethod of digitally processing analog signals.

D-channel: A 16-kb/s channel provided by the ISDNbasic rate interface. The D-channel is primarilyused for call-control signaling functions. It canalso be used for low priority, low-speed userdata at rates up to 9600-bps.

FCS: Frame Check Sequence: A method of detecting errors in the LAPD protocol.

HDLC: High-Level Data Link Control: A bitoriented synchronous communications protocolthat uses a special bit pattern (the flag) tomark the beginning and end of data transmissions. If the data contains a flag, an extra 0 isinserted into the data stream; this is known asbit stuffing.

IDC: The Am79C32A ISDN Data Controller: Anintegrated chip that handles basic rate ISDNservices for data only.

ISDN: Integrated Digital Services Network: Aninternational standard for digital voice anddata transmission over the switched telephonenetwork.

ISO: International Standards Organization: Aninternational organization that sets worldwidestandards in telecommunications and otherfields.

JTAG: Joint Test Access Group: The name ofthegroup responsible for a 5-pin test and debuginterface codified in IEEE 1149.1 specification.JTAG is also used generically as the name forany implementation that meets the IEEE1149.1 specification.

LAPB: Link Access Protocol Balanced: A subsetof the HDLC OSI Layer-2 communicationsprotocol. LAPB is the accepted Layer-2 protocolof CCITT's X.25 packet switch specification,and establishes and maintains an errorcontrolled point-to-point link between a terminal and the packet network.


LAPD: Link Access Protocol D-channel: TheOSI Layer-2 protocol defined by CCITT for usein ISDN's D-channel. LAPD can be used on theB channels as well (eg, V.120, DMI mode 3)and many times is preferred because only onesoftware package needs to be supported for allchannels.

Layer-2 protocol: Refers to Layer 2 (Data LinkLayer) of the OSI communications model.Layer-2 converts an unreliable transmissionchannel into a reliable one; sends frames ofdata with a checksum; and uses error detection and acknowledgment. Standards thatimplement Layer-2 protocol include HDLC,SDLC, and BiSYNC.

Layer-3 protocol: Refers to Layer 3 (NetworkLayer) of the OSI communications model.Layer-3 transmits packets of data through anetwork. It is responsible for routing andcongestion control. Standards that implementLayer-3 protocol include X.25.

LID: Line Interface Unit: The functional block inthe DSC that interfaces to an ISDN S or Treference point.

LT: Line Tennination: Interfaces to the ISDN Ureference point. The LT is located in thetelephone company's switch, often at thecentral office. The LT performs Layer-1functions for Band D channels, and Layer-2and Layer-3 functions for D channels.

MAP: Main Audio Processor: The functionalblock in the DSC that provides a telephoneaudio interface.

MPI: Microprocessor Interface: The functionalblock in the DSC that interfaces to an externalmicroprocessor or microcontroller.

NT: Network Tennination: There are two types ofNTs: NT1 and NT2. The NT1 acts as a repeater and performs two- to four-wire conversion (U to S interface). An NT1 deals only withLayer-1 of the OSI model. NT2s are intelligentand actively participate in the call routing!control process. PABXs and line concentratorsare examples ofNT2 devices. NT2 devices canbe connected to multiple types ofISDN linessimultaneously. NT devices often form theboundary between equipment owned by thecustomer and equipment owned by thetelephone company.

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OSI: Open Systems Interconnection: A sevenlayer model of communications servicesdeveloped by the ISO. This layered model ofcommunications divorces upper layers fromchanges in technology in lower layers.

PABX: Private Automatic Branch Exchange: Atelephone exchange on the user's premises. Itserves as a private central office and attachesto the public network at a central office onthe network.

PIA: Peripheral Interface Adapter: The genericperipheral interface defined for the Am29200microcontroller.

Primary rate: An expensive, high-bandwidth ISDNconnection. The primary rate interface iscomposed of multiple B channels and one 64kbps D channel.

R Reference point: The R reference point establishes the boundary between non-ISDN equipment and the ISDN network. Terminal adapters are used to convert the protocol used by thenon-ISDN terminal to ISDN basic rate orprimary rate protocol.

Reference points: CCITT-identified interfaceswith established standards for both hardwareand software.

S Reference Point: The CCITT designation for theconnection between terminal equipment (TE)and the network terminator (NT2), or betweenTAs and TEs and NT1 ifthere is no NT2.

SDLC: Synchronous Data Link Control:An OSI Layer-2 bit-oriented synchronouscommunications protocol.

SNA: Systems Network Architecture: A structureof data protocols developed by IBM thatpredates the OSI model.


Subscriber loop: The connection between thecentral office or PABX and the user'sequipment.

T Reference point: The CCITT designation forthe connection between NT1 and NT2. If noNT2 is present, there is no T reference point.

TA: Terminal adapter: A device that connectsa non-ISDN device between the R and Sinterface.

TE: Terminal Equipment: An ISDN-compatibledevice connection to the Sir reference points.A TE can be a computer, telephone, dataterminal, etc.

U Reference point: The CCITT designation forthe connection between the LT and NTl.Normally, a two-wire basic rate interface or aprimary rate line is used, but the four-wirebasic rate interface can also be used.

v.no: The CCITT recommendation for interfacingnon-ISDN equipment to the ISDN using thebit-stuffing technique. ECMA 102 is theEuropean Computer Manufacturer'sAssociation's version ofV.ll0.

V.120: The CCITT recommendation for interfacingnon-ISDN equipment to the ISDN usingpacketizing techniques. V.120 uses LAPD,provides rate adaption via statisticalmultiplexing, and supports multiple logicconnections.

X.25: The CCITT international packet-orientedprotocol used primarily at Layer 3 of the OSImodel. channel is primarily used for callcontrol signaling functions. It can also be usedfor low-speed user data.

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