Upload
others
View
7
Download
0
Embed Size (px)
Citation preview
Rev. 1.30 1 February 13, 2017 Rev. 1.00 PB February 13, 2017
HT16K23RAM Mapping 20×4/16×8 LCD
Controller Driver with Keyscan
Feature• Logicvoltage:2.4V~5.5V• IntegratedRCoscillator• Variousdisplaymodes
Max.20×4patterns,20segments,4commons,1/3bias,1/4duty Max.16×8patterns,16segments,8commons,1/4bias,1/8duty
• I2C-businterface• Keyscanfunction
Max.20×1matrixkeyscanningin20×4displaymode Max.16×1matrixkeyscanningin16×8displaymode
• 16×8bitsRAMfordisplaydatastorage• Selectablehardwareinterrupt• R/Waddressautoincrement• ManufacturedinsilicongateCOMSprocess• 28-pinSOPpackage
Applications• Industrialcontrolindicator• Digitalclock,thermometer,counter,voltmeter• Comboset• VCRset• Instrumentationreadouts• Otherconsumerapplication• LCDdisplays
General DescriptionTheHT16K23 is amemorymapping andmulti-functionLCDcontrollerdriver.TheMax.displaysegment numbers in the device are 80 patterns(20segmentsand4commons)or128patterns (16segments and 8 commons).TheMax. key scancircuitsare20×1matrixor16×1matrix.Thesoftwareconfiguration feature of theHT16K23makes itsuitable formultipleLCDapplications includingLCDmodulesanddisplaysubsystems.TheHT16K23supportsahardwareinterruptusingregistersetting.
TheHT16K23iscompatiblewithmostmicrocontrollersandcommunicatesviaa two-linebidirectional I2C-bus.
Rev. 1.30 2 February 13, 2017
HT16K23
Block Diagram
LCD Driver / Keyscan circuit / Device address selecting circuit
Display RAM16x8bits
Timing generator
I2C Controller
VDD
VSS
SDA
SCL
Power_on reset
SEG0/K0
Key data RAM20x1 bits
SEG1/K1
SEG2/K2
SEG15/K15/INT
SEG14/K14
SEG13/K13
LCD biascircuit
Internal RCOscillator
COM3
COM2
COM1
COM0
SEG19/COM4/K19/INT
SEG18/COM5/K18
SEG17/COM6/K17
SEG16/COM7/K16
Pin Assignment� �� �� �� �� �� �� �� �� �� �� �� �� �� �
���������� �� �� �� �� �
� � � � � � �� � � � � � � �
� � �� � � �� � � �� � � �� � � �
� � � � � � � � � � � � � � � �
� � � � � � � � � � � � �� � � � � � � � � � � � �� � � � � � � � � � � � �
� � � � � � � � � � �
� � � � � � � �� � � � � � � �� � � � � � � �� � � � � � � �
� � �� � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � �� � � � � � � �
Rev. 1.30 3 February 13, 2017
HT16K23
Pad Coordinatesunit:μm2
No Pad Name X Y No Pad Name X Y
123456789101112131415
COM3SEG19/COM4/K19/INT
SEG18/COM5/K18SEG17/COM6/K17SEG16/COM7/K16
SEG15/K15/INTN.C.
SEG14/K14SEG13/K13SEG12/K12SEG11/K11SEG10/K10SEG9/K9SEG8/K8SEG7/K7
-400.967 -479.400-479.400-479.400-479.400-479.400-182.270
-3.50081.500
166.500251.500336.500421.500479.400479.400
924.900-496.281-592.981-677.981-762.981-868.000-392.291-924.900-924.900-924.900-924.900-924.900-924.900-538.200-453.200
161718192021222324252627282930
SEG6/K6SEG5/K5SEG4/K4SEG3/K3SEG2/K2SEG1/K1SEG0/K0
SCLSDA
VLCDVDDVSS
COM0COM1COM2
479.400479.400479.400479.400479.400479.400400.967305.917220.917132.31747.317
-60.967-145.967-230.967-315.967
-368.200-283.200-198.200-113.200-28.20056.800
924.900924.900924.900924.900924.950924.950924.900924.900924.900
Pad Assignment
14
30 29
2
4
7
(0, 0)
3
5
68 9 10 11 12 13
151617
1819
2021
222324252627281
SE
G0/K
0S
CL
SD
AV
LCD
VD
D
VS
SC
OM
0C
OM
1C
OM
2C
OM
3
SEG19/COM4/K19/INT
SEG18/COM5/K18
SEG17/COM6/K17
SEG16/COM7/K16
SEG15/K15/INT
SE
G9/K
9S
EG
10/K10
SE
G11/K
11S
EG
12/K12
SE
G13/K
13S
EG
14/K14
SEG1/K1SEG2/K2SEG3/K3SEG4/K4SEG5/K5SEG6/K6SEG7/K7SEG8/K8
N.C.
Chipsize:1167×2058μm2
TheICsubstrateshouldbeconnectedtoVSSinthePCBlayoutartwork.
TheVLCDandVDDshouldbebondedtogether.
Rev. 1.30 4 February 13, 2017
HT16K23
Pin DescriptionPin Name Type Description
SDA I/O Serial Data Input/Output for I2C interface.
SCL I Serial Clock Input for I2C.
VDD — Positive power supply for logic circuits.
VSS — Negative power supply for logic circuits, ground.
COM0 ~ COM3 O LCD Common output.
SEG0/K0 ~SEG14/K14 I/O
● LCD Segment output. ● Key data input, internal pull-low during key scan.
SEG15/K15/INT I/O
● When the “M” bit of the mode set command is set to “1”, and the “INT/ROW” bit of the mode set command is set to “0”, this pin becomes an LCD Segment output and key data input with internal pull-low during key scan. ● When the “M” bit of the mode set command is set to “1”, and the “INT/ROW” bit of the mode set command is set to “1”, this pin becomes an INT pin, interrupt signal out. INT is output active-low when the “ACT” bit of mode set command is set to “0”, The INT output is active-high when the “ACT” bit of the mode set command is set to “1”
SEG16/COM7/K16 ~SEG18/COM5/K18 I/O
● When the “M” bit of the mode set command is set to “0”, this pin becomes an LCD Segment output and a key data input with internal pull-low during a key scan. ● When the “M” bit of the mode set command is set to “1”, this pin becomes an LCD Common output.
SEG19/COM4/K19/INT I/O
● When the “M” bit of the mode set command is set to “0”, and the “INT/ROW” bit of the mode set command is set to “0”, this pin becomes a LCD Segment output and a key data input with internal pull-low during key scan. ● When the “M” bit of the mode set command is set to “0”, and the “INT/ROW” bit of the mode set command is set to “1”, this pin becomes an INT pin, interrupt signal out. The INT output is active-low when the “ACT” bit of the mode set command is set to “0”, The INT output active-high when the “ACT” bit of the mode set command is set to “1” ● When the “M” bit of the mode set command is set to “1”, this pin becomes an LCD Common output.
Rev. 1.30 5 February 13, 2017
HT16K23
Approximate Internal Connections
VDD
GND
SCL, SDA
Vselect-on
Vselect-off
COM0~COM3
Vselect-on
Vselect-off
SEG15/K15/INTSEG19/COM4/K19/INT
Vselect-on
Vselect-off
SEG0/K0 ~ SEG14/K14SEG16/COM7/K16~SEG18/COM5/K18
Absolute Maximum RatingsSupplyVoltage.......................................................................................................................VSS-0.3VtoVSS+6.5V
InputVoltage.........................................................................................................................VSS-0.3VtoVDD+0.3V
StorageTemperature........................................................................................................................ -55°Cto150°C
OperatingTemperature...................................................................................................................... -40°Cto85°C
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder“AbsoluteMaximumRatings”maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnot impliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.
Rev. 1.30 6 February 13, 2017
HT16K23
D.C. CharacteristicsVDD=2.4V~5.5V; Ta=25°C (Unless otherwise specified)
Symbol ParameterTest condition
Min. Typ. Max. UnitVDD Condition
VDD Operating Voltage — — 2.4 — 5.5 V
IDD1 Operating Current3V No load, LCD On,
20×4 display mode— 155 310 μA
5V — 260 420 μA
IDD2 Operating Current3V No load, LCD Off,
20×4 display mode— 8 30 μA
5V — 20 60 μA
ISTB Standby Current3V
No load, standby mode— 1 3 μA
5V — 2 5 μAVIL Input Low Voltage — SDA, SCL 0 — 0.3VDD VVIH Input High Voltage — SDA, SCL 0.7VDD — VDD VIIL Input leakage current — VIN = VSS or VDD -1 — 1 μA
IOL Low level output current3V
VOL=0.4V, SDA3 — — mA
5V 6 — — mA
IOL1 LCD Common Sink Current3V VOL=0.3V 80 160 — μA5V VOL=0.5V 180 360 — μA
IOH1 LCD Common Source Current3V VOH=2.7V -80 -120 — μA5V VOH=4.5V -120 -200 — μA
IOL2 LCD Segment Sink Current3V VOL=0.3V 60 120 — μA5V VOL=0.5V 120 200 — μA
IOH2 LCD Segment Source Current3V VOH=2.7V -40 -70 — μA5V VOH=4.5V -70 -140 — μA
IOL3 INT Sink Current3V VOL=0.3V 1 — — mA5V VOL=0.5V 2 — — mA
IOH3 INT Source Current3V VOH=2.7V -1 — — mA5V VOH=4.5V -2 — — mA
RPL Input pull-low Resistance3V SEG0/K0~SEG19/K19,
during keyscan period220 400 600
KΩ5V 220 400 600
A.C. CharacteristicsVDD=2.4V~5.5V; Ta=25°C (Unless otherwise specified)
Symbol ParameterTest condition
Min. Typ. Max. UnitVDD Condition
fLCD LCD Frame Frequency3V 20×4 display mode
16×8 display mode 58 72 90 Hz5VtOFF VDD OFF Times — VDD drop down to 0V 20 — — MstSR VDD Slew Rate — — 0.05 — — V/ms
Note:1.IfthePoweronResettimingconditionsarenotsatisfiedinthepowerOn/Offsequence,theinternalPoweronResetcircuitwillnotoperatenormally.
2.IfVDDdropsbelowtheminimumvoltageoftheoperatingvoltagespec.duringoperating,thePoweronResettimingconditionsmustalsobesatisfied.Thatis,VDDmustdropto0Vandremainat0Vfor20ms(min.)beforerisingtothenormaloperatingvoltage.
Rev. 1.30 7 February 13, 2017
HT16K23
A.C. Characteristics − I2C-BusTa=25°C (Unless otherwise specified)
Symbol ParameterTest condition VDD=2.4V to 5.5V VDD=3.0V to 5.5V
UnitCondition Min. Max. Min. Max.
fSCL Clock Frequency — — 100 — 400 kHz
tBUF Bus Free TimeTime in which the bus must be free before a new transmission can start
4.7 — 1.3 — μs
tHD; STA Start Condition Hold TimeAfter this period, the first clock pulse is generated 4 — 0.6 — μs
tLOW SCL Low Time — 4.7 — 1.3 — μstHIGH SCL High Time — 4 — 0.6 — μs
tSU; STA Start Condition Set-up TimeOnly relevant for repeated START condition. 4.7 — 0.6 — μs
tHD; DAT Data Hold Time — 0 — 0 — μstSU; DAT Data Set-up Time — 250 — 100 — nstr Rise Time Note — 1 — 0.3 μstf Fall Time Note — 0.3 — 0.3 μs tSU; STO Stop Condition Set-up Time — 4 — 0.6 — μstAA Output Valid from Clock — — 3.5 — 0.9 μs
tSPInput Filter Time Constant(SDA and SCL Pins) Noise suppression time — 100 — 50 ns
Note:Theseparametersareperiodicallysampledbutnot100%tested.
Timing Diagrams• I2C Timing
SDA
SCL
tf
tHD:SDA
tLOW tr
tHD:DAT
tSU:DAT
tHIGH tSU:STA
tHD:STA
S Sr
tSP
tSU:STOP
tBUF
StAA
SDAOUT
• Power-on Reset Timing� � �
� � �� � � �
Rev. 1.30 8 February 13, 2017
HT16K23
Wake-up
Standby mode command set from MCU
Read key data command set from MCU
INT flag or INT pin output
Any key
Press
Release key
2 frame cycle
Normal active statusHT16K23 operation status
Standby status
Press
2 frame cycle< 2 frame cycle
Release key
Normal active status
Press Release
(When the act bit is set to “1”)
Key data are updated Key data are updated
When after the key data has been read,Clears the key data RAM.
When after the key data has been read,Clears the key data RAM.
Functional Description
Power-on ResetWhenpower is turnedon, the IC is initialisedbytheinternalpower-onresetcircuit.Thestatusof theinternalcircuitafterinitializationisasfollows:
• Displaymode is 20×4, 20 segments and 4commons.
• Systemoscillatorisoff.• LCDDisplayisoff.• Keyscanstopped.• AllcommonpinsaresettoVSS.• Allsegmentpinsareinaninputstate.• SEG19/COM4/INTpinissettosegmentdriver.• Thecontrolregisters,keydataRAManddisplaydataRAMaresettoadefaultvalue.
Data transfersontheI2C-busshouldbeavoidedfor1msfollowingpower-ontoallowcompletionoftheresetprocedure.
Standby ModeIn the standbymode, theHT16K23cannotacceptanyinputcommandorwritedatatothedisplayRAMexceptforthesystemsetcommand.
Ifstandbymodeisselectedwiththe“S”bitofsystemsetcommandisset to“0”, thestatusof thestandbymodeisasfollows:
• SystemOscillatorisoff.• LCDdisplayisoff.
• Keyscanstopped.• AllkeydataandINTflagsarecleared,until thestandbymodeiscancelled.
• Thekeymatrixispushedbyanykeyorifthe“S”bitof thesystemsetcommandisset to“1”, thisstandbymodewillbecancelledandthedevicewillwake-up.
• AllcommonpinsaresettoVSS.• Ifthe“INT/ROW”bitofmodesetcommandissetto“0”,allsegmentpinsarechangedtoinputpins.
• Ifthe“INT/ROW”bitofmodesetcommandissetto“1”:allsegmentpinsarechangedtoinputpinsexceptfortheINTpin(output).
• TheINTpinoutputkeepsahigh levelwhen the“ACT”bitofthemodesetcommandissetto“0”,.TheINTpinoutputkeepstoalowlevelwhenthe“ACT”bitofthemodesetcommandissetto“1”,ifthe“INT/ROW”bitofmodesetcommandissetto“1”.
Wake-up• Wake-upisimplementedbyakeypressbyanykeyorifthe“S”bitofthesystemsetcommandissetto“1”.Thenakeyscanisperformed.
• SystemOscillatorrestartsfornormaloperation.• Thepreviousoutputwillbedisplayeduntilupdatedbyeachmodecommandset.
• The relationshipbetweenWake-upandanykeypressdelaytimelessandINToutputandINTflagstatusisasfollows:
Rev. 1.30 9 February 13, 2017
HT16K23
System OscillatorTheinternallogicandtheLCDdriversignalsoftheHT16K23aretimedbytheintegratedRCoscillator.
TheSystemClock frequency (fSYS)determines theLCDframefrequency.Aclocksignalmustalwaysbesuppliedtothedeviceasremovingtheclockmayfreeze thestandbymodecommand isexecuted.Atinitialsystempoweron, theSystemOscillator is inthestopstate.
LCD Bias GeneratorThefull-scaleLCDvoltage(Vop) isobtainedfromVDD~VSS.
FractionalLCDbiasingvoltagesareobtainedfroman internalvoltagedividerof threeseries resistorsconnectedbetweenVLCDandVSS.Thecentreresistorcanbeswitchedoutofthecircuittoprovidea1/3biasvoltagelevelforthe1/4dutyconfigurationor1/4biasvoltagelevelforthe1/8dutyconfiguration.
Segment Driver OutputsTheLCDdriver section includes segmentoutputswhich should be connected directly to theLCDpanel.Thesegmentoutputsignalsaregenerated inaccordancewiththemultiplexedcolumnsignalsandwiththedataresidentinthedisplaylatch.Theunusedsegmentoutputsshouldbeleftopen-circuit.
System Set CommandThiscommandisusedtosetthefollowfunctions.
• TheHT16K23operates innormalmodeorstandbymode.Before thestandbymodecommandissent, it isstronglyrecommendedtoreadkeydatafirst.
• LCDdisplayon/off
NameCommand
Option Description Def.D7 D6 D5 D4 D3 D2 D1 D0
System set 1 0 0 0 0 0 D S
SStandby mode selecting
● {0}: standby mode ● {1}: normal mode
80H
DLCD display on/off
● {0}: LCD display off ● {1}: LCD display on
Mode Set CommandThiscommandisusedtosetthefollowfunctions.
• Displaymodeselecting,20×4displaymodeor16×8displaymode.• SettheHT16K23SEG/INTporttobeasegmentoutputoranINToutput.• INToutputisactive-loworactive-high.
NameCommand
Option Description Def.D7 D6 D5 D4 D3 D2 D1 D0
Mode set 1 0 1 0 0 ACT
INT/ROW M
MLCD display mode selecting
● {0}: 20×4 display mode ● {1}:16×8 display mode
A0HINT/ROW
Segment or INT pin selecting ● {0}: Segment output SEG19/COM4/K19/INT is segment output in 20×4 display mode.SEG15/K15/INT is segment output in 16×8 display mode. ● {1}: INT outputSEG19/COM4/K19/INT is INT output in 20×4 display mode.SEG15/K15/INT is INT output in 16×8 display mode.
ACTINT output level selection,
● {0}: INT output is active-low. ● {1}: INT output is active-high.
Rev. 1.30 10 February 13, 2017
HT16K23
Output COM3 COM2 COM1 COM0 Output COM3 COM2 COM1 COM0 addressSEG1 — — — — SEG0 — — — — 00HSEG3 — — — — SEG2 — — — — 01HSEG5 — — — — SEG4 — — — — 02HSEG7 — — — — SEG6 — — — — 03HSEG9 — — — — SEG8 — — — — 04HSEG11 — — — — SEG10 — — — — 05HSEG13 — — — — SEG12 — — — — 06HSEG15 — — — — SEG14 — — — — 07HSEG17 — — — — SEG16 — — — — 08HSEG19 — — — — SEG18 — — — — 09H
D7 D6 D5 D4 D3 D2 D1 D0 Data
RAM Mapping of 20×4 Display Mode
Output COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 addressSEG0 — — — — — — — — 00HSEG1 — — — — — — — — 01HSEG2 — — — — — — — — 02HSEG3 — — — — — — — — 03HSEG4 — — — — — — — — 04HSEG5 — — — — — — — — 05HSEG6 — — — — — — — — 06HSEG7 — — — — — — — — 07HSEG8 — — — — — — — — 08HSEG9 — — — — — — — — 09HSEG10 — — — — — — — — 0AHSEG11 — — — — — — — — 0BHSEG12 — — — — — — — — 0CHSEG13 — — — — — — — — 0DHSEG14 — — — — — — — — 0EHSEG15 — — — — — — — — 0FH
D7 D6 D5 D4 D3 D2 D1 D0 Data
RAM Mapping of 16×8 Display Mode
D7
MSB
D6 D5 D4 D3 D2 D1 D0
LSB
Common Driver OutputsTheLCDdriver section includes columnoutputswhich should be connected directly to theLCDpanel.Thecommonoutputsignalsaregenerated inaccordancewith theselectedLCDdrivemode.Theunusedcolumnoutputsshouldbeleftopen-circuit.
Display Memory – RAM StructureThedisplayRAMisastatic16x8-bitRAMwheretheLCDdataisstored.Alogic“1”intheRAMbit-mapindicatesthe“on”stateofthecorrespondingLCDsegment;similarlyalogic0indicatesthe“off”state.
There isaone-to-onecorrespondencebetween theRAMaddressesandthesegmentoutputs,andbetweenthe individualbitsofaRAMwordand thecolumnoutputs.ThefollowingtablesshowthemappingfromtheRAMtotheLCDpattern:
Rev. 1.30 11 February 13, 2017
HT16K23
LCD Drive Mode Waveforms
• 20×4 Display Mode, 1/4 Duty , 1/3 Bias
VDD
V1
V2
VSS
COM0
VDD
V1
V2
VSS
COM1
VDD
V1
V2
VSS
COM2
VDD
V1
V2
VSS
COM3
VDD
V1
V2
VSS
SEG0(K0)~SEG19(K19)
1 frame
Key scan periodDisplay period
Rev. 1.30 12 February 13, 2017
HT16K23
• 16×8 Display Mode, 1/8 Duty , 1/4 Bias
VDD
V1
V2
V3
VSS
COM0
VDD
V1
V2
V3
VSS
COM1
VDD
V1
V2
V3
VSS
COM2
VDD
V1
V2
V3
VSS
COM3
VDD
V1
V2
V3
VSS
COM4
VDD
V1
V2
V3
VSS
COM5
V1
VDD
V2V3
VSS
COM6
V1
VDD
V2V3
VSS
COM7
V1
VDD
V2
V3
VSS
SEG0/K0~SEG15/K15
Display period Key scan period
1 frame
Rev. 1.30 13 February 13, 2017
HT16K23
INT flag register Address code R/WRegister Data
D7 D6 D5 D4 D3 D2 D1 D0 Def.INT flag register 0X30H R 0 0 0 0 0 0 0 INT flag 00H
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame
INT flag
INT pin(active high)
INT pin(active low)
When the interrupt asserted if required:1. Key data are updated2. Slave address are updated
When after the all key data has been read: 1. Clears the key debounced register 2. The INT flag bit is set to "0"3. The INT pin goes to low when "act" bit is set to "1"4. The INT pin goes to high when "act" bit is ise to "0"
Press first key
7th frame 8th frame
Realease key
9th frame
Key data updated Realease keyPress second key
Keyscan• TheHT16K23supportsa20×1matrixkeyscaninthe20×4displaymodeanda16×1matrixkeyscaninthe16×8displaymode.
• The hardware interrupt function is optional,allowingSEG19/COM4/K19/INT in the 20×4displaymodeorSEG15/K15/INTtobeusedasanINToutputorasasegmentdriver.The interruptflagcanberead(polled)throughtheserialinterfaceinstead.
• Thekeyscaninputpinsaresharedwithsegmentoutputpins.
• Thekeyscancycle loopscontinuouslywith time,withallkeysexperiencingafullkeyscandebounceofover20ms.Akeypress isdebouncedandaninterrupt issued ifat leastonekey thatwasnotpressedinapreviouscycleisfoundpressedduringbothsamplingperiods.
• INToutputisactive-lowwhenthe“act”bitofthemodesetcommandissetto“0”.
• INToutputisactive-highwhenthe“act”bitofthemodesetcommandissetto“1”.
Keyscan and INT Timing• Thekeydata isupdatedand theINTfunction ischanged if thekeyhasbeenpressed for2key-cycles.
• TheINTfunctionischangedwhenthefirstkeyhasbeenpressed.
• After thekeydatahasbeen read, thekeydataregistersareclearedto“0”andtheINTflagbitissetto“0”.TheINTpingoeslowwhenthe“ACT”bitofthemodesetcommandissetto“1”.
• After thekeydatahasbeen read, thekeydataregistersarecleared to“0”and the INTflagbitisset to“1”,andtheINTpingoes lowwhenthe“ACT”bitofthemodesetcommandissetto“0”.
• TheINTflagregisterisshownbelow.TocleartheINTflagstatus,thekeydataregistermustbereadfrom0x20H~0x22Hinoneoperation.
Rev. 1.30 14 February 13, 2017
HT16K23
Key data register AddressCode R/WRegister Data
D7 D6 D5 D4 D3 D2 D1 D0 Def.
Key data register address point0x20H R K7 K6 K5 K4 K3 K2 K1 K0 00H0x21H R K15 K14 K13 K12 K11 K10 K9 K8 00H0x22H R 0 0 0 0 K19 K18 K17 K16 00H
Key Matrix ConfigurationThereisakeyscancircuit integral totheHT16K23whichcandetectakeypress.Itincludestwentyinputs(K0toK19,sharedwithSEG0toSEG19)inthe20×4displaymodeorsixteen inputs (K0 toK15,sharedwithSEG0toSEG15)inthe16×8displaymode.
The keymatrix has a 20×1matrix in the 20×4displaymodeora16×1matrix in the16×8displayconfigurationasshownbelow:
SE
G0/
K0
SE
G1/
K1
SE
G2/
K2
SE
G3/
K3
SE
G4/
K4
SE
G5/
K5
SE
G6/
K6
SE
G7/
K7
SE
G8/
K8
SE
G9/
K9
SE
G10
/K10
SE
G11
/K11
SE
G12
/K12
SE
G13
/K13
SE
G14
/K14
SE
G15
/K15
SE
G16
/K16
SE
G17
/K17
SE
G18
/K18
SE
G19
/K19
VDD
=
20×1 Matrix in 20×4 Display Mode
VDD
SE
G0/
K0
SE
G1/
K1
SE
G2/
K2
SE
G3/
K3
SE
G4/
K4
SE
G5/
K5
SE
G6/
K6
SE
G7/
K7
SE
G8/
K8
SE
G9/
K9
SE
G10
/K10
SE
G11
/K11
SE
G12
/K12
=
SE
G13
/K13
SE
G14
/K14
SE
G15
/K15
16×1 Matrix in 16×8 Display Mode
Key Data RegisterAfter thekeydataregistershavebeenread, thekeydataregistersareclearedto“0”.Toenablefuturekeypressestobeidentified,ifthekeydataregisterisnotread, thekeydataaccumulates.There isnoFIFOregisterintheHT16K23.Key-pressorder,orwhetherakeyhasbeenpressedmore thanonce,cannotbedeterminedunlesstheallofthekeydataRAMisreadaftereachinterruptandbeforecompletionofthenextkeyscancycle.
After thekeydataregistershavebeenread, theINToutputand INTflagstatusarecleared. Ifakey ispressedandhelddown, thekeyisreportedasbeingdebounced(andanINTisissued)onlyonce.Thekeymustbedetectedasreleasedby thekeyscancircuitbeforeitisdebouncedagain.
It is strongly recommended to read the keydataregistersfromtheaddress0x20Honly.Thekeydataregistersofaddressesfrom0x20Hto0x22Hshouldbereadcontinuouslyandcompletedinoneoperation.
There isaone-to-onecorrespondencebetween thekeydataregisteraddressesandthekeydataoutputsandbetweentheindividualbitsofakeydataregisterwordandthekeydataoutputs.ThefollowingshowsthemappingfromtheRAMtothekeydataoutput:
Thekeydata registersare readonly.Thekeydataregisterformatisshownbelow:
Rev. 1.30 15 February 13, 2017
HT16K23
Key Scan Period Setting Command• HT16K23canadjustthekeyscanperiodthroughthiscommand.Thesettingisshowasbelow.• Thedefaultvalueofkeyscanperiodis2clockcycletimein20×4displaymode,1clockcycletimein16×8displaymode.
• Ingenerally,userdoesnotneedtousethiscommand,whenkeydatacanbereadcorrectly.• DuetovariousLCDcharacteristic,itwillhavedifferentRCtimeconstantinkeyscanperiod.IftheequivalentcapacitanceislargerintheLCD,itcannotbechargedordischargedfullyinkeyscanperiod.Thekeycannotbereadcorrectly.Toavoidreadkeyerror,usercanadjustthekeyscanperiodthroughthiscommand.Ifkeyscanperiodistoolonger,itmayaffecttheLCDvisualquality.
NameCommand
Option Description Def.D7 D6 D5 D4 D3 D2 D1 D0
Key scan period setting 1 1 1 1 1 P2 P1 P0 [P2:P0] To adjust key scan period F8H
The Setting of Key Scan Period
[P2:P0] 20×4 Display Mode 16×8 Display Mode000 2 clock cycle time 1 clock cycle time001 4 clock cycle time 3 clock cycle time010 6 clock cycle time 5 clock cycle time011 8 clock cycle time 7 clock cycle time100 10 clock cycle time 9 clock cycle time101 12 clock cycle time 11 clock cycle time110 14 clock cycle time 13 clock cycle time111 16 clock cycle time 15 clock cycle time
The Relationship of Display Period and Key Scan Period
VDD
V1
V2
VSS
COM0~COM3
VDD
V1
V2
VSS
SEG0/K0~SEG19/K19
Key scan period
Display period
T
V1
VDD
V2
V3
VSS
COM0~COM7
V1
VDD
V2
V3
VSS
SEG0/K0~SEG15/K15
Key scan period
Display period
T
20×4 display mode 16×8 display mode
T= Display period + Key scan period = 110 clock cycle time (fixed)
T= Display period + Key scan period = 55 clock cycle time (fixed)
Rev. 1.30 16 February 13, 2017
HT16K23
I2C Serial InterfaceThedeviceincludesaI2Cserialinterface.TheI2Cbusisusedforbidirectional,two-linecommunicationbetweendifferentICsormodules.Thetwolinesareaserialdataline(SDA)andaserialclockline(SCL).Bothlinesareconnectedtoapositivesupplyviaapull-upresistor.Whenthebusisfree,bothlinesarehigh.Theoutputstagesofdevicesconnectedtothebusmusthaveanopen-drainoropen-collectoroutputtypetoimplementtherequiredwiredandfunction.Datatransferisinitiatedonlywhenthebusisnotbusy.
Data ValidityThedataontheSDAlinemustbestableduringthehighperiodoftheclock.ThehighorlowstateofthedatalinecanonlychangewhentheclocksignalontheSCLlineisLow(seeasbelow).
SDA
SCL
Data line stable;Data valid Change of data allowed
START and STOP Conditions• AhightolowtransitionontheSDAlinewhileSCLishighdefinesaSTARTcondition.• AlowtohightransitionontheSDAlinewhileSCLishighdefinesaSTOPcondition.• STARTandSTOPconditionsarealwaysgeneratedbythemaster.ThebusisconsideredtobebusyaftertheSTARTcondition.ThebusisconsideredtobefreeagainacertaintimeaftertheSTOPcondition.
• ThebusstaysbusyifarepeatedSTART(Sr) isgeneratedinsteadofaSTOPcondition.In thisrespect, theSTART(S)andrepeatedSTART(Sr)conditionsarefunctionallyidentical.
PS
SDA
SCL
SDA
SCL
START condition STOP condition
Byte FormatEverybyteputontheSDAlinemustbe8-bitslong.Thenumberofbytesthatcanbetransmittedpertransferisunrestricted.Eachbytehastobefollowedbyanacknowledgebit.Dataistransferredwiththemostsignificantbit(MSB)first.
SorSr
PorSr
SDA
SCL 1 2 7 8 9
ACK
1 2 3-8 9
ACK
P
Sr
Acknowledge• Eachbyteofeightbitsisfollowedbyasingleacknowledgebit.Thisacknowledgebitisalowlevelwhichisplacedonthebusbythereceiver.Themastergeneratesanextraacknowledgerelatedclockpulse.
Rev. 1.30 17 February 13, 2017
HT16K23
• Aslavereceiverwhichisaddressedmustgenerateanacknowledge(ACK)afterthereceptionofeachbyte.• TheacknowledgingdevicemustpulldowntheSDAlineduringtheacknowledgeclockpulsesothatitremainsatastablelowlevelduringthehighperiodofthisclockpulse.
• Amasterreceivermustsignalanendofdatastatustotheslavebygeneratinganot-acknowledge(NACK)bitonthelastbytethathasbeenclockedoutoftheslave.Inthiscase,themasterreceivermustleavethedatalinehighduringthe9thpulsetonotacknowledge.ThemasterwillgenerateaSTOPorrepeatedSTARTcondition.
S1 2 7 8 9
CLK pulse foracknowledgement
Data OutputBy Transmiter
Data OutputBy Receiver
SCL FromMaster
acknowledge
not acknowledge
STARTcondition
Device Addressing• TheslaveaddressbyteisthefirstbytereceivedfollowingaSTARTconditionformthemasterdevice.Thefirstsevenbitsofthefirstbytemakeuptheslaveaddress.Theeighthbitdefineswhetherareadorwriteoperationistobeperformed.WhenthisR/Wbitis“1”,thenareadoperationisselected.A“0”selectsawriteoperation.
• TheHT16K23addressbitformatisshownbelow.Whenanaddressbyteissent,thedevicecomparesthefirstsevenbitsaftertheSTARTcondition.Iftheymatch,thedeviceoutputsanacknowledgeontheSDAline.
1
MSB
1 1 0 0 1 1 R/W
LSB
Write Operation• ByteWriteOperationAbytewriteoperationrequiresaSTARTcondition,aslaveaddresswithanR/Wbit,avalidRegisterAddress,DataandaSTOPcondition.Aftereachofthethreebyteshavebeentransmitted,thedevicerespondswithanACK.
1 1 1 0 0 1 1 0S
ACK
P
SLAVE ADDRESS
WRITE
COMMAND CODE
ACK
Command Byte Received
1 1 1 0 0 1 1 0S
ACK
P
SLAVE ADDRESS
WRITE
REGISTER ADDRESS(An) DATA(n)
ACK ACK
Single Data Byte ReceivedNote:Ifthebytefollowingslaveaddressisacommandcode,thebytefollowingthecommandcodewillbe
ignored.
Rev. 1.30 18 February 13, 2017
HT16K23
• PageWriteOperationASTARTconditionandaslaveaddresswithaR/WbitplacedonthebusindicatestotheaddresseddevicethataRegisterAddresswillfollowandistobewrittentotheaddresspointer.Thedatatobewrittentothememoryisnextandtheinternaladdresspointerwillbeincrementedtothenextaddresslocationonthereceptionofanacknowledgeclock.Afterreachingthememorylocation0x8Ahinthe20×4displaymodeor0X8Fhinthe16×8displaymode,thepointerwillberesetto0x80h.
1 1 1 0 0 1 1 0S
ACK
SLAVE ADDRESS
WRITE
REGISTER ADDRESS(An) DATA(n)
ACK ACK ACK
DATA(n+1)
ACKACK
DATA(n+x)
P
N Data Bytes Received
Read Operation• Inthismode,themasterreadstheHT16K23dataaftersettingtheslaveaddress.FollowingaR/Wbit(=“0”)andanacknowledgebit,theregisteraddress(An)iswrittentotheaddresspointer.NextaSTARTconditionandaslaveaddressarerepeatedfollowedbyaR/Wbit(=“1”).Thedatawhichwasaddressedisthentransmitted.Theaddresspointerisonlyincrementedonreceptionofanacknowledgeclock.TheHT16K23willplacethedataataddressAn+1onthebus.Themasterreadsandacknowledgesthenewbyteandtheaddresspointerisincrementedto“An+2”.Iftheregisteraddress(An)is0X00H~0X0FH,afterreachingthememorylocation0X0FH,thepointerwillreset to0X00H.If theregisteraddress(An)is0X20H~0X22H,afterreachingthememorylocation0X22H,thepointerwillresetto0X20H.
• ThiscycleofreadingconsecutiveaddresseswillcontinueuntilthemastersendsaSTOPcondition.
1 1 1 0 0 1 1 1S
SLAVE ADDRESS
READ
DATA(n)
ACK ACK ACK
DATA(n+1)
ACK
DATA(n+x)
P
1 1 1 0 0 1 1 0S
ACK
SLAVE ADDRESS
WRITE
REGISTER ADDRESS(An)
P
ACK
NACK
Rev. 1.30 19 February 13, 2017
HT16K23
Command SummaryName
Command / AddressOption Description Def.
D7 D6 D5 D4 D3 D2 D1 D0
Display data Address pointer 0 0 0 0 A3 A2 A1 A0
[A3:A0](R/W)
Four bits of immediate data, bits A0 to A4, are transferred to the data pointer to define display RAM addresses.
00H
Key data Address pointer 0 0 1 0 0 0 K1 K0
{K0~K1}(R)
It is strongly recommended that the key data registers with addresses from 0x20H to 0x22H should be read continuously and in one operation.Therefore the key data RAM addresses should be started form 0x20H only.
20H
INT flag Address pointer 0 0 1 1 0 0 0 0 (R)
INT flag address for reading INT flag status. 30H
System setcommand 1 0 0 0 0 0 D S
SStandby mode selecting
● {0}: standby mode ● {1}: normal mode
80H
DLCD display on/off
● {0}: LCD display off ● {1}: LCD display on
Mode setcommand 1 0 1 0 0 ACT
INT/ROW M
MLCD display mode selecting
● {0}: 20×4 display mode ● {1}:16×8 display mode
A0HINT/ROW
Segment or INT pin selecting ● {0}: Segment output SEG19/COM4/K19/INT is segment output in 20×4 display mode.SEG15/K15/INT is segment output in 16×8 display mode. ● {1}: INT outputSEG19/COM4/K19/INT is INT output in 20×4 display mode.SEG15/K15/INT is INT output in 16×8 display mode.
ACTINT output level selection,
● {0}: INT output is active-low. ● {1}: INT output is active-high.
Key scan period setting 1 1 1 1 1 P2 P1 P0 [P2:P0] To adjust key scan period F8H
Note:Iftheprogrammedcommanddataisnotdefined,thefunctionwillnotbeaffected.
Rev. 1.30 20 February 13, 2017
HT16K23
• Key Data Read
no
yes
Start
Int flag bit =1 ?
Read Key data
Next processing
Port Configuration Register setINT / ROW bit=1?
yes no
Clear int flag
no
yes
Int pin bit =1 ?
Read Key data
Next processing
INT pin is set to low level
no
yes
Int pin bit =0 ?
Read Key data
Next processing
INT pin is set to high level
“act” bit is set to “0”=?
yes
no
Operation Flow ChartTheaccessprocedureisillustratedusingthefollowingflowcharts.
• Initialisation
Power On
Mode set
System set
Display ON
Power On
• Display Data Rewrite – Address Setting
Start
Display data RAM write
Address setting
Display data
Next processing
Rev. 1.30 21 February 13, 2017
HT16K23
Power Supply Sequence• If thepoweris individuallysuppliedontheLCDandVDDpins, it isstronglyrecommendedtofollowtheHoltekpowersupplysequencerequirement.
• Ifthepowersupplysequencerequirementisnotfollowed,itmayresultinmalfunction.
HoltekPowerSupplySequenceRequirement:
1.Power-onsequence:TurnonthelogicpowersupplyVDDfirstandthenturnontheLCDdriverpowersupplyVLCD.
2.Power-offsequence:TurnofftheLCDdriverpowersupplyVLCD.FirstandthenturnoffthelogicpowersupplyVDD.
3.TheHoltekPowerSupplySequenceRequirementmustbefollowednomatterwhethertheVLCDvoltageishigherthantheVDDvoltage.
• WhentheVLCDvoltageissmallerthanorisequaltoVDDvoltageapplication
Voltage
Time
VLCD
VDD
1µs
VDD
VLCD
1µs
Rev. 1.30 22 February 13, 2017
HT16K23
Application Circuit• 20×4 Display Mode Without INT
LCD panel
SCL
SDA
VDD
VSS
MCU
VDD
VSS
HT16K23
VSS
R
0.1μF
SEG11/K11SEG12/K12SEG13/K13SEG14/K14
SEG15/K15/INTSEG16/COM7/K16SEG17/COM6/K17SEG18/COM5/K18
COM3COM2COM1COM0
VDDSEG4/K4SEG5/K5SEG6/K6SEG7/K7SEG8/K8SEG9/K9
SEG10/K10
R
SEG3/K3SEG2/K2SEG1/K1SEG0/K0
SEG19/COM4/K19/INT
VDD
R1x20
=
4.7KΩ4.7KΩ
• 19×4 Display Mode with INT
LCD panel
SCL
SDA
VDD
VSS
MCU
VDD
VSS
HT16K23
VSS
R
0.1μF
SEG11/K11SEG12/K12SEG13/K13SEG14/K14
SEG15/K15/INTSEG16/COM7/K16SEG17/COM6/K17SEG18/COM5/K18
COM3COM2COM1COM0
VDDSEG4/K4SEG5/K5SEG6/K6SEG7/K7SEG8/K8SEG9/K9
SEG10/K10
R
SEG3/K3SEG2/K2SEG1/K1SEG0/K0
SEG19/COM4/K19/INT
=
VDD
R1x19
4.7KΩ4.7KΩ
Note:R1=180KΩ~220KΩ,adjustR1tofittheLCDvisualquality.
Rev. 1.30 23 February 13, 2017
HT16K23
• 16×8 Display Mode Without INT
LCD panel
SCL
SDA
VDD
VSS
MCU
VDD
VSS
VSS
R
0.1μF
SEG11/K11SEG12/K12SEG13/K13SEG14/K14
SEG15/K15/INT
COM3COM2COM1COM0
VDDSEG4/K4SEG5/K5SEG6/K6SEG7/K7SEG8/K8SEG9/K9
SEG10/K10
R
SEG3/K3SEG2/K2SEG1/K1SEG0/K0
SEG16/COM7/K16SEG17/COM6/K17SEG18/COM5/K18
SEG19/COM4/K19/INT
VDD
R1x16
4.7KΩ4.7KΩ
• 15×8 Display Mode With INT
LCD panel
SCL
SDA
VDD
VSS
MCU
VDD
VSS
VSS
R
0.1μF
SEG11/K11SEG12/K12SEG13/K13SEG14/K14
SEG15/K15/INT
COM3COM2COM1COM0
VDDSEG4/K4SEG5/K5SEG6/K6SEG7/K7SEG8/K8SEG9/K9
SEG10/K10
R
SEG3/K3SEG2/K2SEG1/K1SEG0/K0
SEG16/COM7/K16SEG17/COM6/K17SEG18/COM5/K18
SEG19/COM4/K19/INT
VDD
R1x15
4.7KΩ4.7KΩ
Note:R1=180KΩ~220KΩ,adjustR1tofittheLCDvisualquality.
Rev. 1.30 24 February 13, 2017
HT16K23
Package Information
Notethat thepackageinformationprovidedhereisforconsultationpurposesonly.Asthis informationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.
Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.
• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)
• TheOperationInstructionofPackingMaterials
• Cartoninformation
http://www.holtek.com/en/http://www.holtek.com/en/package_carton_informationhttp://www.holtek.com/en/package_carton_information
Rev. 1.30 25 February 13, 2017
HT16K23
28-pin SOP (300mil) Outline Dimensions
� �
�
� �
� �
� �
�
�
�
� � ��
��
SymbolDimensions in inch
Min. Nom. Max.A — 0.406 BSC —B — 0.295 BSC —C 0.012 — 0.020 C’ — 0.705 BSC —D — — 0.104 E — 0.050 BSC —F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° ― 8°
SymbolDimensions in mm
Min. Nom. Max.A — 10.30 BSC —B — 7.5 BSC —C 0.31 — 0.51 C’ — 17.9 BSC —D — — 2.65 E — 1.27 BSC —F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° ― 8°
Rev. 1.30 26 February 13, 2017
HT16K23
Copyright© 2017 by HOLTEK SEMICONDUCTOR INC.The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
FeatureApplicationsGeneral DescriptionBlock DiagramPin AssignmentPad CoordinatesPad AssignmentPin DescriptionApproximate Internal ConnectionsAbsolute Maximum RatingsD.C. CharacteristicsA.C. CharacteristicsIC-Bus A.C. CharacteristicsTiming DiagramsFunctional DescriptionPower-on ResetStandby ModeWake-upSystem Set CommandMode Set CommandSystem OscillatorLCD Bias GeneratorSegment Driver OutputsCommon Driver OutputsDisplay Memory – RAM StructureLCD Drive Mode WaveformsKeyscanKeyscan and INT TimingKey Matrix ConfigurationKey Data RegisterKey Scan Period Setting CommandThe Setting of Key Scan PeriodThe Relationship of Display Period and Key Scan Period
I2C Serial InterfaceData ValiditySTART and STOP ConditionsByte FormatAcknowledgeDevice AddressingWrite OperationRead Operation
Command SummaryOperation Flow ChartPower Supply SequenceApplication CircuitPackage Information28-pin SOP (300mil) Outline Dimensions