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Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M3 Core HT32F12364 User Manual Revision: V1.00 Date: July 29, 2020
HT32F12364 User Manual - Holtek
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HT32F12364 User Manual
Rev. 1.00 2 of 575 July 29, 2020
32-Bit Arm® Cortex®-M3 MCU HT32F12364
Table of C ontents
Overview
..............................................................................................................................
25 Features
...............................................................................................................................
26 Device Information
...............................................................................................................
30 Block Diagram
.....................................................................................................................
31
2 Document Conventions
.......................................................................................
32
3 System Architecture
.............................................................................................
33 Arm® Cortex®-M3 Processor
................................................................................................
33 Bus Architecture
...................................................................................................................
34 Memory Organization
..........................................................................................................
35
Memory Map
...................................................................................................................................
36 Embedded Flash Memory
...............................................................................................................
39 Embedded SRAM Memory
.............................................................................................................
39 AHB Peripherals
.............................................................................................................................
39 APB Peripherals
.............................................................................................................................
39
4 Flash Memory Controller (FMC)
..........................................................................
40 Introduction
..........................................................................................................................
40 Features
...............................................................................................................................
40 Functional Descriptions
.......................................................................................................
41
Flash Memory Map
.........................................................................................................................
41 Flash Memory Architecture
.............................................................................................................
42 Wait State Setting
...........................................................................................................................
42 Page Erase
.....................................................................................................................................
44 Mass Erase
.....................................................................................................................................
45 Word Programming
.........................................................................................................................
46 Option Byte Description
..................................................................................................................
47 Page Erase/Program Protection
.....................................................................................................
48 Security Protection
..........................................................................................................................
49
Register Map
.......................................................................................................................
50 Register Descriptions
...........................................................................................................
51
Flash Target Address Register – TADR
..........................................................................................
51 Flash Write Data Register – WRDR
...............................................................................................
52 Flash Operation Command Register – OCMR
...............................................................................
53 Flash Operation Control Register – OPCR
.....................................................................................
54 Flash Operation Interrupt Enable Register – OIER
........................................................................
55 Flash Operation Interrupt and Status Register – OISR
..................................................................
56 Flash Page Erase/Program Protection Status Register – PPSR
.................................................... 58 Flash
Security Protection Status Register – CPSR
........................................................................
59 Flash Vector Mapping Control Register – VMCR
...........................................................................
60
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Table of C ontents
Flash Manufacturer and Device ID Register – MDID
......................................................................
61 Flash Page Number Status Register – PNSR
................................................................................
62 Flash Page Size Status Register – PSSR
......................................................................................
63 Device ID Register – DID
................................................................................................................
63 Flash Cache and Pre-fetch Control Register – CFCR
....................................................................
64 SRAM Booting Vector Register n – SBVTn (n = 0 ~ 3)
...................................................................
65 Custom ID Register n – CIDRn (n = 0 ~ 3)
.....................................................................................
66
5 Power Control Unit (PWRCU)
..............................................................................
67 Introduction
..........................................................................................................................
67 Features
...............................................................................................................................
68 Functional Descriptions
.......................................................................................................
68
VDD Power Domain
..........................................................................................................................
68 1.5 V Power Domain
.......................................................................................................................
70 Operation Modes
............................................................................................................................
70
Register Map
.......................................................................................................................
73 Register Descriptions
...........................................................................................................
73
Power Control Status Register – PWRSR
......................................................................................
73 Power Control Register – PWRCR
.................................................................................................
74 VDD Power Domain Test Register – PWRTEST
..............................................................................
76 Low Voltage / Brown-Out Detect Control and Status Register –
LVDCSR ..................................... 77 Power Control LDO
Status Register – PWRLDOSR
......................................................................
79
6 Clock Control Unit (CKCU)
..................................................................................
80 Introduction
..........................................................................................................................
80 Features
...............................................................................................................................
82 Function Descriptions
..........................................................................................................
82
High Speed External Crystal Oscillator – HSE
...............................................................................
82 High Speed Internal RC Oscillator – HSI
........................................................................................
83 Auto Trimming of High Speed Internal RC Oscillator – HSI
............................................................ 83
Phase Locked Loop – PLL
..............................................................................................................
85 USB Phase Locked Loop – USB PLL
.............................................................................................
87 Low Speed External Crystal Oscillator – LSE
.................................................................................
89 Low Speed Internal RC Oscillator – LSI
.........................................................................................
89 Clock Ready Flag
...........................................................................................................................
89 System Clock (CK_SYS) Selection
................................................................................................
90 HSE Clock Monitor
.........................................................................................................................
91 Clock Output Capability
..................................................................................................................
91
Register Map
.......................................................................................................................
92 Register Descriptions
...........................................................................................................
93
Global Clock Configuration Register – GCFGR
..............................................................................
93 Global Clock Control Register – GCCR
..........................................................................................
94 Global Clock Status Register – GCSR
...........................................................................................
96 Global Clock Interrupt Register – GCIR
..........................................................................................
97
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PLL Configuration Register – PLLCFGR
........................................................................................
99 PLL Control Register – PLLCR
.....................................................................................................
100 AHB Configuration Register – AHBCFGR
....................................................................................
101 AHB Clock Control Register – AHBCCR
......................................................................................
102 APB Configuration Register – APBCFGR
.....................................................................................
104 APB Clock Control Register 0 – APBCCR0
..................................................................................
105 APB Clock Control Register 1 – APBCCR1
..................................................................................
106 Clock Source Status Register – CKST
.........................................................................................
107 APB Peripheral Clock Selection Register 0 – APBPCSR0
........................................................... 108 APB
Peripheral Clock Selection Register 1 – APBPCSR1
............................................................110 HSI
Control Register – HSICR
.......................................................................................................111
HSI Auto Trimming Counter Register – HSIATCR
.........................................................................113
APB Peripheral Clock Selection Register 2 – APBPCSR2
............................................................114 Low
Power Control Register – LPCR
............................................................................................115
MCU Debug Control Register – MCUDBGCR
...............................................................................116
7 Reset Control Unit (RSTCU)
..............................................................................
118 Introduction
........................................................................................................................
118 Functional Descriptions
.....................................................................................................
119
Power On Reset
............................................................................................................................119
System Reset
................................................................................................................................119
AHB and APB Unit Reset
...............................................................................................................119
Register Map
.....................................................................................................................
120 Register Descriptions
.........................................................................................................
120
Global Reset Status Register – GRSR
.........................................................................................
120 AHB Peripheral Reset Register – AHBPRSTR
.............................................................................
121 APB Peripheral Reset Register 0 – APBPRSTR0
........................................................................
122 APB Peripheral Reset Register 1 – APBPRSTR1
........................................................................
124
8 General Purpose I/O (GPIO)
...............................................................................
126 Introduction
........................................................................................................................
126 Features
.............................................................................................................................
127 Functional Descriptions
.....................................................................................................
127
Default GPIO Pin Configuration
....................................................................................................
127 General Purpose I/O – GPIO
........................................................................................................
127 GPIO Locking Mechanism
............................................................................................................
129
Register Map
.....................................................................................................................
129 Register Descriptions
.........................................................................................................
131
Port A Data Direction Control Register – PADIRCR
.....................................................................
131 Port A Input Function Enable Control Register – PAINER
............................................................ 132
Port A Pull-Up Selection Register – PAPUR
.................................................................................
133 Port A Pull-Down Selection Register – PAPDR
............................................................................
134 Port A Open-Drain Selection Register – PAODR
..........................................................................
135 Port A Drive Current Selection Register – PADRVR
.....................................................................
136
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Table of C ontents
Port A Lock Register – PALOCKR
................................................................................................
137 Port A Data Input Register – PADINR
...........................................................................................
138 Port A Output Data Register – PADOUTR
....................................................................................
138 Port A Output Set/Reset Control Register – PASRR
....................................................................
139 Port A Output Reset Register – PARR
..........................................................................................
140 Port B Data Direction Control Register – PBDIRCR
.....................................................................
140 Port B Input Function Enable Control Register – PBINER
........................................................... 141
Port B Pull-Up Selection Register – PBPUR
................................................................................
142 Port B Pull-Down Selection Register – PBPDR
............................................................................
143 Port B Open-Drain Selection Register – PBODR
.........................................................................
144 Port B Drive Current Selection Register – PBDRVR
....................................................................
145 Port B Lock Register – PBLOCKR
................................................................................................
146 Port B Data Input Register – PBDINR
..........................................................................................
147 Port B Output Data Register – PBDOUTR
...................................................................................
147 Port B Output Set/Reset Control Register – PBSRR
....................................................................
148 Port B Output Reset Register – PBRR
.........................................................................................
149 Port C Data Direction Control Register – PCDIRCR
....................................................................
149 Port C Input Function Enable Control Register – PCINER
........................................................... 150
Port C Pull-Up Selection Register – PCPUR
................................................................................
151 Port C Pull-Down Selection Register – PCPDR
...........................................................................
152 Port C Open-Drain Selection Register – PCODR
.........................................................................
153 Port C Drive Current Selection Register – PCDRVR
....................................................................
154 Port C Lock Register – PCLOCKR
...............................................................................................
155 Port C Data Input Register – PCDINR
..........................................................................................
156 Port C Output Data Register – PCDOUTR
...................................................................................
156 Port C Output Set/Reset Control Register – PCSRR
...................................................................
157 Port C Output Reset Register – PCRR
.........................................................................................
158 Port D Data Direction Control Register – PDDIRCR
....................................................................
158 Port D Input Function Enable Control Register – PDINER
........................................................... 159
Port D Pull-Up Selection Register – PDPUR
................................................................................
160 Port D Pull-Down Selection Register – PDPDR
...........................................................................
161 Port D Open-Drain Selection Register – PDODR
.........................................................................
162 Port D Drive Current Selection Register – PDDRVR
....................................................................
163 Port D Lock Register – PDLOCKR
...............................................................................................
164 Port D Data Input Register – PDDINR
..........................................................................................
165 Port D Output Data Register – PDDOUTR
...................................................................................
165 Port D Output Set/Reset Control Register – PDSRR
...................................................................
166 Port D Output Reset Register – PDRR
.........................................................................................
167 Port F Data Direction Control Register – PFDIRCR
.....................................................................
167 Port F Input Function Enable Control Register – PFINER
............................................................ 168
Port F Pull-Up Selection Register – PFPUR
.................................................................................
169 Port F Pull-Down Selection Register – PFPDR
............................................................................
170 Port F Open-Drain Selection Register – PFODR
..........................................................................
171 Port F Drive Current Selection Register – PFDRVR
.....................................................................
172 Port F Lock Register – PFLOCKR
................................................................................................
173
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Port F Data Input Register – PFDINR
...........................................................................................
174 Port F Output Data Register – PFDOUTR
....................................................................................
174 Port F Output Set/Reset Control Register – PFSRR
....................................................................
175 Port F Output Reset Register – PFRR
..........................................................................................
176
9 Alternate Function Input/Output Control Unit (AFIO)
...................................... 177 Introduction
........................................................................................................................
177 Features
.............................................................................................................................
178 Functional Descriptions
.....................................................................................................
178
External Interrupt Pin Selection
....................................................................................................
178 Alternate Function
.........................................................................................................................
179 Lock Mechanism
..........................................................................................................................
179
Register Map
.....................................................................................................................
179 Register Descriptions
.........................................................................................................
180
EXTI Source Selection Register 0 – ESSR0
................................................................................
180 EXTI Source Selection Register 1 – ESSR1
................................................................................
181 GPIO Port x Configuration Low Register – GPxCFGLR (x = A, B, C,
D, F) ................................. 182 GPIO Port x
Configuration High Register – GPxCFGHR (x = A, B, C, D, F)
................................ 183
10 Nested Vectored Interrupt Controller (NVIC)
.................................................. 184 Introduction
........................................................................................................................
184 Features
.............................................................................................................................
186 Function Descriptions
........................................................................................................
187
SysTick Calibration
.......................................................................................................................
187
Register Map
.....................................................................................................................
187
11 External Interrupt/Event Controller (EXTI)
...................................................... 189
Introduction
........................................................................................................................
189 Features
.............................................................................................................................
189 Functional Descriptions
.....................................................................................................
190
Wakeup Event
Management.........................................................................................................
190 External Interrupt/Event Line Mapping
.........................................................................................
191 Interrupt and Debounce
................................................................................................................
191
Register Map
.....................................................................................................................
192 Register Descriptions
.........................................................................................................
193
EXTI Interrupt n Configuration Register – EXTICFGRn (n = 0 ~ 15)
............................................ 193 EXTI Interrupt
Control Register – EXTICR
...................................................................................
194 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR
................................................................
194 EXTI Interrupt Edge Status Register – EXTIEDGESR
.................................................................
195 EXTI Interrupt Software Set Command Register – EXTISSCR
.................................................... 195 EXTI
Interrupt Wakeup Control Register – EXTIWAKUPCR
........................................................ 196 EXTI
Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR
................................................... 196 EXTI
Interrupt Wakeup Flag Register – EXTIWAKUPFLG
...........................................................
197
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Table of C ontents
12 Analog to Digital Converter (ADC)
..................................................................
198 Introduction
........................................................................................................................
198 Features
.............................................................................................................................
199 Functional Descriptions
.....................................................................................................
200
ADC Clock Setup
..........................................................................................................................
200 Channel Selection
.........................................................................................................................
200 Conversion Mode
..........................................................................................................................
200 Start Conversion on External Event
..............................................................................................
203 Sampling Time Setting
..................................................................................................................
204 Data Format
..................................................................................................................................
204 Analog
Watchdog..........................................................................................................................
204 Interrupts
.......................................................................................................................................
205 PDMA Request
............................................................................................................................
205 Voltage Reference Generator
.......................................................................................................
205 VDDA Voltage Monitor
.....................................................................................................................
206
Register Map
.....................................................................................................................
206 Register Descriptions
.........................................................................................................
207
ADC Conversion Control Register – ADCCR
...............................................................................
207 ADC Conversion List Register 0 – ADCLST0
...............................................................................
209 ADC Conversion List Register 1 – ADCLST1
...............................................................................
210 ADC Input Sampling Time Register – ADCSTR
............................................................................211
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7
............................................................... 212
ADC Trigger Control Register – ADCTCR
....................................................................................
213 ADC Trigger Source Register – ADCTSR
.....................................................................................
214 ADC Watchdog Control Register – ADCWCR
..............................................................................
215 ADC Watchdog Threshold Register – ADCTR
..............................................................................
217 ADC Interrupt Enable Register – ADCIER
....................................................................................
218 ADC Interrupt Raw Status Register – ADCIRAW
.........................................................................
219 ADC Interrupt Status Register – ADCISR
.....................................................................................
220 ADC Interrupt Clear Register – ADCICLR
....................................................................................
221 ADC DMA Request Register – ADCDMAR
...................................................................................
222 Voltage Reference Control Register – VREFCR
..........................................................................
223 Voltage Reference Value Register – VREFVALR
.........................................................................
224
13 General-Purpose Timer (GPTM)
......................................................................
225 Introduction
........................................................................................................................
225 Features
.............................................................................................................................
226 Functional Descriptions
.....................................................................................................
226
Counter Mode
...............................................................................................................................
226 Clock Controller
............................................................................................................................
228 Trigger Controller
..........................................................................................................................
229 Slave Controller
............................................................................................................................
231 Master Controller
..........................................................................................................................
233 Channel Controller
........................................................................................................................
233
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Input Stage
...................................................................................................................................
235 Digital Filter
...................................................................................................................................
237 Quadrature Decoder
.....................................................................................................................
237 Output Stage
.................................................................................................................................
240 Clearing the CHxOREF when ETIF is high
...................................................................................
243 Update Management
....................................................................................................................
244 Single Pulse Mode
........................................................................................................................
245 Asymmetric PWM Mode
...............................................................................................................
247 Time Interconnection
....................................................................................................................
247 Trigger ADC
Start..........................................................................................................................
250 PDMA Request
.............................................................................................................................
250
Register Map
.....................................................................................................................
251 Register Descriptions
.........................................................................................................
252
Timer Counter Configuration Register – CNTCFR
.......................................................................
252 Timer Mode Configuration Register – MDCFR
.............................................................................
253 Timer Trigger Configuration Register – TRCFR
............................................................................
256 Timer Counter Register – CTR
.....................................................................................................
258 Channel 0 Input Configuration Register – CH0ICFR
....................................................................
259 Channel 1 Input Configuration Register – CH1ICFR
....................................................................
260 Channel 2 Input Configuration Register – CH2ICFR
....................................................................
262 Channel 3 Input Configuration Register – CH3ICFR
....................................................................
263 Channel 0 Output Configuration Register – CH0OCFR
............................................................... 265
Channel 1 Output Configuration Register – CH1OCFR
............................................................... 267
Channel 2 Output Configuration Register – CH2OCFR
............................................................... 269
Channel 3 Output Configuration Register – CH3OCFR
............................................................... 271
Channel Control Register – CHCTR
.............................................................................................
273 Channel Polarity Configuration Register – CHPOLR
....................................................................
274 Timer PDMA/Interrupt Control Register – DICTR
.........................................................................
275 Timer Event Generator Register – EVGR
.....................................................................................
276 Timer Interrupt Status Register – INTSR
......................................................................................
278 Timer Counter Register –
CNTR...................................................................................................
280 Timer Prescaler Register – PSCR
................................................................................................
281 Timer Counter-Reload Register – CRR
........................................................................................
281 Channel 0 Capture/Compare Register – CH0CCR
......................................................................
282 Channel 1 Capture/Compare Register – CH1CCR
......................................................................
283 Channel 2 Capture/Compare Register – CH2CCR
......................................................................
284 Channel 3 Capture/Compare Register – CH3CCR
......................................................................
285 Channel 0 Asymmetric Compare Register – CH0ACR
.................................................................
286 Channel 1 Asymmetric Compare Register – CH1ACR
.................................................................
286 Channel 2 Asymmetric Compare Register – CH2ACR
.................................................................
287 Channel 3 Asymmetric Compare Register – CH3ACR
.................................................................
287
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Table of C ontents
14 Pulse-Width-Modulation Timer (PWM)
............................................................ 288
Introduction
........................................................................................................................
288 Features
.............................................................................................................................
289 Functional Descriptions
.....................................................................................................
289
Counter Mode
...............................................................................................................................
289 Clock Controller
............................................................................................................................
292 Trigger Controller
..........................................................................................................................
293 Slave Controller
............................................................................................................................
294 Master Controller
..........................................................................................................................
296 Channel Controller
........................................................................................................................
297 Output Stage
.................................................................................................................................
297 Update Management
....................................................................................................................
301 Single Pulse Mode
........................................................................................................................
301 Asymmetric PWM Mode
...............................................................................................................
304 Timer Interconnection
...................................................................................................................
304 Trigger Peripherals Start
...............................................................................................................
307 PDMA Request
.............................................................................................................................
307
Register Map
.....................................................................................................................
308 Register Descriptions
.........................................................................................................
309
Timer Counter Configuration Register – CNTCFR
.......................................................................
309 Timer Mode Configuration Register – MDCFR
.............................................................................
310 Timer Trigger Configuration Register – TRCFR
............................................................................
313 Timer Counter Register – CTR
.....................................................................................................
314 Channel 0 Output Configuration Register – CH0OCFR
............................................................... 315
Channel 1 Output Configuration Register – CH1OCFR
............................................................... 317
Channel 2 Output Configuration Register – CH2OCFR
............................................................... 319
Channel 3 Output Configuration Register – CH3OCFR
............................................................... 321
Channel Control Register – CHCTR
.............................................................................................
323 Channel Polarity Configuration Register – CHPOLR
....................................................................
324 Timer PDMA/Interrupt Control Register – DICTR
.........................................................................
325 Timer Event Generator Register – EVGR
.....................................................................................
326 Timer Interrupt Status Register – INTSR
......................................................................................
327 Timer Counter Register –
CNTR...................................................................................................
329 Timer Prescaler Register – PSCR
................................................................................................
329 Timer Counter-Reload Register – CRR
........................................................................................
330 Channel 0 Compare Register – CH0CR
.......................................................................................
330 Channel 1 Compare Register – CH1CR
.......................................................................................
331 Channel 2 Compare Register – CH2CR
.......................................................................................
331 Channel 3 Compare Register – CH3CR
.......................................................................................
332 Channel 0 Asymmetric Compare Register – CH0ACR
.................................................................
332 Channel 1 Asymmetric Compare Register – CH1ACR
.................................................................
333 Channel 2 Asymmetric Compare Register – CH2ACR
.................................................................
333 Channel 3 Asymmetric Compare Register – CH3ACR
.................................................................
334
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15 Single-Channel Timer (SCTM)
.........................................................................
335 Introduction
........................................................................................................................
335 Features
.............................................................................................................................
336 Functional Descriptions
.....................................................................................................
336
Counter Mode
...............................................................................................................................
336 Clock Controller
............................................................................................................................
337 Trigger Controller
..........................................................................................................................
338 Slave Controller
............................................................................................................................
339 Channel Controller
........................................................................................................................
341 Input Stage
...................................................................................................................................
343 Output Stage
.................................................................................................................................
344 Update Management
....................................................................................................................
346
Register Map
.....................................................................................................................
347 Register Descriptions
.........................................................................................................
348
Timer Counter Configuration Register – CNTCFR
.......................................................................
348 Timer Mode Configuration Register – MDCFR
.............................................................................
349 Timer Trigger Configuration Register – TRCFR
............................................................................
350 Timer Counter Register – CTR
.....................................................................................................
351 Channel Input Configuration Register – CHICFR
.........................................................................
352 Channel Output Configuration Register – CHOCFR
....................................................................
354 Channel Control Register – CHCTR
.............................................................................................
355 Channel Polarity Configuration Register – CHPOLR
....................................................................
356 Timer Interrupt Control Register – DICTR
....................................................................................
357 Timer Event Generator Register – EVGR
.....................................................................................
358 Timer Interrupt Status Register – INTSR
......................................................................................
359 Timer Counter Register –
CNTR...................................................................................................
360 Timer Prescaler Register – PSCR
................................................................................................
360 Timer Counter-Reload Register – CRR
........................................................................................
361 Channel Capture/Compare Register – CHCCR
...........................................................................
362
16 Basic Function Timer (BFTM)
..........................................................................
363 Introduction
........................................................................................................................
363 Features
.............................................................................................................................
363 Functional Description
.......................................................................................................
364
Repetitive Mode
............................................................................................................................
364 One Shot Mode
.............................................................................................................................
365 Trigger ADC
Start..........................................................................................................................
365
Register Map
.....................................................................................................................
366 Register Descriptions
.........................................................................................................
366
BFTM Control Register – BFTMCR
..............................................................................................
366 BFTM Status Register – BFTMSR
................................................................................................
367 BFTM Counter Register – BFTMCNTR
........................................................................................
368 BFTM Compare Value Register – BFTMCMPR
...........................................................................
368
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Table of C ontents
17 Real Time Clock (RTC)
.....................................................................................
369 Introduction
........................................................................................................................
369 Features
.............................................................................................................................
369 Functional Descriptions
.....................................................................................................
370
RTC Related Register Reset
........................................................................................................
370 Reading RTC Register
..................................................................................................................
370 Low Speed Clock Configuration
...................................................................................................
370 RTC Counter Operation
................................................................................................................
371 Interrupt and Wakeup Control
.......................................................................................................
371 RTCOUT Output Pin
Configuration...............................................................................................
371
Register Map
.....................................................................................................................
373 Register Descriptions
.........................................................................................................
373
RTC Counter Register – RTCCNT
................................................................................................
373 RTC Compare Register – RTCCMP
.............................................................................................
374 RTC Control Register – RTCCR
...................................................................................................
375 RTC Status Register –
RTCSR.....................................................................................................
377 RTC Interrupt and Wakeup Enable Register – RTCIWEN
............................................................
378
18 Watchdog Timer (WDT)
....................................................................................
379 Introduction
........................................................................................................................
379 Features
.............................................................................................................................
380 Functional Description
.......................................................................................................
380 Register Map
.....................................................................................................................
382 Register Descriptions
.........................................................................................................
382
Watchdog Timer Control Register – WDTCR
...............................................................................
382 Watchdog Timer Mode Register 0 –
WDTMR0.............................................................................
383 Watchdog Timer Mode Register 1 –
WDTMR1.............................................................................
384 Watchdog Timer Status Register – WDTSR
.................................................................................
385 Watchdog Timer Protection Register – WDTPR
...........................................................................
386 Watchdog Timer Clock Selection Register – WDTCSR
................................................................
387
19 Inter-Integrated Circuit (I2C)
.............................................................................
388 Introduction
........................................................................................................................
388 Features
.............................................................................................................................
389 Functional Descriptions
.....................................................................................................
389
Two-Wire Serial Interface
.............................................................................................................
389 START and STOP Conditions
.......................................................................................................
389 Data Validity
..................................................................................................................................
390 Addressing Format
.......................................................................................................................
390 Data Transfer and Acknowledge
...................................................................................................
392 Clock Synchronization
..................................................................................................................
392 Arbitration
.....................................................................................................................................
393 General Call Addressing
...............................................................................................................
393
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Bus Error
.......................................................................................................................................
393 Address Mask Enable
...................................................................................................................
394 Address Snoop
.............................................................................................................................
394 Operation Mode
............................................................................................................................
394 Conditions of Holding SCL Line
....................................................................................................
399 I2C Timeout Function
....................................................................................................................
399 PDMA Interface
.............................................................................................................................
400
Register Map
.....................................................................................................................
400 Register Descriptions
.........................................................................................................
401
I2C Control Register – I2CCR
.......................................................................................................
401 I2C Interrupt Enable Register – I2CIER
........................................................................................
403 I2C Address Register – I2CADDR
.................................................................................................
404 I2C Status Register – I2CSR
.........................................................................................................
405 I2C SCL High Period Generation Register – I2CSHPGR
.............................................................. 408
I2C SCL Low Period Generation Register – I2CSLPGR
............................................................... 409
I2C Data Register – I2CDR
...........................................................................................................
410 I2C Target Register – I2CTAR
........................................................................................................411
I2C Address Mask Register – I2CADDMR
....................................................................................
412 I2C Address Snoop Register – I2CADDSR
...................................................................................
413 I2C Timeout Register –
I2CTOUT..................................................................................................
414
20 Serial Peripheral Interface (SPI)
......................................................................
415 Introduction
........................................................................................................................
415 Features
.............................................................................................................................
416 Function Descriptions
........................................................................................................
416
Master Mode
.................................................................................................................................
416 Slave Mode
...................................................................................................................................
416 SPI Serial Frame Format
..............................................................................................................
417 Status Flags
..................................................................................................................................
421 PDMA Interface
.............................................................................................................................
424
Register Map
.....................................................................................................................
424 Register Descriptions
.........................................................................................................
425
SPI Control Register 0 – SPICR0
.................................................................................................
425 SPI Control Register 1 – SPICR1
.................................................................................................
427 SPI Interrupt Enable Register – SPIIER
.......................................................................................
428 SPI Clock Prescaler Register – SPICPR
......................................................................................
430 SPI Data Register – SPIDR
..........................................................................................................
431 SPI Status Register – SPISR
........................................................................................................
432 SPI FIFO Control Register – SPIFCR
...........................................................................................
433 SPI FIFO Status Register – SPIFSR
............................................................................................
434 SPI FIFO Time Out Counter Register – SPIFTOCR
.....................................................................
435
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Table of C ontents
Table of C ontents
21 Universal Synchronous Asynchronous Receiver Transmitter (USART)
..... 436 Introduction
........................................................................................................................
436 Features
.............................................................................................................................
437 Function Descriptions
........................................................................................................
437
Serial Data Format
........................................................................................................................
437 Baud Rate Generation
..................................................................................................................
438 Hardware Flow Control
.................................................................................................................
440 IrDA
...............................................................................................................................................
441 RS485 Mode
.................................................................................................................................
443 Synchronous Master Mode
...........................................................................................................
445 Interrupts and Status
....................................................................................................................
447 PDMA Interface
.............................................................................................................................
447
Register Map
.....................................................................................................................
447 Register Descriptions
.........................................................................................................
448
USART Data Register – USRDR
..................................................................................................
448 USART Control Register – USRCR
..............................................................................................
449 USART FIFO Control Register –
USRFCR...................................................................................
451 USART Interrupt Enable Register – USRIER
...............................................................................
452 USART Status & Interrupt Flag Register –
USRSIFR...................................................................
454 USART Timing Parameter Register – USRTPR
...........................................................................
456 USART IrDA Control Register – IrDACR
......................................................................................
457 USART RS485 Control Register –
RS485CR...............................................................................
458 USART Synchronous Control Register – SYNCR
........................................................................
459 USART Divider Latch Register –
USRDLR...................................................................................
460 USART Test Register – USRTSTR
...............................................................................................
461
22 Universal Asynchronous Receiver Transmitter (UART)
................................ 462 Introduction
........................................................................................................................
462 Features
............................................................................................................................
463 Function Descriptions
........................................................................................................
463
Serial Data Format
........................................................................................................................
463 Baud Rate Generation
..................................................................................................................
464 Interrupts and Status
....................................................................................................................
466 PDMA Interface
.............................................................................................................................
466
Register Map
.....................................................................................................................
466 Register Descriptions
.........................................................................................................
467
UART Data Register – URDR
.......................................................................................................
467 UART Control Register – URCR
...................................................................................................
468 UART Interrupt Enable Register – URIER
....................................................................................
469 UART Status & Interrupt Flag Register – URSIFR
.......................................................................
471 UART Divider Latch Register – URDLR
.......................................................................................
472 UART Test Register – URTSTR
....................................................................................................
473
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Table of C ontents
23 Smart Card Interface (SCI)
...............................................................................
474 Introduction
........................................................................................................................
474 Features
.............................................................................................................................
475 Functional Descriptions
.....................................................................................................
475
Elementary Time Unit Counter
......................................................................................................
475 Guard Time Counter
.....................................................................................................................
478 Waiting Time Counter
...................................................................................................................
478 Card Clock and Data Selection
.....................................................................................................
479 Card Detection
.............................................................................................................................
479 SCI Data Transfer Mode
...............................................................................................................
480 Interrupt Generator
.......................................................................................................................
482 PDMA Interface
.............................................................................................................................
483
Register Map
.....................................................................................................................
483 Register Descriptions
.........................................................................................................
484
SCI Control Register – CR
............................................................................................................
484 SCI Status Register – SR
.............................................................................................................
486 SCI Contact Control Register – CCR
............................................................................................
487 SCI Elementary Time Unit Register – ETUR
................................................................................
488 SCI Guard Time Register – GTR
..................................................................................................
489 SCI Waiting Time Register –
WTR................................................................................................
490 SCI Interrupt Enable Register – IER
.............................................................................................
491 SCI Interrupt Pending Register – IPR
...........................................................................................
492 SCI Transmit Buffer – TXB
............................................................................................................
494 SCI Receive Buffer – RXB
............................................................................................................
494 SCI Prescaler Register – PSCR
...................................................................................................
495
24 USB Device Controller (USB)
..........................................................................
496 Introduction
........................................................................................................................
496 Features
.............................................................................................................................
496 Functional Descriptions
.....................................................................................................
497
Endpoints
......................................................................................................................................
497 EP_SRAM
.....................................................................................................................................
497 Serial Interface Engine – SIE
........................................................................................................
498 Double-Buffering
...........................................................................................................................
498 Suspend Mode and Wake-up
.......................................................................................................
499 Remote Wake-up
..........................................................................................................................
500
Register Map
.....................................................................................................................
500 Register Descriptions
.........................................................................................................
501
USB Control and Status Register – USBCSR
..............................................................................
501 USB Interrupt Enable Register – USBIER
....................................................................................
503 USB Interrupt Status Register – USBISR
.....................................................................................
504 USB Frame Count Register – USBFCR
.......................................................................................
505 USB Device Address Register – USBDEVAR
..............................................................................
506
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Table of C ontents
Table of C ontents
USB Endpoint 0 Control and Status Register – USBEP0CSR
..................................................... 507 USB
Endpoint 0 Interrupt Enable Register – USBEP0IER
........................................................... 508 USB
Endpoint 0 Interrupt Status Register – USBEP0ISR
............................................................ 510
USB Endpoint 0 Transfer Count Register – USBEP0TCR
............................................................511 USB
Endpoint 0 Configuration Register – USBEP0CFGR
........................................................... 512 USB
Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3
............................... 513 USB Endpoint 1 ~ 3 Interrupt
Enable Register – USBEPnIER, n = 1 ~ 3
..................................... 514 USB Endpoint 1 ~ 3
Interrupt Status Register – USBEPnISR, n = 1 ~ 3
...................................... 515 USB Endpoint 1 ~ 3
Transfer Count Register – USBEPnTCR, n = 1 ~ 3
..................................... 516 USB Endpoint 1 ~ 3
Configuration Register – USBEPnCFGR, n = 1 ~ 3
..................................... 517 USB Endpoint 4 ~ 7
Control and Status Register – USBEPnCSR, n = 4 ~ 7
............................... 518 USB Endpoint 4 ~ 7 Interrupt
Enable Register – USBEPnIER, n = 4 ~ 7
..................................... 520 USB Endpoint 4 ~ 7
Interrupt Status Register – USBEPnISR, n = 4 ~ 7
...................................... 521 USB Endpoint 4 ~ 7
Transfer Count Register – USBEPnTCR, n = 4 ~ 7
..................................... 522 USB Endpoint 4 ~ 7
Configuration Register – USBEPnCFGR, n = 4 ~ 7
..................................... 523
25 Peripheral Direct Memory Access (PDMA)
..................................................... 524
Introduction
........................................................................................................................
524 Features
.............................................................................................................................
524 Functional Description
.......................................................................................................
525
AHB Master
..................................................................................................................................
525 PDMA Channel
.............................................................................................................................
525 PDMA Request Mapping
..............................................................................................................
525 Channel Transfer
..........................................................................................................................
526 Channel Priority
............................................................................................................................
526 Transfer Request
..........................................................................................................................
527 Address Mode
...............................................................................................................................
527 Auto-Reload
..................................................................................................................................
528 Transfer Interrupt
..........................................................................................................................
528
Register Map
.....................................................................................................................
529 Register Descriptions
.........................................................................................................
530
PDMA Channel n Control Register – PDMACHnCR (n = 0 ~ 5)
................................................... 530 PDMA
Channel n Source Address Register – PDMACHnSADR (n = 0 ~ 5)
................................ 532 PDMA Channel n Destination
Address Register – PDMACHnDADR (n = 0 ~ 5)
......................... 532 PDMA Channel n Transfer Size Register
– PDMACHnTSR (n = 0 ~ 5) .......................................
533 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR (n
= 0 ~ 5) ........................ 534 PDMA Interrupt Status
Register – PDMAISR
...............................................................................
535 PDMA Interrupt Status Clear Register – PDMAISCR
...................................................................
536 PDMA Interrupt Enable Register – PDMAIER
..............................................................................
537
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Table of C ontents
26 External Bus Interface (EBI)
............................................................................
539 Introduction
........................................................................................................................
539 Features
.............................................................................................................................
539 Function Descriptions
........................................................................................................
540
Non-Multiplexed 8-Bit Data 8-Bit Address Mode
..........................................................................
541 Non-Multiplexed 16-Bit Data N-bit Address Mode
........................................................................
542 Multiplexed 16-Bit Data, 16-Bit Address Mode
.............................................................................
543 Multiplexed 8-Bit Data, 20-Bit Address Mode
...............................................................................
544 Write Buffer and EBI Status
..........................................................................................................
545 Bus Turn-around and IDLE Cycles
...............................................................................................
545 AHB Transaction Width Conversion
.............................................................................................
546 EBI Bank Access
..........................................................................................................................
548 PDMA Request
.............................................................................................................................
548
Register Map
.....................................................................................................................
549 Register Descriptions
.........................................................................................................
549
EBI Control Register – EBICR
......................................................................................................
549 EBI Status Register – EBISR
........................................................................................................
551 EBI Address Timing Register – EBIATR
.......................................................................................
552 EBI Read Timing Register – EBIRTR
...........................................................................................
553 EBI Write Timing Register – EBIWTR
...........................................................................................
554 EBI Polarity Register – EBIPR
......................................................................................................
555
27 Cyclic Redundancy Check (CRC)
....................................................................
556 Introduction
.......................................................................................................................
556 Features
.............................................................................................................................
556 Function Descriptions
........................................................................................................
557
CRC Computation
.........................................................................................................................
557 Byte and Bit Reversal for CRC Computation
................................................................................
557 CRC with PDMA
...........................................................................................................................
558
Register Map
.....................................................................................................................
558 Register Descriptions
.........................................................................................................
559
CRC Control Register – CRCCR
..................................................................................................
559 CRC Seed Register – CRCSDR
...................................................................................................
560 CRC Checksum Register – CRCCSR
..........................................................................................
560 CRC Data Register – CRCDR
......................................................................................................
561
28 AES Encrypt/Decrypt Interface (AES)
............................................................. 562
Introduction
........................................................................................................................
562 Features
.............................................................................................................................
562 Function Descriptions
........................................................................................................
563
AES Mode Description
..................................................................................................................
563 AES Status
...................................................................................................................................
566 AES PDMA Interface
....................................................................................................................
566
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Table of C ontents
Table of C ontents
AES Interrupt
................................................................................................................................
566 AES Initial Vector
..........................................................................................................................
566 AES Word Swap
...........................................................................................................................
567
Register Map
.....................................................................................................................
567 Register Descriptions
.........................................................................................................
568
AES Control Register – AESCR
...................................................................................................
568 AES Status Register – AESSR
.....................................................................................................
569 AES DMA Register – AESDMAR
..................................................................................................
570 AES Interrupt Status Register – AESISR
......................................................................................
571 AES Interrupt Enable Register – AESIER
.....................................................................................
572 AES DATA Input Register –
AESDINR..........................................................................................
573 AES DATA Output Register – AESDOUTR
...................................................................................
573 AES Key Register n – AESKEYRn, n = 0 ~ 7
...............................................................................
574 AES Initial Vector Register n – AESIVRn, n = 0 ~ 3
.....................................................................
574
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List of Tables
List of Tables Table 1. Features and Peripheral List
.....................................................................................................
30 Table 2. Document Conventions
.............................................................................................................
32 Table 3. Register Map
.............................................................................................................................
37 Table 4. Flash Memory and Option Byte
.................................................................................................
42 Table 5. Relationship Between Wait State Cycle and HCLK
..................................................................
42 Table 6. Booting Modes
..........................................................................................................................
43 Table 7. Option Byte Memory Map
.........................................................................................................
47 Table 8. Access Permission of Protected Main Flash Page
....................................................................
48 Table 9. Access Permission When Security Protection is Enabled
......................................................... 49 Table
10. FMC Register Map
.................................................................................................................
50 Table 11. Operation Mode Definitions
.....................................................................................................
71 Table 12. Enter/Exit Power Saving Modes
..............................................................................................
71 Table 13. Power Status after System Reset
...........................................................................................
72 Table 14. PWRCU Register Map
............................................................................................................
73 Table 15. Output Divider 2 Value
Mapping..............................................................................................
86 Table 16. Feedback Divider 2 Value
Mapping.........................................................................................
86 Table 17. USB PLL Output Divider 2 Value Mapping
..............................................................................
88 Table 18. USB PLL Feedback Divider 2 Value Mapping
.........................................................................
88 Table 19. CKOUT Clock Source
.............................................................................................................
91 Table 20. CKCU Register