Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G. Fettweis chair

HW/SW Co-design Praktikum

Erik Fischer & Emil Matúš

erik.fischer@ifn.et.tu-dresden.de

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Benefits from this Praktikum

Learn the practical use of HW/SW-Codesign from the application programmers point of view

Get familiar with the Tensilica IDE which is used by many companies today to create customized DSPs

Since the IDE is based on the very common Eclipse framework this knowledge also facilitates the access to other Eclipse based IDEs

Course attendance certificate (Seminarschein) for 2 SWS

Optional: get a grade for the final written elaboration (3 pages)

TU Dresden, CATS Slide 2

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TU Dresden, CATS Slide 3

Tensilica Concept

Hot Spot

Hot Spot

Accelerate

RISC

Enhanced RISC (ASIP)

Software

Compiler

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TU Dresden, CATS Slide 4

Tensilica Instruction Extension (TIE) language

Extension of Xtensa processor cores: new processor instructions, execution units, register files state variables.

TIE: hybrid of the Verilog and C languages easy to learn and use Xtensa Xplorer interfaces with Tensilica TIE Compiler to rapidly

explore and verify TIE implementations Goal:

to understand the Tensilica tool set for configurable processor, get familiar with the Xtensa Xplorer IDE, learn how tune the processor configuration and how to use TIE.

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TU Dresden, CATS Slide 5

HW architecture: Xtensa LX 2

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TU Dresden, CATS Slide 6

Creating Pipelined Instructions

operation MUL_SRL_16 {out AR z, in AR a, in AR b} {} {

wire [31:0] m = TIEmul(a[15:0],b[15:0],1); assign z = {16'b0, m[31:16])};

} schedule ms {MUL_SRL_16} {def z 2;}

                                                       

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TU Dresden, CATS Slide 7

DLP: SIMD Extension

operation MUL_SRL_16 {out AR z, in AR a, in AR b} {} {         

wire [31:0] m1 = TIEmul(a[31:16],b[31:16],1);        wire [31:0] m0 = TIEmul(a[15:0],  b[15:0],  1); assign z = {m1[31:16]), m0[31:16]};

}schedule ms {MUL_SRL_16} {def z 2;}

                                                                                      

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TU Dresden, CATS Slide 8

DLP: SIMD and Vector RF

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TU Dresden, CATS Slide 9

Tool Flow

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TU Dresden, CATS Slide 10

Work plan

Registration & Making appointment for introduction Get Familiar with the Xtensa Xplorer Introduction to TIE Profile application – identify hotspots Create Your Own TIE Instructions Analyse & Iterate