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IBM Technology Symposium

Impact of Input Voltage on Server PSU-

Efficiency, Power Density and Cost

Sriram Chandrasekaran

November 13, 2012

Presentation Outline

• Redundant Server PSU Performance Metrics

• Efficiency, Power Density, Features

• Architectural Overview of Server PSU

• Overview of Converter Topologies

• Impact of input voltage on PSU Metrics

• AC Input voltage

22

• AC Input voltage

• High line/Low line

• 277Vac

• Dual input AC

• DC Input voltage

• 380Vdc

• 260Vdc

• 48Vdc

Redundant Server PSU Performance Metrics

• Efficiency

80 PLUS Certification 230V Internal Redundant

% of Rated Load 10% 20% 50% 100%

80 PLUS Bronze --- 81% 85% 81%

80 PLUS Silver --- 85% 89% 85%

80 PLUS Gold --- 88% 92% 88%

80 PLUS Platinum --- 90% 94% 91%

80 PLUS Titanium 90% 94% 96% 91%

33

• Processed Power Density: > 40W/in3

• Features• Sleep Mode Operation

• High Accuracy Reporting

• No-load input power

• Peak power profiles with throttling

• Event Recording

• Field-upgradability of firmware

80 PLUS Titanium 90% 94% 96% 91%

FlexPower 3kW PSU Efficiency @ 230Vin

84

86

88

90

92

94

96

PS

U E

ffic

ien

cy (

%)

% Load Efficiency

5 78.41

10 87.82

15 91.49

20 93.02

25 93.78

30 94.21

35 94.46

40 94.62

45 94.68

50 94.67

55 94.63

44

76

78

80

82

84

0 10 20 30 40 50 60 70 80 90 100

PS

U E

ffic

ien

cy (

%)

% Load

55 94.63

60 94.56

65 94.50

70 94.41

75 94.28

80 94.15

85 93.88

90 93.68

95 93.46

100 93.22

PSU Block Diagram

EMI

Filter

Rectifier &

Inrush

Control

Boost PFC

(80 ~100kHz)

Isolated

DC/DC

(80

~100kHz)

Bias & To power supply

1-φ AC

90-264VACV1 = 12V

~400V ORing

FETs

ORing

55

Bias &

standby

(80-100kHz)

Control

Isolation

Communication

To power supply

To system

Vsb = 12V

Vhk

ORing

FETs

Digital PFC control

Input current

Bus voltage

Switching FrequencyVAC

Boost PFC FET gating

signals, Relay drive

Primary and

secondary side FET

gating signals

Isolation barrierPM Bus

Digital Load share

DC Algorithms

System

Control Block Diagram

Analog or Digital

Control IC

66

Primary side

digital controller

Primary side

monitoring and

communication

VAC

Bus voltage,

rectified

current

DC/DC

Controller

Voltage/current

analog control

Output voltage,

current signals

8 bit Silabs

Micro controller

Housekeeping

and black box

Secondary side

microcontroller

PFC

Power & RMS

algorithms

Digital Isolator

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Converter Topologies

R1

R

DC1

DC

CR

CHSA1

DA1

DCH

LB1

DC1

SA1

DA1LB1DA2

LB2

SA2

CHL

N

Power Factor Correction (AC ���� Bulk Vdc)

Conventional Boost PFC Bridgeless Boost PFC

88

R2 DC2DC2

A1 A2

• Robust, time tested topology

• DCM, BM (Boundary Mode), CCM

• Interleaving for higher power

• Innovations• Soft switching variations

• Magnetics design

• Control

• Higher efficiency

• EMI compliance is challenging

• Innovations• EMI compliance

• Magnetics Design

• Control

Isolated DC/DC Conversion (Bulk Vdc ���� 12V)

Single Stage Two-Stage

PWM

(1) Phase-shifted Full Bridge

(2) Half-Bridge

(3) 2T forward

(1) Boost + Half-bridge (50% duty cycle)

(2) Buck + Half-bridge (50% duty cycle)

Resonant Frequency modulated LLC(1) Boost + fixed frequency LLC

(2) Buck + fixed frequency LLC

Primary side

99

• Interleaving variations for higher power and ripple cancellation

Secondary side

• Synchronous Rectification

• Current doublers

• Coupled inductors

• Center-tapped/single winding variations

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Impact on Input Voltage on PSU

Single Phase AC Input

• Universal line (90Vac – 264Vac): 1000W, >30W/in3

• High line/de-rated low line

1111

• 277Vac

Single Phase AC Input

1-φ ACDC

DC

AC

DC

Vo = 12V DC

DC BUS

(400V nom)EMI + PFC Isolated DC/DC

REVERSE AIR FLOW

1212

FORWARD AIR FLOW

• Impact of input voltage range is dominant on design of the PFC power train• Efficiency and power density• 120Hz ripple on DC bus � E-cap life

• Second order impact on DC/DC design from air-flow direction• Packaging and Layout

277Vac• 277Vac is Line-Neutral (Y) from 480Vac Line-Line (∆) input

• Input voltage max is 277Vac+10% = 305V

• Higher efficiency and density due to lower input current

• Front-End

• AC inlet

• X and Y caps

1313

• X and Y caps

• 305V rated safety caps are available in the market now

• Rectifier/PFC Stage

• Peak Rectified 305Vac = 430Vdc

• Voltage rating switching devices can stay at 600V is Vbulk < 480V (80% derating)

• 500V rated bulk capacitance required

• High Vbulk results in lower Cbulk for given hold-up spec

• PF and THD impact due to lower input current

277Vac

• DC/DC Stage

• No change to primary side if Vbulk < 480V

• 600V/650V devices can continue to be used

• For PWM topologies, SR FET voltage rating may increase from 60V to 75V

• Device portfolio not as broad in the 75V space

• Cost and efficiency impact

1414

• No impact to SRs for resonant topologies

• SR Voltage rating is 2X output voltage

277Vac – Hold-up Capacitance Requirement

Bulk capacitance/Watt for 10ms of hold-up

2

2

,

21 o,maxH

Co t

bus nom

max

PC t

k V nV

D

η=

−

• Po ���� Maximum output power

• tH ���� Hold-up time, 10ms

• Vbus,nom���� Bulk voltage @ full load

• Dmax ���� Max allowable duty cycle, 45%

• Vo ���� Output voltage, 12.2V

1515

• Vo ���� Output voltage, 12.2V

• Vdropout ���� Drop out voltage, Vont/Dmax• nt ���� Transformer turns ratio, 12:1

• kC ���� capacitor derating factor, 80%

• ηηηη ���� DC/DC Stage efficiency, 96%

33% reduction in Cbulk

• Bulk capacitance requirement is reduced at higher Vbulk.

• Availability of 500V caps (105C, 2000hr) is limited

• Best option is to build a series/parallel cap bank � Impact to power density• Largest capacitance in 30x50 can size is 300uF

• Large drop in foil gain results in reduction of C/m2 voltage rating increases from 450V to 500V

277Vac – PFC Efficiency Improvement

PFC Efficiency comparison at 3kW

1616

• Modulation range of bulk voltage as a function of load is limited with 277Vac

• Gains at light loads are insignificant due to dominant switching losses

• PFC design is optimized for reduced current at 277Vac � Density advantage• Higher inductance boost choke

• Bulk cap availability is the limiting factor for increasing density

Dual Redundant AC Input

• AC input fed into PSU through two AC inlets (FEED1 and FEED2)

• FEED 1 is the default input

• PSU monitors both AC inputs continuously

• PSU should switch to FEED 2 in the event of AC FAIL on FEED 1

• PSU should switch back to FEED 1 when “good” AC is available

1717

• Density and Cost impact due to

• AC Transfer Circuitry (Relay network)

• Monitoring and Control circuitry

• No efficiency impact

Dual Redundant AC Input – AC Transfer Circuit

L1

L2

L

RLY0

PRI_RTN

RLY_LINE

AC_DETECT

L1 N1 L2 N2

1818

N2

N1

PSU

N

RLY1

PRI_RTN

RLY_NEUT

DC Input PSU

• 380Vdc – High Voltage DC Input

• 2006 study from Lawrence Berkeley labs showed 7% reduction in input power

• Hold-up requirements will dictate “size” of front-end

• 160Vdc – 265Vdc – Pass-through from Standby Power System

• PSU to operate from AC input and DC input.

• In the event of AC failure, DC input will be made available with specified duration

1919

• In the event of AC failure, DC input will be made available with specified duration

• PSU will power up within specified duration after availability of “GOOD” DC power

• 48Vdc

• 36VDC – 72VDC input (from battery bank)

• Reverse polarity protection

• Hold-up time of 2ms - 8ms

• High current makes design of front-end challenging

DC Input PSU Block Diagram

EMI

Filter

Inrush Control &

Reverse Polarity

Protection or

Bridge Rectifier

Front-end

Boost

(80 ~100kHz)

Isolated

DC/DC

(80

~100kHz)

Bias & To power supply

Vdc V1 = 12VORing

FETs

ORing

2020

Bias &

standby

(80-100kHz)

Control

Isolation

Communication

To power supply

To system

Vsb = 12V

Vhk

ORing

FETs

High Voltage 380Vdc Input

• Efficiency improvement of front-end boost due to• Elimination of Bridge Rectifier

• “Near Unity” Step-up ratio from 380Vdc to 430Vdcmax � ~99%

• Density Improvement due to reduced input current

• No significant change in PSU architecture• Simplified RMS detection and control algorithms on front-end• MPPF/MPF high voltage caps used for DM and CM filtering

2121

• MPPF/MPF high voltage caps used for DM and CM filtering• No impact to DC/DC stage or AUX stage

Vin = 380V, Vo = 420V, fs = 60kHz

Front-End Boost Efficiency (3kW)

2222

• Efficiency estimations are based on best-available component models

High Voltage 380Vdc Input - Connectors

• We have looked at Positronics connectors as an option

2323

• We also expect front-loading designs where input/output terminals are on

same connector system

DC Input PSU (165Vdc – 260Vdc)

• 160Vdc – 265Vdc – Pass-through from Standby Power System

• PSU to operate from AC input and DC input

• In the event of AC failure, DC input will be made available with specified duration

• PSU will power up from DC input within specified duration from instant of

2424

• PSU will power up from DC input within specified duration from instant of availability of “GOOD” DC power

• No change in PSU architecture

• AC detection/metering algorithm has to accommodate DC input for• Determining turn-on/turn-off thresholds

• Reporting Input power/voltage/current

DC Input PSU (48VDC)

• Counterparts of AC input PSUs in same form factor at same or lower power levels

• Reduced hold-up time (2ms to 8ms)

• Reverse Polarity Protection is required

• Achieving high densities at higher power levels (>1000W) is a challenge due to high input current

2525

high input current

Common-Mode Choke based on UU-core

Input fuse and EMI Filter

2626

Common-Mode Choke based on UU-core

• At 36Vin/3kW input current is ~85A

• For every mΩ , power loss is 7.225W

• 4in of 14AWG wire has a resistance of 1mΩ at 75C

• Multi-filar magnet wire or copper stampings

• UU-core geometry results in better window utilization

• Low L/High C filter to minimize turns, hence copper loss

sDT

g1

g2

g3

φL1 φL2 φL3

φC∆φC

∆φL

L

C

φ

φ

∆

∆

D

2

3

4

Integrated Boost Choke for Front-End

2727

• 3 boost chokes integrated within a single ferrite core assembly (54mm (L) x 24mm (W) x 40mm (H))

• Flux and currents are interleaved resulting low core and copper loss

• Fluxes are interleaved in ~72% of core volume (very low core loss)

• Per phase inductance of 28uH

3

sTsDT

sT

D

84

86

88

90

92

94

96P

SU

Eff

icie

ncy

(%

)

% Load % Eff

10 93.17

20 94.46

30 94.30

40 93.85

50 93.25

60 92.57

Estimated Efficiency at 48Vdc/3kW

2828

76

78

80

82

84

0 10 20 30 40 50 60 70 80 90 100

PS

U E

ffic

ien

cy (

%)

% Load

60 92.57

70 91.84

80 91.09

90 90.33

100 89.57

• PSU efficiency is dominated by conduction loss due to high input and output currents

• As a result, efficiency peaks at light loads and decreases down to 100% load due to I2R loss

Summary

• Impact of input voltage on redundant server PSU architecture and metrics were covered.

• No significant changes in power converter topologies other than obvious updates to component selection

• Higher input voltages lead to higher efficiency

2929

• Density improvements are dictated by advancements in component technologies(1) 500V E-cap availability for 277Vac designs

(2) High current front-end designs for 48Vdc designs

• High Voltage DC input PSUs are more efficient and simpler designs• Require “re-architecting” of the power delivery infrastructure to server rack