iC-LNG(B) EVAL LN1A · iC-LNG(B) EVAL LN1A MICROCONTROLLER BOARD DESCRIPTION Rev A2, Page 6/21 J3: µC Programmer input (Microchip PICKit3) 6-pin connector, male PIN Name Function

preliminary preliminary iC-LNG(B) EVAL LN1AMICROCONTROLLER BOARD DESCRIPTION

Rev A2, Page 1/21

ORDERING INFORMATION

Type Order Designation Description Options

Microcontroller Board iC-LNG EVAL LN1A

iC-LNB EVAL LN1A

Microcontroller Board for evaluation with iC-LNG and

iC-LNB (same board, no changes required)

Ready to operate, accessible through the GUI using a PC adapter

Evaluation Kits iC-LNG EVAL LNG2M-1R Evaluation kits for iC-LNG with PCB, LED and

code disc (see description of evaluation kit )

iC-LNB EVAL LNB2M-1R iC-LNB is currently in preparation

Software iC-LNG GUI GUI software for Windows PC

Stores setup to file, communication with iC-LNG

Please see www.ichaus.de/product/iC-LNG for download informa-

tion

PC Adapter iC-MB3 iCSY MB3U-I2C PC-USB to I2C Adapter

BOARD LN1A

Figure 1: Evaluation board LN1A

(size 100 mm x 80 mm)

PLUG CONFIGURATION

J1/J2 Pin configuration suitable for connector

J1/J2 of LNB1M, LNB2M and LNG2M

J3 Microchip ICSP Programmer

(e.g. PICKit 3)

J4 SSI Interface

J5 I2C Interface

J6 Parallel Interface

Copyright © 2013 iC-Haus http://www.ichaus.com

http://www.ichaus.de/product/iC-LNG

http://www.ichaus.com


Rev A2, Page 2/21

Figure 2: Component side (size 100 mm x 80 mm)

TERMINAL DESCRIPTION

VDD +5 V I/O Port Supply Voltage (150mA)

GND Ground

VDDA Supply Voltage

PSIN Analog Output Sine +

NSIN Analog Output Sine -

PCOS Analog Output Cosine +

NCOS Analog Output Cosine -

LED iC-LNx Current Control

ERROR iC-LNx Error Message

TERMINAL DESCRIPTION

STATUS µC Status Message

ERROR µC Error Message

INCA Quadrature Output A

INCB Quadrature Output B

INCZ Quadrature Output Z


Rev A2, Page 3/21

CIRCUIT DESCRIPTION

I2C

WSL

10

LNB

J1W

SL20

Parr

alle

l Int

erfa

cew1

8x1

ICSP

w6x

1LN

B J2

SSI 9

Pol S

UBD

WSL

20

RC

5 1314

RC

6

RC

715

EPAD

SUB

VDD

17

TS5A

2315

9U3

-A

20R

B2R

B321

RB4

22

RB523

RB624

25

RB7

RC

0 8

RC

1 9

RC

2 10

RC

3 11

RC

4 12

2627

RA0

28

RA1

1R

A2R

A32

RA4

3

RA5

4

RA6

7R

A76

18R

B0RB1

19

U1

PIC

18F2

321

GND

15

16G

ND2

MC

LR

GN

D1

R5

10k

1kR

10

10k

R4

R9

1k

R6

C4

100n

F

C3

C19

1nF

10k

1nF

22pF

22pFC

1

100n

FC

5

R7

10k

C2

10k

R3

10M

HzX1

RES

ETSW

1

VDD

SW3

PRES

ET

RD

GND

U5-S

GNDVP

VDD

AD

2R2

10k

TS5A

2315

9

U5-A

TS5A

2315

9

VP

TS5A

2315

9U5

-B

TS5A

2315

9U4

-S

GND

TS5A

2315

9U4

-A

U6-S

TS5A

2315

9G

NDVP

U4-B

TS5A

2315

9

TS5A

2315

9U6

-A

GNDVP

TS5A

2315

9U3

-B

10k

R1

U3-S

TS5A

2315

9C

18 100n

F

10k

R13

C15

100n

F

1μF

C17

10μF

C14

10μF

C16

J18

J17

J112

VCC Y

9 10Z

5

GND

67

3NR

E

RO

2

RXP

13

1SH

DN

TXP

8

14U2 M

AX34

65

12A B

11

DE

4

DI

SW2

DIR

J116

J11510

J114

J113

J11711

INC

Z

J111

J1 J119

J2

1μF

C13

1μF

C12

C11

1μF

C10

1μF

C8

100n

F

1μF

C9

470R

R8

C6

100n

F

1k

R11

1k

100n

FC

20

R12

R14 10

k

C21

1μF

3J4

2J4

1

C7

100n

F

ERR

OR

J617

J616

J4

J61

J613

4

J19

JP6

JP2

6

J16

J15

J1

4J3 3

J13

J12

J3J3

1

J11

J3 5J3

7

J26

J25

J3 2

J24

J23

J22

J2

9

J21

J120

J118

J66

J65

J610

J6

4

J63

J62

J67

J614

JP4

J6

J220

J219

J218

INC

A

12

J217

J216

J215

J28

J214

J213

J2

LED

J210

J29

JP3

J49

STAT

US

4

J48

J47

J46

J618

JP5

J45

J4

6

J510

J59

J584

J53

J57

J5J51

NCO

S

J55

J5

NSIN

PSIN

J52

JP1

INC

B

PCO

S

J68

J612

J611

J615

SEL_

SW

VDD

NSE

L_SS

I

VDD_I2C

VDD

PO3

PO4

PO2

PO9

PO10

PO11

PO12

PO13

MO+

MO-

VB

VDDA

VDD

INCA

INCB

INCZ

SCL

VDD

VDD

CS

MISO

MOSI

SDA

MCLR

_UAR

T

MCLR

_I2C

ERR_L

NB

DIN

DIN

VDD

ERR_L

NB

GND

GND

VDD

VDD

VDD

VDD

VDD_S

SI

VDD

VDDA

MA+

SSI_SC

LMA-

SL+

DOUT

SL-

VDD

GND

GND

GND

VDD

VDD

NMCLR

GND

DIN

SSI_SC

L

VDD

NSL

_LNB

PGC

PGD

SCK_L

NB

DIR

VDD

INCZ

INCB

INCA

VDD

VDD

VDD

VDD

DOUT

PO0

PO1

PO5

PO6

PO7

PO8

PO14

PO15

C3

1nF

1nF

C19

R6

10k

100n

FC

4

R4

10k

1kR

9

10k

R5

R10

1k

D1

GN

PIC

18FX

X21

PIC

18F2

321

U1

U3-A

TS5A

2315

9

U4-A

TS5A

2315

9

U4-S

TS5A

2315

9

U5-B

TS5A

2315

9

TS5A

2315

9U5

-A

10k

R2

U5-S

TS5A

2315

9

VDD

AR

DD2

GND

VDDPR

ESET

SW3

SW1

RES

ET

R3

10k

X110

MHz

10k

R7

22pFC

2

C1

22pF

C5

100n

F

MAX

3465

U2

J1J1 J1

C14

10μF

C16

10μF

100n

FC

15

C17

1μF

100n

FC

18

R13 10

kR

110

k

TS5A

2315

9U3

-S

U3-B

TS5A

2315

9

U6-A

TS5A

2315

9TS

5A23

159

U6-S

TS5A

2315

9U4

-B

1μF

C11

1μF

C10

C13

1μF

C12

1μF

J1J2

INC

Z

J1J1 J1J1 J1J1J1

DIRSW

2

J3

J1

J3J3

J3

J1J1

J3

J1J1J1 J1

JP6

JP2

J6 J6

ERR

OR

J6J6

J4J4J4

100n

FC

7

10k

R14

1μF

C21

C20

100n

F

1kR12

1kR

11

R8

470R

100n

FC6

100n

FC

8C

91μ

F

J2J2 J2J2J2 J2J2J2 J2J2J2

INC

A

J6

JP4

J6J6J6 J6J6J6 J6J6

J2 J1J1J2J2J2 J2J2J2

J3

J6 J6J6 J6 JP1

INC

B

PCO

S

NSIN

PSIN

J5J5

NCO

S

J5J5J5 J5J5 J5J5J5

J6

JP5

J4J4 J4J4J4

JP3

J4

STAT

US

LED

J2

Figure 3: Circuit diagram including optional components


Rev A2, Page 4/21

ASSEMBLY PART LIST

Device Value (typical) Comment

C1, C2 22 pF (CSMD0603)

C3, C19 1 nF (CSMD0603)

C4, C5, C6, C7, C8,

C15, C18, C20

100 nF (CSMD0603)

C9, C10, C11, C12,

C13, C17, C21

1 µF (CSMD0603)

C14 10 µF (ESMD SIZE A)

C16 10 µF (CSMD0805)

D1 LED green (PLCC2)

D2 LED red (PLCC2)

J1, J2 CONN WSL 20 MALE

J3 W6X1

J4 CONN SUBD 9 FEMALE RH

J5 CONN WSL 10 MALE

J6 W18X1

JP1, JP4, JP5, JP6 W2X1

JP2 W3x1

JP3 W2X1 SMD 0603

R1, R2, R3, R4, R5,

R6, R7, R13, R14

10 kΩ (RSMD0603)

R8 470 Ω (RSMD0603)

R9, R10, R11, R12 1 kΩ (RSMD0603)

SW1, SW3 OMRON B3S 1000

SW2 KNITTER ATE1

U1 PIC18F2321 QFN28 6X6 0.65 1

U2 MAX3465 SO14 3.9 1.27

U3, U4, U5, U6 TS5A23159 UQFN10 2.0X1.5 0.5

X1 PQ18G

X1 10 MHz XTAL HC49U


Rev A2, Page 5/21

BOARD, CONNECTOR PINOUT AND TERMINAL DESCRIPTION

Figure 4: LN1A Top view

J1: Signal input (J1 on LNB1M, LNB2M or LNG2M)

20-pin connector, male

PIN Name Function

1 INCZ Incremental Signal Z

2 INCB Incremental Signal B

3 INCA Incremental Signal A

4 ERR Alarm Message Output

5 NCOS Analog Voltage Signal Cosine -

6 PCOS Analog Voltage Signal Cosine +

7 NSIN Analog Voltage Signal Sine -

8 PSIN Analog Voltage Signal Sine +

9 DIR Code Direction (CW / CCW)

10 VDDA +5 V Supply Voltage

11 GND Ground

12 VDD +5 V I/O Port Supply Voltage

13 SCK SPI Clock

14 MOSI SPI Data Slave Input

15 MISO SPI Data Slave Output

16 CS SPI Chip Select

17 NSL Shift Register Load

18 DIN Shift Register IC Data Input

19 DOUT Shift Register IC Data Output

20 CLK Shift Register Clock

J2: Signal input (J2 on LNB1M, LNB2M or LNG2M)


PIN Name Function

1 TPC Parallel Output Bit 0

2 TPS Parallel Output Bit 1

3 INCA Parallel Output Bit 2

4 INCB Parallel Output Bit 3

5 INCZ Parallel Output Bit 4

6 POK Parallel Output Bit 5

7 PO6 Parallel Output Bit 6



10 CLK Parallel Output Bit 9

11 DOUT Parallel Output Bit 10

12 DIN Parallel Output Bit 11

13 NSL Parallel Output Bit 12

14 DIR Parallel Output Bit 13

15 TNS Parallel Output Bit 14

16 TNC Parallel Output Bit 15

17 VDDA +5 V Supply Voltage

18 GND Ground

19 VDD +5 V I/O Port Supply Voltage

20 LED LED Current Control

(Highside Output)


Rev A2, Page 6/21

J3: µC Programmer input (Microchip PICKit3)


PIN Name Function

1 MCLR/Vpp

2 VDD Target

3 VSS Ground

4 ICSP_DAT/PGD

5 ICSP_CLK/PGC

6 LVP

J4: SSI Interface input

D-sub 9-pin connector, female

PIN Name Function

1 VB +12 V supply voltage

2 MA + Clock input

3 MA - Clock input (inverted)

4 VDD +5 V supply voltage

5 SLI - Data input (inverted)

6 GND 0 V ground

7 SL + Data line

8 SL - Data line (inverted)

9 SLI + Data input

J5: I2C Interface


PIN Name Function

1 SCL I2C clock

2 GND_I2C I2C ground

3 SEL_SW Select Software

’1’ = programming via I2C

’0’ = SSI communication

4 VDD_I2C I2C +5 V supply voltage

5 MCLR Reset µC

6 NSEL_SSI Bridge pin 7 and pin 9

7 SDA I2C data

8 n. c.

9 MCLR_UART I2C data (NSEL_SSI = ’1’)

10 GND_I2C I2C ground

Note:

n. c. Pin not connected

JUMPER DESCRIPTION

Jumper Pin 1 Pin 2 Description

JP1 <VDD> <VDDA> Bridge VDD and VDDA

JP4 J3 Pin1 Capacitor C6 Bridge for µC programming via PICKit3

JP5 DOUT U2 Pin 5 Bridge iC-LNx Data Line and RS422 Transeiver Input DI

JP6 SCLK U2 Pin 2 Bridge iC-LNx Clock Line and RS422 Transeiver Output

RO

Jumper Pin 1 Pin 2 Pin 3 Description

JP2 VDD J5 VDD VDD J4 Select board supply voltage

recommendation:

use external power supply (jumper open)


Rev A2, Page 7/21

EXAMPLE APPLICATION

Microcontroller board LN1A can be used to commis-

sion and test optoencoder ICs iC-LNG and iC-LNB

(currently in preparation). Figure 5 shows all the eval-

uation kits/components needed for this purpose, tak-

ing iC-LNG as an example (c.f. Related Products and

Documentation).

• iC-LNG EVAL LNG2M-xR (EvalKit iC-LNG) or

iC-LNB EVAL LNB2M-xR

(EvalKit iC-LNB, currently in preparation)

• iC-LNG EVAL LN1A (microcontroller board)

• iC-LNB EVAL LN1A (same board as iC-LNG EVAL

LN1A)

• iC-MB3 iCSY MB3U-I2C (PC/USB to I2C adapter)

Figure 5: Example: iC-LNG EVAL LNG2M connected to iC-LNG EVAL LN1A

Figure 6: Encoder test application with iC-LNx EVAL LNx2M (x = B, G)

(screws and hub not included)


Rev A2, Page 8/21

IMPLEMENTING THE MICROCONTROLLER

The microcontroller (µC) on evaluation board LN1A

configures iC-LNB / iC-LNG after power-on. The mi-

crocontroller’s internal EEPROM stores this configura-

tion. During power-up the µC automatically recognizes

which type of IC is connected (iC-LNB or iC-LNG). If

the device is not programmed through the ABZ inter-

face, the µC writes the configuration stored in the EEP-

ROM to iC-LNx. iC-LNB’s and iC-LNG’s configuration

parameters are stored in different areas of the EEP-

ROM so that they do not influence one another.

µC

I2C

SSI

ABZ

SPI

PCSSI

Interface

ABZInterface

SCL

iC-LNxSPI

Interface

A

B

Z

Figure 7: Interfaces

Possible configurations

There are three possible configurations for microcon-

troller programming:

• I2C configuration

• Advanced SSI configuration

• ABZ configuration (currently in development)

ABZ configuration is only available during power-up.

I2C and advanced SSI configuration can be applied

during operation. It is also possible to combine the two.

Figure 8 shows the µC sequence following power-up.

Power-on

ABZ configuration

Read µC EEPROMcontents

iC-LNxconfiguration through SPI

µC runningconfiguration

through SSI or I2C

µC configurationthrough

ABZ interface

Yes

No

Figure 8: Power-up sequence

µC firmware: version recognition

The microcontroller permits the current firmware ver-

sion to be read out (see I2C interface).


Rev A2, Page 9/21

I2C INTERFACE

The µC behaves like a I2C slave with a 7-bit device ID

of 0x50. The interface permits read and write access

to internal µC registers. During power-on the µC auto-

matically recognizes which type of IC is connected.

If the microcontroller detects iC-LNB, its register map

is as follows:

Address Description

0x00-0x12 iC-LNB register

0x13-0x15 iC-LNB position value

0x17 µC error register

0x18 µC status register

0x19 µC firmware recognition

0x20 µC config

Table 1: µC register map for iC-LNB

If the microcontroller detects iC-LNG, its register map

is as follows:

Address Description

0x00-0x0F iC-LNG register

0x13-0x14 iC-LNG position value

0x17 µC error register

0x18 µC status register

0x19 µC firmware recognition

0x20 µC config

Table 2: µC register map for iC-LNG

On write access through the I2C the second sent

byte is equivalent to the register address. The ensu-

ing bytes contain the data. After each data byte the

internal address counter is increased by one. The

amended register value is transmitted to iC-LNx’s SPI

interface. It is thus possible to quickly change the con-

figuration of iC-LNx.

Sending the I2C condition after setting the register ad-

dress enables read access (standard I2C access).

The µC error flag register can be read out and accept

at address 0x17. The error flag bits are cleared by writ-

ing a ’1’ to the correspond Bit position (see Table 3).

µC error Addr. 0x17; bit 7:0 RW - 0

Bit Description

0 SPI communication error flag, active high

1 ABZ communication error flag, active high

2 I2C address error flag (greater than 0x20), active

high

3 I2C register address error flag (greater than 0x09

by iC-LNG respectively 0x11 by iC-LNB), active

high

4 TMO task duration error flag (eradication of the task

to long), active high

5 Power up configuration error flag, active high

6 ADSSI communication error flag, active high

7 POSOK Timeout error flag, active high

Table 3: µC error register

The µC status reports can be read out at address 0x18

(see Table 4).

µC status Addr. 0x18; bit 7:0 R

Bit Description

0 µC busy indicator, active high

1 µC error indicator, active high

2 LNB/LNG error pin, active high

3-7 Reserved

Table 4: µC status register

At address 0x19 the current firmware version of the µC

can be read out.

µC firmware Addr. 0x19; bit 7:0 R

Code Chip Revision Major Modifications

0x10 iC-LNB Z1 / iC-LNG Y

0x12 iC-LNB Y1 / iC-LNG Y

0x14 iC-LNB Y1 / iC-LNG Y Bugfixes,

Implementation error

flag register

0x15 iC-LNB Y1 / iC-LNG Y Bugfixes

0x17 iC-LNB X / iC-LNG Y Bugfixes

Table 5: µC firmware versions

Besides configuring iC-LNx the I2C interface can also

be used to send special commands to the µC. The ad-

dress of this configuration register is 0x20.


Rev A2, Page 10/21

µC config Addr. 0x20; bit 7:0 RW - 0

Code Description

0x01 Copy to EEPROM

0x02 Read position data

0x04 Preset (only for iC-LNB)

Table 6: µC configuration register

Copy to EEPROM

If this bit is set , the internal µC register contents are

transmitted to the internal EEPROM. On the next µC

power-on sequence the contents of the EEPROM can

be used as a start value for iC-LNx (see Figure 8).

Read position data

The contents of the iC-LNx shift register are read out

through the SPI interface.

For iC-LNB the value is stored in the µC at addresses

0x13 to 0x15 (with the MSB or most significant bit first).

It should be noted here that the MSB of the position

data is at bit 7 in address 0x13.

Figure 9: iC-LNB position data from I2C

For iC-LNG the value is written to addresses 0x13 to

0x14 in the µC (with the MSB first). Here, the position

data MSB is also at bit 7 in address 0x13.

Figure 10: iC-LNG position data from I2C

Preset (for iC-LNB only)

This has the same function as pressing the preset

switch. The FlexCount™is set to the current position

(see Preset switch).


Rev A2, Page 11/21

ADVANCED SSI INTERFACE

SSI_SCL

DOUT_SSI

DOUT_Multiturn

MSB1 MSB-1 MSB-2 MSB - n LSB+1 LSB 1

MSB-1MSB MSB-2 MSB-3 MSB - n LSB+1 LSB MSB

SSI-Timeout

DIN/ERR

DIN/ERR

CDM

Figure 11: Position of the CDM bit

With configuration using the advanced SSI interface

the level of the SSI SCL line is evaluated during time-

out signaling (CDM or control data master bit).

This interface can be used to write data to both the

iC-LNx registers and the µC configuration register. It is

not possible to read out this written information.

Write access

The register frame starts with the addressing se-

quence. Here, the master sends the register address

(8 bits), followed by a 4-bit CRC. These are followed

by the start bit, 8 data bits, a 4-bit CRC, and a stop

bit. The 8 data and address bits are protected during

the writing of a 4-bit CRC. Correct initialization of the

data parity bit (bit 7 of each address; see the iC-LNx

datasheet) is not necessary. The µC automatically

sets this bit to the correct value before it is transmitted

to iC-LNx.

The CRC polynomial used is X4+X1+X0.

Cycle ...>=14x

Optional:multiple bytes

(S=Start, P=Stop)

CDM ADR 7..0 CRC 3..0 SS SDATA 7..0 CRC 3..0 P

Figure 12: Single byte write

Sequential register access

It is possible to write information to several consecutive

registers on one access. To this end the master sends

a new start bit immediately after the stop bit of the first

data value (CDM = 1). Internally, on each access the

slave increments the register address by 1 (autoincre-

ment). On one access all µC registers can be writ-

ten to in sequence. Sequential access with register

addresses ≥ 0x20 is not allowed. Sequential access

ends when there is no new start bit at CDM.

P S PP

End of sequence

SSCDM ADR+CRC DATA+CRC S DATA+CRC

Cycle ...

(S=Start, P=Stop)

DATA+CRC>=14x

Figure 13: Multiple byte write

CRC error detection

Should a CRC error occur in the register address or

data, the µC data and thus the iC-LNx registers remain

unaltered. A CRC error is indicated by the status LED

being set .


Rev A2, Page 12/21

ADVANCED ABZ-INTERFACE (with iC-LNB only; currently in preparation)

Using the advanced ABZ interface the µC and thus

iC-LNB can be configured after a power-on, during

which the µC controller can be notified as to the con-

tents of all writable iC-LNB registers. The ABZ inter-

face signals at A (I2C clock line) and B (I2C data line)

are evaluated or manipulated. The protocol adopted

by the master is equivalent to a standard 7-bit I2C

slave interface. The configuration must be activated

within 400 ms after power-on by the ABZ master set-

ting A = B = 1. During ABZ configuration the output

of RS422 driver iC-HD2 is switched to tristate. If

during this period the interface is activated , the I2C

start sequence must follow a maximum of 5 ms later.

The minimum clock frequency is 1 Hz and the max-

imum 50 kHz. If the minimum clock frequency is

undershot, communication is aborted and the status

LED set. Both read and write access are possible

through this interface. After each successful commu-

nication, a new communication can be implemented

within 5 ms by initiating the I2C start sequence. Fol-

lowing correct ABZ configuration the written register

contents are transferred to iC-LNB and to the internal

µC EEPROM Ist das so, oder muss man den write to

EEPROM befehl ausführen?. Wenn beim Aufstarten

die ABZ-Konfiguration von extern gestartet wird, wer-

den am Ende diese Daten automatisch ins EEPROM

des µC übernommen. Diese Art der Konfiguration

ist eigentlich, für den Betrieb ohne I2C Schnittstelle

gedacht. (PL, 26.07.2012)

Write access

The register frame starts with the addressing se-

quence. Here, the master sends the register address

(7 bits, with a value of 0), followed by a write bit and

a request for acknowledgement . These are followed

by a total of 16 data bytes with the relevant acknowl-

edgement request. The next 8 bits contain the CRC

value through the 7-bit address, the write bit, and the

16 data bytes . On correct CRC transmission the en-

suing request for acknowledgement from the master is

accepted. If the CRC is incorrect, there is no acknowl-

edgement and the status LED is set. The master then

sends the stop bit.

(S=Start, P=Stop, A=Acknowledge, W=Write, C=CRC-Check)

< 400ms

Powerup

S 7-Bit ADR; all '0' W A 8-Bit DATA A 8-Bit DATA A 8-Bit DATA

= x14< 5ms

8-Bit CRCA C P

Figure 14: Write command

Read access

Read access starts like write access, with the differ-

ence being that the write bit (with a value of 0) must be

replaced by the read bit (with a value of 1). This step

is then followed by a total of 16 register data bytes with

the relevant acknowledgement request from the µC. To

conclude the master must then send the stop bit.

(S=Start, P=Stop, A=Acknowledge, R=Read)

< 400ms

Powerup

S 7-Bit ADR; all '0' R A 8-Bit DATA A 8-Bit DATA A 8-Bit DATA

= x14< 5ms

A P

Figure 15: Read command

Sequential access

Any number of read and write accesses can follow

one another. Here, the time between the different ac-

cesses, where A = B = 1, may not exceed 5 ms. The se-

quence can be ended by A = B = 1 being greater than

5 ms (after access), by a faulty transmission (incorrect

CRC, no master acknowledgement), or by a clock fre-

quency of < 1 Hz.


Rev A2, Page 13/21

(S=Start, P=Stop, A=Acknowledge, R=Read, W=Write, C=CRC-Check)

< 400ms

Powerup

S ADR+W+A DATA+A CRC+C P S ADR+R+A DATA+A P

< 5ms > 5ms End of sequence

Figure 16: Sequential read and write commands


Rev A2, Page 14/21

DIR SWITCH (with iC-LNB only)

The position data MSB can be inverted using the DIR

switch (code inversion). To this end the microcontroller

checks the state of the DIR switch and sets the DIR

pin on iC-LNB, depending on the operating mode. The

µC decides whether the FlexCount™is active or not

(NENFLEX = 0, address 0x0B, bit 1).

If the FlexCount™is active, the FlexCount™outputs

are switched to low before pin DIR is set (NOUTLO =

0, address 0x11, bit 6) and the FlexCount™is halted

(STOPFLEX = 1, address 0x11, bit 5). After pin

DIR has been set , the FlexCount™is again enabled

(STOPFLEX = 0, address 0x11, bit 5).

Following this, the iC-LNB POSOK signal is scanned,

indicating the validity of the position (POSOK, address

0x12, bit 0). After iC-LNB has reached the current

position (POSOK = 1), the output signal is enabled

(NOUTLO = 1, address 0x11, bit 6). A failed POSOK

signal is indicated by the µC error LED being set .

If the FlexCount™ is deactivated, pin DIR is set imme-

diately.

Figure 17: State diagram: change DIR switch


Rev A2, Page 15/21

PRESET SWITCH (with iC-LNB only)

Using the preset switch it is possible to store the cur-

rent position as a zero position. To this end iC-LNB’s

FlexCount™must be active.

The preset switch used has a maximum bounce time

of 5 ms. The microcontroller thus checks the preset

switch for a change in switching state during a mini-

mum time of 8 ms.

If correct activation is recognized after this time has

elapsed, the FlexCount™is first deactivated (NEN-

FLEX = 1, address 0x0B, bit 1). After setting the sen-

sor data length to 18 bits (SRC = 000, address 0x08,

bit 2:0), the sensor data (current zero position) can

be read out through iC-LNB’s SPI interface. The Flex-

Count™outputs are then set to low (NOUTLO = 0, ad-

dress 0x11, bit 6) and the FlexCount™counter is reset

(STOPFLEX = 1, address 0x11, bit 5).

The determined Gray value of the zero position is con-

verted into binary form and written to the ZPOS reg-

ister (ZPOS, addresses 0x0C, 0x0D, 0x0E, bit 3:0).

The sensor data length is then reset, the Flex-

Count™activated (NENFLEX = 0, address 0x0B, bit 1),

and the FlexCount™reset enabled (STOPFLEX = 0,

address 0x11, bit 5).

The POSOK signal is then scanned (POSOK, address

0x12, bit 0). After iC-LNB has reached the current

position (POSOK = 1), the output signal is enabled

(NOUTLO = 1, address 0x11, bit 6). A failed POSOK

signal is indicated by the error LED being set .

Figure 18: State diagram: preset switch


Rev A2, Page 16/21

MICROCONTROLLER RESET SWITCH

By activating the RESET switch on evaluation board

LN1A the microcontroller is reset and subsequently

restarts. This switch should be activated if an error

occurs (the error LED is illuminated). The switch used

has a maximum bounce time of 5 ms. The signal is not

filtered if there is a change of state.

LED STATUS DISPLAYS

The iC-LN1A demo board has two status displays:

• The green light indicates that the microcontroller is

busy. This LED is lit after power-up and initialization

of iC-LNx.

• The red light signals an error (for example, no iC-

LNx is connected up or there is an error in the

communication interfaces). This LED can only be

switched off by the microcontroller being reset.

The iC-LNx error message can be picked up by the µC

status register being read out (I2C address 0x18, bit 2).


Rev A2, Page 17/21

TASK AND EVENT ADMINISTRATION

Task administration

To ensure that µC tasks are processed according to

priority, the individual tasks have been collated as

groups of tasks. These tasks are prioritized so that the

most important tasks are handled first. For this pur-

pose each task has its own counter and a maximum

count. The higher the maximum count, the less impor-

tant the task. If enabled, the maximum task count is

incremented by one by an interrupt every millisecond.

If the maximum count has been reached, the task is

processed in the main loop. During task processing

the task’s counter and its status flag are reset. In part,

the task enable is also deleted. So that all task coun-

ters do not always have to be incremented, the task is

enabled depending on the state of iC-LNx.

Task Enable with:

New data for iC-LNx Write access through the I2C interface

Read iC-LNx position data Microcontroller configuration command through I2C

Check preset pin state, read iC-LNB status register In iC-LNB Flexcount mode ((bit NENFLEX = 0) and

(preset switch or software preset))

Check DIR pin state Always

Check iC-LNB POSOK bit With a change in state at the preset (switch/GUI

software) or DIR (switch, bit)

Write iC-LNx configuration to EEPROM After correct advanced ABZ configuration or on mi-

crocontroller configuration command

State of I2C stop bit After each I2C communication

Table 7: Task processing

As already mentioned, the tasks are prioritized in mul-

tiples of the 1 ms timer interrupt. If enabled, the indi-

vidual tasks are processed at the following intervals:

Task Description Task processing

Task0 New iC-LNx data Every 2 ms

Task1 Read out iC-LNx position data Every 3 ms

Task2 Scan preset pin Every 8 ms

Task3 Scan DIR pin, scan iC-LNB status register Every 9 ms

Task4 Scan iC-LNB POSOK status Every 1 ms

Task5 Write iC-LNx configuration register to the

EEPROM

Every 255 ms

Task6 Check state of the I2C stop bit, µC and iC-LNx Every 1 ms

Table 8: Task prioritizing

Event administration

The advanced SSI interface is a special case where

the minimum wait period of 1 ms between two tasks

being processed would result in faulty communication.

This procedure is thus processed as an event. Here,

each time an SSI timeout occurs an event is initiated in

the interrupt routine. This event then controls the ad-

vanced SSI state machine in the main loop. The event

flag in this machine is again reset.


Rev A2, Page 18/21

APPLICATION SOFTWARE

iC-LNG software for PCs running on Windows operating systems, as well as the required USB and/or LPT driver

are available as a ZIP file. iC-Haus software built with LabVIEW™requires the installation of the LabVIEW™Run-

Time Engine (RTE). The RTE must be installed only once, hence there are two download links available.

Software overview online: http://www.ichaus.de/software

Download package without RTE (small size) including RTE (big size)

iC-LNG: http://www.ichaus.de/LNG_gui http://www.ichaus.de/LNG_gui_rte

Features

• Reducing evaluation and design-in time and cost

• Manually setting up parameters of iC-LNG

• Saving parameter configuration into ROM

• Saving parameter configuration to Hex files

• Loading predefined configurations from Hex files

• Reading and displaying of sensor data

Installation

After unzipping the iC-LNG software package LNG1SO_gui_xx resp. LNG1SO_gui_xxrte, the following files are

located in the selected working directory.

xx is a placeholder for revisions

→ Subfolder LNG1SO_gui_xx including the executable setup.exe which starts the installation routine.

→ Driver packages for USB, LPT and/or other adapter devices.

→ Evaluation board description.

Note: Administrator rights are required to run installations.

1. To access the iC-LNG evaluation board, interface adapter drivers for USB, LPT and/or other adapter devices

need to be installed. Before connecting the adapter to your PC the driver installation must be completed suc-

cessfully.

→ Execute the USB_xx.exe and/or LPT_xx.exe installation package and follow the on-screen instructions. This

can take a few minutes.

1.1 When using an iC-Haus USB adapter, it must to be connected to the PC after the driver installation, to

complete the whole driver installation procedure.

2. Install the evaluation software LNG1SO by executing the setup.exe located in the subfolder LNG1SO_gui_xx.

→ Follow the on-screen instructions to finish the installation.

3. After installation the executable LNG1SO_gui_xx.exe will be available in the selected working directory. Figure

19 shows a screenshot of the evaluation software.

LabView™is a trademark of National Instruments.

http://www.ichaus.de/software

http://www.ichaus.de/LNG_gui

http://www.ichaus.de/LNG_gui_rte


Rev A2, Page 19/21

Figure 19: Evaluation software start-up window

Function Description

The iC-LNG software starts in No Hardware mode. For a detailed description of the parameter settings please

refer to iC-LNG’s Data Sheet. When moving the mouse cursor to a parameter input box, a tool tip is displayed

identifying the corresponding parameter name as described in the specification.

The evaluation software is divided into five sections.

• Menu

• Header

• Sensor

• Parameter

• Status


Rev A2, Page 20/21

1 Menu Section

Button Description

<File> Save Config File Saves the configuration to a file, Intel Hex file format (*.hex)

Load Config File Loads the configuration to the IC, Intel Hex file format (*.hex)

Exit Quits the software

<Interface> No Hardware Switches to No Hardware mode to reset the communication between

the PC and the adapter

iC-Interface↔ USB (MB3U) for use with PC-USB adapter MB3U-I2C

<Interface Options> Connect & Reset - (enabled) connects the PC adapter and resets

the µC, (disabled) only connects the PC adapter without resetting

the µC

Connect & Read - (enabled) connects the PC adapter and reads the

iC/µC RAM content, (disabled) only connects the PC adapter without

reading the iC/µC RAM

<Extras> Parameter Search Enables a search field. The search string must be the exact param-

eter name (not case sensitive)

Generate Report To help the software support team with a detailed error description

this function generates a zip container file with all needed screen-

shots and configuration files.

About Additional software information

2 Header Section Project title, software version and connection state

3 Sensor Section Reading and displaying of sensor data

4 Parameter Section Reading and writing Parameter configuration

5 Status Section Displaying feedback of user interaction

For parameter settings, please refer to iC-LNG data sheet for a detailed description.


Rev A2, Page 21/21

RELATED PRODUCTS AND DOCUMENTATION

Item Description Documentation and

Information

iC-LNG oBGA LNB2C-xR 16-Bit Optical Encoder with SPI and

Serial/Parallel Outputs

http://www.ichaus.de/

product/iC-LNG

LNG1S 42-1024 Code disc suitable for iC-LNG equipped with

reticle LNG1R (iC-LNG oBGA LNB2C-1R)

iC-LNG EVAL LNG2M-xR iC-LNG Eval Kit (including iC-LNG, LED, code disc)

iC-LNG EVAL LN1A Microcontroller Board suitable for LNG2M

iC-SN85 BLCC SN1C High-Quality Encoder IR LED, 850 nm,

with lens, SMT

http://www.ichaus.de/

product/iC-SN85

iC-MB3 iCSY MB3U-I2C BiSS/SSI and I2C-to-PC Adapter (USB) http://www.ichaus.de/

product/MB3U-I2C

REVISION HISTORY

Rev Notes Pages affected

A1 Initial version

iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to therelevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users byemail.Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in thesematerials.The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitnessfor a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and noguarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications ofthe product.iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trademark rights of a third party resulting from processing or handling of the product and/or any other use of the product.



http://www.ichaus.de/product/iC-SN85

http://www.ichaus.de/product/iC-SN85

http://www.ichaus.de/product/MB3U-I2C

http://www.ichaus.de/product/MB3U-I2C

http://www.ichaus.com/infoletter

Documents

iC-LNG(B) EVAL LN1A · iC-LNG(B) EVAL LN1A MICROCONTROLLER BOARD DESCRIPTION Rev A2, Page 6/21 J3: µC Programmer input (Microchip PICKit3) 6-pin connector, male PIN Name Function