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RESEARCH POSTER PRESENTATION DESIGN © 2012
www.PosterPresentations.com
Implementing ultra-low power AES cryptoprocessor for
embedded systems and mobile applications.
•Secure against side channel attacks.
•No clock-related Issues.
•Robust towards PVT variations.
•Scaling down the supply voltage is not risky.
OBJECTIVE
Fully Asynchronous AES
Tools & Technology
Synopsys Tools: Design Vision & IC Compiler.
Cadence: Virtuoso.
UMC 130nm 4mm.
Faraday Standard Cells.
Fabricated Chip
1Benha Faculty of Engineering, Benha University2Center of Nanoelectronics and Devices (CND), American University in Cairo, Zewail City of Science and Technology
Eslam Yahya1,2, Nada El-Miligy1, Moustafa Amin1, and Yehea Ismail2
iCrypt – Fully Asynchronous AES Cryptoprocessor
Block Diagram
* Contacts: [email protected], [email protected]
