®

February 2011

6024 Silver Creek Valley Road, San Jose, California 95138Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.©2011 Integrated Device Technology, Inc.

IDT™ EB-LOGAN-23Evaluation Board Manual

(Evaluation Board: 18-691-001)

DISCLAIMERIntegrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed.

LIFE SUPPORT POLICYIntegrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes

EB-LOGAN-23 Evaluati

Table of Contents®

Description of the EB-LOGAN-23 Evaluation BoardIntroduction ..................................................................................................................................... 1-1Board Features ............................................................................................................................... 1-2

Hardware ................................................................................................................................ 1-2Software.................................................................................................................................. 1-2Other....................................................................................................................................... 1-2

Revision History .............................................................................................................................. 1-2

Installation of the EB-LOGAN-23 Evaluation BoardEB-LOGAN-23 Installation .............................................................................................................. 2-1PCI Express Mezzanine and Edge Adapters.................................................................................. 2-1Hardware Description ..................................................................................................................... 2-3Reference Clocks............................................................................................................................ 2-4

Global Reference Input Clocks ............................................................................................... 2-4Local Port Input Clocks........................................................................................................... 2-6

CLKMODE Selection ................................................................................................... 2-8Power Sources ....................................................................................................................... 2-9PCI Express Analog Power Voltage Regulator..................................................................... 2-10PCI Express Digital Power Voltage Converter...................................................................... 2-10PCI Express Transmitter Analog Voltage Converter ............................................................ 2-10Core Logic Voltage Converter .............................................................................................. 2-103.3V I/O Voltage Regulator................................................................................................... 2-10Power-up Sequence for PES32NT24AG2............................................................................ 2-10

Heatsink Requirement .................................................................................................................. 2-10Reset............................................................................................................................................. 2-10

Fundamental Reset ..............................................................................................................2-10Downstream Reset ...............................................................................................................2-11Stack Configuration .............................................................................................................. 2-11

Boot Configuration Vector............................................................................................................. 2-11SMBus Interfaces.......................................................................................................................... 2-12

SMBus Slave Interface ......................................................................................................... 2-12SMBus Master Interface ....................................................................................................... 2-13

JTAG Header ................................................................................................................................ 2-13Miscellaneous Jumpers, Headers................................................................................................. 2-14LEDs ............................................................................................................................................. 2-15EB-LOGAN-23 Board Figure ........................................................................................................ 2-23

Software For EB-LOGAN-23Introduction ..................................................................................................................................... 3-1Device Management Software........................................................................................................ 3-1Device Drivers................................................................................................................................. 3-1

SchematicsSchematics ..................................................................................................................................... 4-1

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EB-LOGAN-23 Evaluati

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EB-LOGAN-23 Evaluati

List of Figures®

Figure 1.1 Function Block Diagram of the EB-LOGAN-23 Evaluation Board ......................................1-1Figure 2.1 Bifurcated and Merged Mezzanine Cards ..........................................................................2-1Figure 2.2 MiniSAS Mezzanine Adapter ............................................................................................2-2Figure 2.3 EB-LOGAN-23 iSAS-to-SATA Breakout Cable ..................................................................2-2Figure 2.4 EB-LOGAN-23 iSAS-to-iSAS Cable ..................................................................................2-2Figure 2.5 PCIe x4 Edge-to-SATA Adapter ........................................................................................2-3Figure 2.6 PCIe x8 Edge-to-SAS Adapter ...........................................................................................2-3Figure 2.7 EB-LOGAN-23 Evaluation Main Board ..............................................................................2-4Figure 2.8 12-PACK PCIe Slots Breakout Board ................................................................................2-4Figure 2.9 Differential Jumper Arrangement Example ........................................................................2-5Figure 2.10 Reference Clock Configuration ..........................................................................................2-5Figure 2.11 EB32NT24AG2 Evaluation Board ....................................................................................2-23

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EB-LOGAN-23 Evaluati

Notes

on Board iv February 16, 2011

Notes

VB64H16AG2 Validatio

List of Tables®

Table 2.1 EB-LOGAN-23 Global Clock Select .................................................................................... 2-5Table 2.2 Clock Buffer Input Sources ................................................................................................. 2-6Table 2.3 Global Reference Input Clock Frequency Select ................................................................ 2-6Table 2.4 Onboard Clock Generator Frequency Select ......................................................................2-6Table 2.5 Onboard Reference Clock Generator Access Points ......................................................... 2-6Table 2.6 EB-LOGAN-23 Port (0, 2, 4, 6, 12, 20) Clock Select .......................................................... 2-7Table 2.7 EB-LOGAN-23 Port 8 Clock Source Select ........................................................................ 2-7Table 2.8 EB-LOGAN-23 Port 16 Clock Source Select ......................................................................2-7Table 2.9 EB-LOGAN-23 Slot Clock Select ........................................................................................ 2-8Table 2.10 CLKMODE Selection for the PES32NT24AG2 ................................................................... 2-9Table 2.11 EPS12V 24-pin Power Connector - J69 ............................................................................. 2-9Table 2.12 EPS12V 8-Pin Connector - J68 .......................................................................................... 2-9Table 2.13 Ports in Each Stack .......................................................................................................... 2-11Table 2.14 Boot Configuration Vector Signals .................................................................................... 2-11Table 2.15 Boot Configuration Vector Switch SW10 .......................................................................... 2-12Table 2.16 Slave SMBus Interface Connector .................................................................................... 2-12Table 2.17 SMBus Slave Interface Address Configuration ................................................................. 2-13Table 2.18 JTAG Connector Pin Out .................................................................................................. 2-13Table 2.19 Miscellaneous Jumpers, Headers ..................................................................................... 2-14Table 2.20 LED Indicators .................................................................................................................. 2-15

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89EB-LOGAN-23 Evaluation Board 1 - 1 Febru

®

Chapter 1

Description of the EB-LOGAN-23Evaluation Board

IntroductionThe 89H32NT24AG2 switch (also referred to as PES32NT24AG2 in this manual) is a member of the IDT

PCI Express® Inter-Domain Switch family of products. It is a PCIe® Base Specification 2.1 compliant(Gen2) 32-lane, 24-port switch. The EB-LOGAN-23 Evaluation Board provides an evaluation platform forboth the PES32NT24AG2 and PES32NT24BG2 switches and for several other members of this switchfamily including PES24NT24AG2, PES32NT8AG2, and PES24NT6AG2 .

Detailed information related to configuration of number of ports and lanes in the switch device can befound in the Device User Manual and the Device Data Sheet. The evaluation board, along with additionaladapters and daughter boards provide by IDT, can be configured to test every possible combination of thenumber of lanes and ports offered by the switch. Advanced capabilities such as switch partitioning, NTB,DMA, and local port clocking can be evaluated with the evaluation board.

The EB-LOGAN-23 brings out all 32 lanes of the device to 4 Mezzanine connectors (see Figure 1.1)located close to the device — one connector per stack of 8 lanes. Various types of daughter cards (providedby IDT) can then be plugged into these connectors to facilitate connectivity to one x8 or two x4 or four x2 oreight x1 link partners. Link partners may be plugged directly into these daughter cards, or they can beconnected to these daughter cards via SAS or SATA cables and a different board with PCIe slots known asthe 12-PACK board (provided by IDT). Given that the majority of the hosts/servers offer PCIe standardslots, IDT provides the necessary adapter cards that may be plugged into these host/server slots as well asthe cables that connect such adapters to the daughter cards, which in turn are plugged into the main evalu-ation board on which the IDT PCIe switch device is populated.

The EB-LOGAN-23 is also used by IDT to reproduce system-level hardware or software issues reportedby customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EB-LOGAN-23 board.

Figure 1.1 Function Block Diagram of the EB-LOGAN-23 Evaluation Board

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Board Features

Hardware32NT24AG2 PCIe 24-port switch

– Twenty four ports (8 x2 and 16 x1) — adjacent ports may be combined to create x4 or x8 ports– PCIe Base Specification Revision 2.1 compliant (Gen2 SerDes speeds of 5 GT/S)– Up to 2048 byte maximum Payload Size– Automatic lane reversal and polarity inversion supported on all lanes– Automatic per port link width negotiation to x8, x4, x2, x1– Power on reconfiguration via optional serial EEPROM connected to the SMBUS Master interfaceUpstream, Downstream Ports

– The EB-LOGAN-23 has a minimum of one port configured as an upstream port to be plugged intoa host slot through an adaptor and a cable.

– Up to 23 ports can be configured as downstream ports, for PCIe endpoint add-on cards to beplugged in. The slot connectors can be configured to be x1, x2, x4, or x8, but are mechanicallyopen-ended on one side to allow card widths greater than x8 (e.g. x16) to be populated.

– When used in multi-partition mode, the device can be programmed through the serial EEPROMto generate the appropriate number of upstream and downstream ports per partition.

Numerous user selectable configurations set using onboard jumpers and DIP-switches– Source of clock - host clock or onboard clock generator– Two clock rates (100/125 MHz) from an onboard clock generator– Flexible clocking modes

• Common clock• Non-common clock• Local port clocking on ports that support this feature

– Boot mode selectionSMBUS Slave Interface (4 pin header)SMBUS Master Interface connected to the Serial EEPROMs and I/O ExpandersPush button for Warm Reset Many LEDs to display status, reset, power, hot-plug, etc.JTAG connector to the 32NT24AG2 JTAG pins.

SoftwareThere is no software or firmware executed on the board. However, useful software is provided along

with the Evaluation Board to facilitate configuration and evaluation of the 32NT24AG2 within host systemsrunning popular operating systems.

Installation programs– Operating Systems Supported: WindowsServer200x, WindowsXP, Vista, LinuxGUI based application for Windows and Linux

– Allows users to view and modify registers in the 32NT24AG2– Binary file generator for programming the serial EEPROMs attached to the SMBUS.

OtherSMBUS cable/dongle may be required for certain evaluation exercises.SMA/SATA connectors are provided on the EB-LOGAN-23 board for clock outputs.

Revision HistoryMarch 15, 2010: Initial publication of evaluation board manual.April 23, 2010: Updated Schematics in Chapter 4.

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August 11, 2010: Updated the manual for Rev. 2.0 board.February 16, 2011: Changed default settings from Off to On in Tables 2.3 and 2.4.

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IDT Description of the EB-LOGAN-23 Evaluation Board

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89EB-LOGAN-23 Evaluation Board 2 - 1 Febru

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Chapter 2

Installation of the EB-LOGAN-23Evaluation Board

EB-LOGAN-23 InstallationThis chapter discusses the steps required to configure and install the EB-LOGAN-23 evaluation board.

All available DIP switches and jumper configurations are explained in detail. The primary installation steps are:

1. Configure jumper/switch options suitable for the evaluation or application requirements.2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the daughter cards

plugged into the evaluation board. Daughter cards are provided by IDT. In some cases the 12-PACKboard will be required as well (specifically when more ports than those supported by the main boardare required).

3. Make sure that the host system (e.g. server with root complex chipset) is powered off.4. Connect the evaluation board to the host system via the adapter card and cable provided by IDT.5. Apply power to the host system and to the IDT board.The EB-LOGAN-23 board is typically shipped with all jumpers and switches configured to their default

settings which will satisfy the initial needs of the majority of the users. In most cases, the board does notrequire further modification or setup. However, please visit the IDT website and fill out the TechnicalSupport Request form at http://www.idt.com/?app=TechSupport for other configurations.

PCI Express Mezzanine and Edge AdaptersThe PCI Express lanes are broken out to four Mezzanine connectors on the EB-LOGAN-23 Evaluation

Board. The adapter cards are used to convert Mezzanine connectors into PCI Express slot connector(s) orInternal mini SAS (iSAS) connectors or both. A Bifurcated Mezzanine Card has two mechanical x8 PCIeSlots (x4 electrically) while a Merged Mezzanine Card has single x8 PCIe Slot. Pictured in Figure 2.1.

Figure 2.1 Bifurcated and Merged Mezzanine Cards

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Pictured in Figure 2.2 is the mini-SAS Mezzanine card which consists of two iSAS and two SATAconnectors. Each iSAS connector supports up to two PCI Express x4 width and the SATA connectors areused for clock and reset signals of each x4 or less stack/port. An iSAS-to-SATA breakout cable shown inFigure 2.3 is used connect from iSAS to edge adapter and/or 12PACK. An iSAS-to-iSAS cable shown inFigure 2.4 is used to connect from iSAS to x8 edge adapter.

Figure 2.2 MiniSAS Mezzanine Adapter

Figure 2.3 EB-LOGAN-23 iSAS-to-SATA Breakout Cable

Figure 2.4 EB-LOGAN-23 iSAS-to-iSAS Cable

The PCI Express Edge to SATA Adapter, pictured in Figure 2.5 and Figure 2.6, can be inserted into anyphysical PCIe slot on a host system and in combination with mini-SAS Mezzanine Card, such as the one inFigure 2.2, to form a link between evaluation main board and the host system. There are 5 SATA connec-

SAS (x4) – four SATA (x1) breakout cable

SAS (x4) – four SATA (x1) breakout cable

SAS (x4) –SAS (x4) cableSAS (x4) –SAS (x4) cable

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IDT Installation of the EB-LOGAN-23 Evaluation Board

89EB-LOGAN-23 Evalu

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tors: one connector is for clock and reset, and the remainder support one PICe lane per SATA connector.The PCI Express Edge to SAS Adapter shown in Figure 2.6 is similar to the SATA adapter in that it supportsup to a x8 width using two SAS cables. The edge adapters can be inserted into a mechanical x4/x8 orgreater slot and supports x1, x2, x4, and x8 widths.

Figure 2.5 PCIe x4 Edge-to-SATA Adapter

Figure 2.6 PCIe x8 Edge-to-SAS Adapter

Hardware DescriptionThe PES32NT24AG2 is a 32-lane, 24-port PCI Express® switch. It is a peripheral chip that performs

PCI Express based switching with a feature set optimized for high performance applications such asservers and storage. It provides fan-out and switching functions between a PCI Express upstream port anddownstream ports or peer-to-peer switching between downstream ports. Furthermore, up to eight ports canbe configured as NTB ports for multi-root applications. The device offers additional features such as DMAand local port clocking support (a feature required for enabling multiple spread spectrum clocks in thesystem).

The EB-LOGAN-23 Main Board, shown in Figure 2.7, supports up to 6 PCI Express downstream portsand up to 23 ports when using two 12-PACK Boards.

Basic requirements for the board function are:– Host system with a PCI Express root complex supporting x8 configuration through a PCI Express

x8 slot. (If your host system does not offer a x8 slot, please contact ssdhelp@idt.com for alterna-tive solutions.)

– – x1, x2, x4, or x8 PCI Express Endpoint Cards.

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Figure 2.7 EB-LOGAN-23 Evaluation Main Board

Figure 2.8 12-PACK PCIe Slots Breakout Board

Reference Clocks

Global Reference Input ClocksThe PES32NT24AG2 requires two differential reference clocks. The EB-LOGAN-23 derives these

clocks from SMA connectors (J17/J20, J66/J67), clock buffer (U51) with on board clock generator (U49),SMA (J5/J7) or SATA (J8) connectors via jumpers (J6) as described in Table 2.2, or SATA connectors (J21,J22) as described in Table 2.1 and Figures 2.9 and 2.10. Both reference clocks are mandatory and mustcome from the same reference clock source. The switch will not function normally if only one clock is used.

Mezz to two x4 slot connectors

Mezz to one x8 slot connectorsDUT on bottom side

Mezzanine to two x4 slot connectors

Mezzanine to two x4 slot connectors

Mezzanineto one x8 slot connectorsDUT on bottom side

Mezzanine to two x4 iSA connectors

Mezzanine to two x4 iSA connectors

On-BoardClock Gen

1:12Buffer

SATA

SMA

clk[0:11]

8-PIN EPS12V24-PIN ATX

+12+3.3 +12

SLOT

11

x2 Data

SATA

CLK

SATA

SATA

SLOT

10

x4 Data

SATA

CLK

SATA

SATA

SATA

SATA

SLOT

9

x2 Data

SATA

CLK

SATA

SATA

SLOT

8

x8 Data

SATA

CLK

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SLOT

7

x2 Data

SATA

CLK

SATA

SATA

SLOT

6

x4 Data

SATA

CLK

SATA

SATA

SATA

SATA

SLOT

5

x2 Data

SATA

CLK

SATA

SATA

SLOT

4

x8 Data

SATA

CLK

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SLOT

3

x2 Data

SATA

CLK

SATA

SATA

SLOT

2

x4 Data

SATA

CLK

SATA

SATA

SATA

SATA

SLOT

1

x2 Data

SATA

CLK

SATA

SATA

SLOT

0

x8 Data

SATA

CLK

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

On-BoardClock Gen

1:12Buffer

SATA

SMASMA

clk[0:11]

8-PIN EPS12V24-PIN ATX

+12+3.3 +12

SLOT

11

x2 Data

SATA

CLK

SATA

SATA

SLOT

10

x4 Data

SATA

CLK

SATA

SATA

SATA

SATA

SLOT

9

x2 Data

SATA

CLK

SATA

SATA

SLOT

8

x8 Data

SATA

CLK

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SLOT

7

x2 Data

SATA

CLK

SATA

SATA

SLOT

6

x4 Data

SATA

CLK

SATA

SATA

SATA

SATA

SLOT

5

x2 Data

SATA

CLK

SATA

SATA

SLOT

4

x8 Data

SATA

CLK

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SLOT

3

x2 Data

SATA

CLK

SATA

SATA

SLOT

2

x4 Data

SATA

CLK

SATA

SATA

SATA

SATA

SLOT

1

x2 Data

SATA

CLK

SATA

SATA

SLOT

0

x8 Data

SATA

CLK

SATA

SATA

SATA

SATA

SATA

SATA

SATA

SATA

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Figure 2.9 Differential Jumper Arrangement Example

Figure 2.10 Reference Clock Configuration

By default, the clock buffer derives its clock from a common source. The common source can be thehost system reference clock via a SATA connector, the onboard clock generator, or SMA connectors. SeeTable 2.2.

Global Clock# Jumper Selection

GCLK0 J18 [1-3 / 2-4] SMA (J66/J67)[5-7 /6-8] From Clock Buffer U51 (default)[7-9 / 8-10] SATA, J21

GCLK1 J19 [1-3 / 2-4] SMA (J17/J20)[5-7 /6-8] From Clock Buffer U51 (default)[7-9 / 8-10] SATA, J22

Table 2.1 EB-LOGAN-23 Global Clock Select

1

3

5

7

9

2

4

6

8

10

IOAIOB

IOC

COM

1

3

5

7

9

2

4

6

8

10

IOAIOB

IOC

COM

10-139-11IOD <-> COM8-107-9IOC <-> COM4-63-5IOB <-> COM2-41-3IOA <-> COMJMP2JMP1CONNECTION

10-139-11IOD <-> COM8-107-9IOC <-> COM4-63-5IOB <-> COM2-41-3IOA <-> COMJMP2JMP1CONNECTION

On-BoardClock Gen

DUT

gclk0

Slot/PC 02

sata

sata

gclkNgclkN

sata

sata

gclkNgclkN

Slot/PC 46

sata

sata

gclkNgclkN

sata

sata

gclkNgclkN

Slot/PC 0812

satasata

gclkNgclkN

satasata

gclkNgclkN

Slot/PC 1620

satasata

gclkNgclkN

satasata

gclkNgckN

sata

gck1

sma

sata

sma

sata

sma

gck0

gclk1

1:12 Buffer

gclk0

gclk1

gclk[2:11]

sata

sma

1:12On-BoardClock Gen

DUT

gclk0

Slot/PC 02

sata

sata

gclkNgclkN

sata

sata

gclkNgclkN

Slot/PC 46

sata

sata

gclkNgclkN

sata

sata

gclkNgclkN

Slot/PC 0812

satasata

gclkNgclkN

satasata

gclkNgclkN

Slot/PC 1620

satasata

gclkNgclkN

satasata

gclkNgckN

sata

gck1

sma

sata

smasma

sata

smasma

gck0

gclk1

1:12 Buffer

gclk0

gclk1

gclk[2:11]

sata

sma

1:12

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.

The frequency of the global reference clock input may be either 100 MHz or 125 MHz, as shown in Table2.3, and is selected by the Clock Frequency Select (GCLKFEL) pin.

The source for the onboard clock is the ICS841484 clock generator device (U49) connected to a 25MHzoscillator (X1). When using the onboard clock generator, the output frequency can be selected usingICS_FS (SW10, bit 1). The default setting is ON. See Table 2.4.

The output of the onboard clock generator is accessible through SMA or SATA connectors. See Table2.5. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive theclock from an external source.

Local Port Input ClocksAssociated with some ports is a local port reference clock input (PxCLK). Depending on the port

clocking mode, a differential reference clock can be driven into the device on the corresponding PxCLKPand PxCLKN pins. The frequency of a port reference clock input MUST always at 100 MHz. Table 2.6 liststhe possible sources for the port reference clock input, and Table 2.9 lists the possible sources for the slotclock input. Additional information on port clocking usage and configuration can be found in the Device UserManuals and in IDT’s Application Note AN-715.

Jumper Selection

J6 [1-3 / 2-4] SMA (J5/J7) [5-7 / 6-8] Onboard Clock Generator (U49)[7-9 / 8-10] SATA (J8) (default)

Table 2.2 Clock Buffer Input Sources

Global Clock Frequency Switch - SW10[2]

SW10[2] Clock Frequency

ON 100 MHz (Default)

OFF 125 MHz

Table 2.3 Global Reference Input Clock Frequency Select

Onboard Clock Frequency Switch - SW10[1]

SW10[1] Clock Frequency

ON 100 MHz (Default)

OFF 125 MHz

Table 2.4 Onboard Clock Generator Frequency Select

Onboard Reference Clock Output (Differential)

TP119 Positive Reference Clock (SMA)

TP120 Negative Reference Clock (SMA)

J121 Differential Reference Clock (SATA)

Table 2.5 Onboard Reference Clock Generator Access Points

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Local port clock sources for ports 8 and 16 are selected by DIP switch (S17 and S19) via a clock mux/buffer. See Tables 2.7 and 2.8.

Port # Header Selection

0 J9 [1-3 / 2-4] Onboard Clock Generator (U116)[3-5 / 4-6] SATA (J58)

2 J10 [1-3 / 2-4] Onboard Clock Generator (U122)[3-5 / 4-6] SATA (J59)

4 J11 [1-3 / 2-4] Onboard Clock Generator (U123)[3-5 / 4-6] SATA (J60)

6 J12 [1-3 / 2-4] Onboard Clock Generator (U117)[3-5 / 4-6] SATA (J61)

12 J14 [1-3 / 2-4] Onboard Clock Generator (U119)[3-5 / 4-6] SATA (J63)

20 J16 [1-3 / 2-4] Onboard Clock Generator (U121)[3-5 / 4-6] SATA (J65)

Table 2.6 EB-LOGAN-23 Port (0, 2, 4, 6, 12, 20) Clock Select

Port 8 Clock Source Select - S19[1]

S19[1] Clock Source

OFF SATA J62

ON Port 8 Clock Generator (U118)

Table 2.7 EB-LOGAN-23 Port 8 Clock Source Select

Port 16 Clock Source Select - S17[1]

S17[1] Clock Source

OFF SATA J64

ON Port 16 Clock Generator (U120)

Table 2.8 EB-LOGAN-23 Port 16 Clock Source Select

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CLKMODE SelectionAll ports in the PES32NT24AG2 device (upstream and downstream) use global clocked mode by

default. The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the bootconfiguration vector as shown in Table 2.10. This field determines the initial value of the Slot Clock Configu-ration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls theadvertisement of whether or not the port uses the same reference clock source as the link partner. A one inthe SCLK field indicates that the port and its link partner use the same reference clock source. This isdefined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK fieldindicates that the port and its link partner do not use the same reference clock source.

Slot # Jumper Selection

0 J23 [1-3 / 2-4] Onboard Clock Generator (U115)[3-5 / 4-6] Clock Buffer (U51)[7-9 / 8-10] P08CLK Clock Mux (U18)[9-11 / 10-12] SATA (J27)

2 J24 [1-3 / 2-4] Onboard Clock Generator (U122)[3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P08CLK Clock Mux (U18)[9-11 / 10-12] SATA (J28)

4 J25 [1-3 / 2-4] Onboard Clock Generator (U123)[3-5 / 4-6] Clock Buffer (U51)[7-9 / 8-10] P08CLK Clock Mux (U18)[9-11 / 10-12] SATA (J29)

6 J26 [1-3 / 2-4] Onboard Clock Generator (U117)[3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P16CLK Clock Mux (U16)[9-11 / 10-12] SATA (J30)

8 J31 [1-3 / 2-4] Onboard Clock Generator (U118)[3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P16CLK Clock Mux (U16)[9-11 / 10-12] SATA (J31)

12 J32 [1-3 / 2-4] Onboard Clock Generator (U119)[3-5 / 4-6] Clock Buffer (U51)[7-9 / 8-10] P16CLK Clock Mux (U16)[9-11 / 10-12] SATA (J32)

16 J33 [1-3 / 2-4] Onboard Clock Generator (U120)[3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P08CLK Clock Mux (U18)[9-11 / 10-12] SATA (J33)

20 J34 [1-3 / 2-4] Onboard Clock Generator (U121)[3-5 / 4-6] Clock Buffer (U51)[7-9 / 8-10] P16CLK Clock Mux (U16)[9-11 / 10-12] SATA (J34)

Table 2.9 EB-LOGAN-23 Slot Clock Select

ation Board 2 - 8 February 16, 2011

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Notes

Power SourcesPower for the PES32NT24AG2 and all downstream ports is generated from a 12V supply via an external

power connector. See Table 2.11. A 12V to 3.3V DC-DC converter is used to provide power to five switchingregulators to generate VDDCORE, VDDPEA, VDDPETA, VDDPEHA, and VDDIO voltages. The 3.3V from theDC-DC converter will be used to power the clock buffers and circuitries.

The external power supply connectors are 24-pin (J69) and 8-pin (J68) molex connectors as describedin Tables 2.11 and 2.12. The +12V3 is used to power the PES32NT24AG2 and downstream slots 0, 2, 16,and 20. The +12V2 is used to power downstream slots 4, 6, 8, and 12.

SW10[8]CLKMODE[0]

SW10[7]CLKMODE[1]

Port 0 SCLK

Port[15:1] SCLK

ON ON 0 0

OFF ON 1 0

ON OFF 0 1

OFF OFF 1 1

Table 2.10 CLKMODE Selection for the PES32NT24AG2

Pin Signal Pin Signal

1 +3.3V 13 +3.3V

2 +3.3V 14 -12V

3 GND 15 GND

4 +5V 16 PS_ON

5 GND 17 GND

6 +5V 18 GND

7 GND 19 GND

8 PWR_OK 20 NC

9 5VSB 21 +5V

10 +12V3 22 +5V

11 +12V3 23 +5V

12 +3.3V 24 GND

Table 2.11 EPS12V 24-pin Power Connector - J69

Pin Signal Pin Signal

1 GND 5 +12V1

2 GND 6 +12V1

3 GND 7 +12V2

4 GND 8 +12V2

Table 2.12 EPS12V 8-Pin Connector - J68

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Notes

The power switch located at S1 can be used to control the supply power from the external power supplyconnector. Add a shunt to W27 to enable power on switch.

PCI Express Analog Power Voltage RegulatorA voltage regulator (U65) provides a 2.5V PCI Express analog power voltage (shown as VDDPEHA) to

the PES32NT24AG2.

PCI Express Digital Power Voltage ConverterA separate voltage regulator (U62) provides a 1.0V PCI Express analog power voltage (shown as

VDDPEA) to the PES32NT24AG2.

PCI Express Transmitter Analog Voltage ConverterA separate voltage regulator (U68) provides a 1.0V PCI Express transmitter analog voltage (shown as

VDDPETA) to the PES32NT24AG2.

Core Logic Voltage ConverterA separate voltage regulator (U59) provides the 1.0V core voltage (VDDCORE) to the PES32NT24AG2.

3.3V I/O Voltage RegulatorA separate voltage regulator (U56) provides the 3.3V I/O voltage (VDDIO) to the PES32NT24AG2.

Power-up Sequence for PES32NT24AG2During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There

are no other power-up sequence requirements for the various operating supply voltages.

Heatsink Requirement The EB-LOGAN-23 evaluation board utilizes a heatsink with integrated fan. All initial shipments of the

board are made with the heatsink whether or not one is truly required. There may be low link usage applica-tions within which the heatsink may, in fact, not be required.

ResetThe PES32NT24AG2 supports two types of reset mechanisms as described in the PCI Express specifi-

cation:– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express

tree through a single side-band signal PERST# which is connected to the Root Complex, thePES32NT24AG2, and the endpoints.

– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device toanother. Hot Reset may be initiated by software. This is further discussed in the PES32NT24xG2User Manual. The EB-LOGAN-23 evaluation board provides seamless support for Hot Reset.

Fundamental ResetThere are two types of Fundamental Resets which may occur on the EB-LOGAN-23 evaluation board:

– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCIExpress Reset (PERSTN) input pin of the PES32NT24AG2.

– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can beinitiated by two methods: • Pressing a push-button switch (S3) located on EB-LOGAN-23 board• The host system board IO Controller Hub asserting PERST# signal, which propagates through

the PCIe upstream edge connector of the EB-LOGAN-23.Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN) input of the PES32NT24AG2 while power is on.

ation Board 2 - 10 February 16, 2011

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Notes

Downstream ResetSingle Partition Mode without Hot Plug:When the evaluation board initially powers on, it assumes the following:

The switch is configured in single partition mode. Slot 0 is the root port and controls the downstream port resets. Ports 1-23 are downstream ports. Hot Plug is disabled.

The following behavior should be observed: The resets to slots 1-23 should initially be asserted and remain this way until after the fundamental reset is initially de-asserted. The assertion of slot 0 reset should propagate to slots 1-23.

Stack ConfigurationThe PES32NT24AG2 contains four stack blocks labeled Stack 0, Stack 1, Stack 2, and Stack 3. Stacks

0 and 1 have four x2 ports each, and stacks 2 and 3 have eight x1 ports each. This provides a total of 24ports in the device labeled port 0 through port 23. Table 2.13 lists the ports associated with each stack.

Boot Configuration VectorA boot configuration vector consisting of the signals listed in Table 2.14 is sampled by the

PES32NT24AG2 during a fundamental reset (while PERSTN is active). The boot configuration vectordefines the essential parameters for switch operation and is set using DIP switches S5, SW8, SW9, andSW10 as defined in Table 2.15.

Stack Ports Associated with the Stack

Stack 0 0, 1, 2, 3

Stack 1 4, 5, 6, 7

Stack 2 8, 9, 10, 11, 12, 13, 14, 15

Stack 3 16, 17, 18, 19, 20, 21, 22, 23

Table 2.13 Ports in Each Stack

Signal Description

GCLKFSEL Global Clock Frequency Select. This pin specifies the frequency of the GCLKP and GCLKN signals. Default: low

CLKMODE[1:0] Clock Mode. These pins specify the clocking mode used by switch ports. SeeTable 2.10 for a definition of the encoding of these signals. The value of these signals may be overridden by modifying the Port Clocking Mode (PCLKMODE) register.

RSTHALT Reset Halt. When this pin is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the quasi-reset state when the RSTHALTbit is cleared in the SWCTL register by an SMBus master. Refer to section Switch Funda-mental Reset on page 3-2 for further details. Default: low

SSMBADDR[2:1] Slave SMBus Address. SMBus address of the switch on the slave SMBus. Default: 0x3

Table 2.14 Boot Configuration Vector Signals (Part 1 of 2)

ation Board 2 - 11 February 16, 2011

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Notes

SMBus InterfacesThe System Management Bus (SMBus) is a two-wire interface through which various system compo-

nent chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBussignals in the PCI Express connector is optional and may not be present on the host system. The SMBusinterface consists of an SMBus clock pin and an SMBus data pin.

The PES32NT24AG2 contains two SMBus interfaces: a slave SMBus interface and a master SMBusinterface. The slave SMBus interface allows a SMBus Master device full access to all software-visible regis-ters. The Master SMBus interface provides a connection to the external serial EEPROM used for initializa-tion and the I/O expanders used for hot-plug signals.

SMBus Slave InterfaceOn the PES32NT24AG2 board, the slave SMBus interface is accessible through a 4-pin header as

described in Table 2.16. .

SWMODE[3:0] Switch Mode. These pins specify the switch operating mode.

STK0CFG[1:0] Stack 0 Configuration. These pins select the configuration of stack 0 during a switch fun-damental reset.

STK1CFG[1:0] Stack 1 Configuration. These pins select the configuration of stack 1 during a switch fun-damental reset.

STK2CFG[4:0] Stack 2 Configuration. These pins select the configuration of stack 2 during a switch fun-damental reset.

STK3CFG[4:0] Stack 3 Configuration. These pins select the configuration of stack 3 during a switch fun-damental reset.

Location Signal Default

SW10[2] GCLKFSEL ON

SW10[4] RSTHALT ON

SW10[5] SSMBADDR[2] OFF

SW10[6] SSMBADDR[1] OFF

Table 2.15 Boot Configuration Vector Switch SW10

Slave SMBus Interface Connector J71

Pin Signal

1 SDA

2 GND

3 SCL

4 NC

Table 2.16 Slave SMBus Interface Connector

Signal Description

Table 2.14 Boot Configuration Vector Signals (Part 2 of 2)

ation Board 2 - 12 February 16, 2011

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Notes

For a fixed address, the SMBus address of the PES32NT24AG2 slave interface is 0b1110111 by defaultand is configurable using DIP Switches SW10[5] and SW10[6] as described in Table 2.17.

The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.Initiation of any SMBus transaction other than those listed above produces undefined results. See theSMBus 2.0 specification for a detailed description of the following transactions:

– Byte and Word Write/Read– Block Write/Read

SMBus Master InterfaceConnected to the master SMBus interface are twenty-two 16-bit I/O Expanders (MAX7311AUG) and a

serial EEPROM, U77 (24LC512). The I/O Expanders are used as the interface for the onboard hot-plugcontrollers (MIC2591B). The lower three bits of the bus address for the I/O Expander 0 through 20 are fixedthrough the stuffing resistor as 0x20, 0x22, 0x24, 0x26, 0x28, 0x2A, 0x2C, 0x2E, 0x50, 0x52, x54, 0x56,0x58, 0x5A, 0x5C, 0x5E, 0xB0, 0xA2, 0xA4, 0xA6, 0xA8, and 0xAA, respectively.

Note: Hot-plug is not implemented when the PES32NT24AG2 is installed.The seven bits address for the selected EEPROM device is fixed at 0b1010_000 by default.

JTAG HeaderThe PES32NT24AG2 provides a JTAG connector J73 for access to the PES32NT24AG2 JTAG inter-

face. The connector is a 2.54 x 2.54 mm pitch male 14-pin connector. Refer to Table 2.18 for the JTAGConnector J73 pin out.

Slave Interface Address Configuration

Address Bit Signal

1 SSMBUSADDR[1]

2 SSMBUSADDR[2]

3 1

4 0

5 1

6 1

7 1

Table 2.17 SMBus Slave Interface Address Configuration

JTAG Connector J5

Pin Signal Direction Pin Signal Direction

1 /TRST - Test reset Input 2 GND —

3 TDI - Test data Input 4 GND —

5 TDO - Test data Output 6 GND —

7 TMS - Test mode select Input 8 GND —

9 TCK - Test clock Input 10 GND —

11 3.3V 12 N/C —

13 GND — 14 3.3V

Table 2.18 JTAG Connector Pin Out

ation Board 2 - 13 February 16, 2011

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Miscellaneous Jumpers, Headers

Miscellaneous Jumpers, Headers

Ref. Designator Type Default Description

W1 Header 1-2 Shunted 1-2: GPIO 8 to DS414 when ALT1 (Default)2-3: GPIO 8 to IO Expander Interrupt when ALT0

W5 Header Shunted 2-3: Slot 0, 3.3Vaux source from Direct Power (Default)1-2: Slot 0, 3.3Vaux source from hot-plug controller

W6 Header 2-3 Shunted 2-3: Slot 2, 3.3Vaux source from Direct Power (Default)1-2: Slot 2, 3.3Vaux source from hot-plug controller

W11 Header 2-3 Shunted 2-3: Slot 4, 3.3Vaux source from Direct Power (Default)1-2: Slot 4, 3.3Vaux source from hot-plug controller

W12 Header 2-3 Shunted 2-3: Slot 6, 3.3Vaux source from Direct Power (Default)1-2: Slot 6, 3.3Vaux source from hot-plug controller

W17 Header 2-3 Shunted 2-3: Slot 8, 3.3Vaux source from Direct Power (Default)1-2: Slot 8, 3.3Vaux source from hot-plug controller

W18 Header 2-3 Shunted 2-3: Slot 12, 3.3Vaux source from Direct Power (Default)1-2: Slot 12, 3.3Vaux source from hot-plug controller

W23 Header 2-3 Shunted 2-3: Slot 16, 3.3Vaux source from Direct Power (Default)1-2: Slot 16, 3.3Vaux source from hot-plug controller

W24 Header 2-3 Shunted 2-3: Slot 20, 3.3Vaux source from Direct Power (Default)1-2: Slot 20, 3.3Vaux source from hot-plug controller

W4 Header 2-3 Shunted 2-3: Slot 0, +12V source from Direct Power (Default)1-2: Slot 0, +12V source from hot-plug controller

W8 Header 2-3 Shunted 2-3: Slot 2, +12V source base on W57(Default)1-2: Slot 2, +12V source from hot-plug controller

W10 Header 2-3 Shunted 2-3: Slot 4, +12V source from Direct Power (Default)1-2: Slot 4, +12V source from hot-plug controller

W14 Header 2-3 Shunted 2-3: Slot 6, +12V source from Direct Power (Default)1-2: Slot 6, +12V source from hot-plug controller

W16 Header 2-3 Shunted 2-3: Slot 8, +12V source from Direct Power (Default)1-2: Slot 8, +12V source from hot-plug controller

W20 Header 2-3 Shunted 2-3: Slot 12, +12V source from Direct Power (Default)1-2: Slot 12, +12V source from hot-plug controller

W22 Header 2-3 Shunted 2-3: Slot 16, +12V source from Direct Power (Default)1-2: Slot 16, +12V source from hot-plug controller

W26 Header 2-3 Shunted 2-3: Slot 20, +12V source from Direct Power (Default)1-2: Slot 20, +12V source from hot-plug controller

W3 Header 2-3 Shunted 2-3: Slot 0, +3.3V source from Direct Power (Default)1-2: Slot 0, +3.3V source from hot-plug controller

W7 Header 2-3 Shunted 2-3: Slot 2, +3.3V source from Direct Power (Default)1-2: Slot 2, +3.3V source from hot-plug controller

W9 Header 2-3 Shunted 2-3: Slot 4, +3.3V source from Direct Power (Default)1-2: Slot 4, +3.3V source from hot-plug controller

Table 2.19 Miscellaneous Jumpers, Headers (Part 1 of 2)

ation Board 2 - 14 February 16, 2011

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Notes

LEDsThere are many LED indicators on the EB-LOGAN-23 which convey status feedback. A description of

each is provided in Table 2.20.

W13 Header 2-3 Shunted 2-3: Slot 6, +3.3V source from Direct Power (Default)1-2: Slot 6, +3.3V source from hot-plug controller

W15 Header 2-3 Shunted 2-3: Slot 8, +3.3V source from Direct Power (Default)1-2: Slot 8, +3.3V source from hot-plug controller

W19 Header 2-3 Shunted 2-3: Slot 12, +3.3V source from Direct Power (Default)1-2: Slot 12, +3.3V source from hot-plug controller

W21 Header 2-3 Shunted 2-3: Slot 16, +3.3V source from Direct Power (Default)1-2: Slot 16, +3.3V source from hot-plug controller

W25 Header 2-3 Shunted 2-3: Slot 20, +3.3V source from Direct Power (Default)1-2: Slot 20, +3.3V source from hot-plug controller

Location Color Definition

DS1 Green Board Power Indicator (5V)

DS2 Green Board Power Indicator (3.3V)

DS4 Green VDDIO Indicator (3.3V)

DS158 Orange Port23: Attention Push Button Input

DS159 Orange Port22: Attention Push Button Input

DS160 Orange Port21: Attention Push Button Input

DS161 Orange Port20: Attention Push Button Input

DS162 Orange Port19: Attention Push Button Input

DS163 Orange Port18: Attention Push Button Input

DS164 Orange Port17: Attention Push Button Input

DS165 Orange Port16: Attention Push Button Input

DS166 Orange Port15: Attention Push Button Input

DS167 Orange Port14: Attention Push Button Input

DS168 Orange Port13: Attention Push Button Input

DS169 Orange Port12: Attention Push Button Input

DS170 Orange Port11: Attention Push Button Input

DS171 Orange Port10: Attention Push Button Input

DS172 Orange Port9: Attention Push Button Input

DS173 Orange Port8: Attention Push Button Input

Table 2.20 LED Indicators (Part 1 of 8)

Miscellaneous Jumpers, Headers

Ref. Designator Type Default Description

Table 2.19 Miscellaneous Jumpers, Headers (Part 2 of 2)

ation Board 2 - 15 February 16, 2011

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Notes

DS174 Orange Port7: Attention Push Button Input

DS175 Orange Port6: Attention Push Button Input

DS176 Orange Port5: Attention Push Button Input

DS177 Orange Port4: Attention Push Button Input

DS178 Orange Port3: Attention Push Button Input

DS179 Orange Port2: Attention Push Button Input

DS180 Orange Port1: Attention Push Button Input

DS181 Orange Port0: Attention Push Button Input

DS182 Yellow Port23: Presence Detect Input

DS183 Yellow Port22: Presence Detect Input

DS184 Yellow Port21: Presence Detect Input

DS185 Yellow Port20: Presence Detect Input

DS186 Yellow Port19: Presence Detect Input

DS187 Yellow Port18: Presence Detect Input

DS188 Yellow Port17: Presence Detect Input

DS189 Yellow Port16: Presence Detect Input

DS190 Yellow Port15: Presence Detect Input

DS191 Yellow Port14: Presence Detect Input

DS192 Yellow Port13: Presence Detect Input

DS193 Yellow Port12: Presence Detect Input

DS194 Yellow Port11: Presence Detect Input

DS195 Yellow Port10: Presence Detect Input

DS196 Yellow Port9: Presence Detect Input

DS197 Yellow Port8: Presence Detect Input

DS198 Yellow Port7: Presence Detect Input

DS199 Yellow Port6: Presence Detect Input

DS200 Yellow Port5: Presence Detect Input

DS201 Yellow Port4: Presence Detect Input

DS202 Yellow Port3: Presence Detect Input

DS203 Yellow Port2: Presence Detect Input

DS204 Yellow Port1: Presence Detect Input

DS205 Yellow Port0: Presence Detect Input

DS5 Red Port23: Power Fault Input

DS6 Red Port22: Power Fault Input

DS7 Red Port21: Power Fault Input

DS8 Red Port20: Power Fault Input

DS9 Red Port19: Power Fault Input

Location Color Definition

Table 2.20 LED Indicators (Part 2 of 8)

ation Board 2 - 16 February 16, 2011

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Notes

DS10 Red Port18: Power Fault Input

DS11 Red Port17: Power Fault Input

DS12 Red Port16: Power Fault Input

DS13 Red Port15: Power Fault Input

DS14 Red Port14: Power Fault Input

DS15 Red Port13: Power Fault Input

DS16 Red Port12: Power Fault Input

DS17 Red Port11: Power Fault Input

DS18 Red Port10: Power Fault Input

DS19 Red Port9: Power Fault Input

DS20 Red Port8: Power Fault Input

DS21 Red Port7: Power Fault Input

DS22 Red Port6: Power Fault Input

DS23 Red Port5: Power Fault Input

DS24 Red Port4: Power Fault Input

DS25 Red Port3: Power Fault Input

DS26 Red Port2: Power Fault Input

DS27 Red Port1: Power Fault Input

DS28 Red Port0: Power Fault Input

DS29 Green Port23: Power Good Input

DS30 Green Port22: Power Good Input

DS31 Green Port21: Power Good Input

DS32 Green Port20: Power Good Input

DS33 Green Port19: Power Good Input

DS34 Green Port18: Power Good Input

DS35 Green Port17: Power Good Input

DS36 Green Port16: Power Good Input

DS37 Green Port15: Power Good Input

DS38 Green Port14: Power Good Input

DS39 Green Port13: Power Good Input

DS40 Green Port12: Power Good Input

DS41 Green Port11: Power Good Input

DS42 Green Port10: Power Good Input

DS43 Green Port9: Power Good Input

DS44 Green Port8: Power Good Input

DS45 Green Port7: Power Good Input

DS46 Green Port6: Power Good Input

Location Color Definition

Table 2.20 LED Indicators (Part 3 of 8)

ation Board 2 - 17 February 16, 2011

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Notes

DS47 Green Port5: Power Good Input

DS48 Green Port4: Power Good Input

DS49 Green Port3: Power Good Input

DS50 Green Port2: Power Good Input

DS51 Green Port1: Power Good Input

DS52 Green Port0: Power Good Input

DS206 Orange Port23: Attention Indicator Output

DS207 Orange Port22: Attention Indicator Output

DS208 Orange Port21: Attention Indicator Output

DS209 Orange Port20: Attention Indicator Output

DS210 Orange Port19: Attention Indicator Output

DS211 Orange Port18: Attention Indicator Output

DS212 Orange Port17: Attention Indicator Output

DS213 Orange Port16: Attention Indicator Output

DS214 Orange Port15: Attention Indicator Output

DS215 Orange Port14: Attention Indicator Output

DS216 Orange Port13: Attention Indicator Output

DS217 Orange Port12: Attention Indicator Output

DS218 Orange Port11: Attention Indicator Output

DS219 Orange Port10: Attention Indicator Output

DS220 Orange Port9: Attention Indicator Output

DS221 Orange Port8: Attention Indicator Output

DS222 Orange Port7: Attention Indicator Output

DS223 Orange Port6: Attention Indicator Output

DS224 Orange Port5: Attention Indicator Output

DS225 Orange Port4: Attention Indicator Output

DS226 Orange Port3: Attention Indicator Output

DS227 Orange Port2: Attention Indicator Output

DS228 Orange Port1: Attention Indicator Output

DS229 Orange Port0: Attention Indicator Output

DS230 Green Port23: Power Indicator Output

DS231 Green Port22: Power Indicator Output

DS232 Green Port21: Power Indicator Output

DS233 Green Port20: Power Indicator Output

DS234 Green Port19: Power Indicator Output

DS235 Green Port18: Power Indicator Output

DS236 Green Port17: Power Indicator Output

Location Color Definition

Table 2.20 LED Indicators (Part 4 of 8)

ation Board 2 - 18 February 16, 2011

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DS237 Green Port16: Power Indicator Output

DS238 Green Port15: Power Indicator Output

DS239 Green Port14: Power Indicator Output

DS240 Green Port13: Power Indicator Output

DS241 Green Port12: Power Indicator Output

DS242 Green Port11: Power Indicator Output

DS243 Green Port10: Power Indicator Output

DS244 Green Port9: Power Indicator Output

DS245 Green Port8: Power Indicator Output

DS246 Green Port7: Power Indicator Output

DS247 Green Port6: Power Indicator Output

DS248 Green Port5: Power Indicator Output

DS249 Green Port4: Power Indicator Output

DS250 Green Port3: Power Indicator Output

DS251 Green Port2: Power Indicator Output

DS252 Green Port1: Power Indicator Output

DS253 Green Port0: Power Indicator Output

DS53 Green Port23: Power Enable Output

DS54 Green Port22: Power Enable Output

DS55 Green Port21: Power Enable Output

DS56 Green Port20: Power Enable Output

DS57 Green Port19: Power Enable Output

DS58 Green Port18: Power Enable Output

DS59 Green Port17: Power Enable Output

DS60 Green Port16: Power Enable Output

DS61 Green Port15: Power Enable Output

DS62 Green Port14: Power Enable Output

DS63 Green Port13: Power Enable Output

DS64 Green Port12: Power Enable Output

DS65 Green Port11: Power Enable Output

DS66 Green Port10: Power Enable Output

DS67 Green Port9: Power Enable Output

DS68 Green Port8: Power Enable Output

DS69 Green Port7: Power Enable Output

DS70 Green Port6: Power Enable Output

DS71 Green Port5: Power Enable Output

DS72 Green Port4: Power Enable Output

Location Color Definition

Table 2.20 LED Indicators (Part 5 of 8)

ation Board 2 - 19 February 16, 2011

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DS73 Green Port3: Power Enable Output

DS74 Green Port2: Power Enable Output

DS75 Green Port1: Power Enable Output

DS76 Green Port0: Power Enable Output

DS77 Red Slot 23 Reset Output

DS78 Red Slot 22 Reset Output

DS79 Red Slot 21 Reset Output

DS80 Red Slot 20 Reset Output

DS81 Red Slot 19 Reset Output

DS82 Red Slot 18 Reset Output

DS83 Red Slot 17 Reset Output

DS84 Red Slot 16 Reset Output

DS85 Red Slot 15 Reset Output

DS86 Red Slot 14 Reset Output

DS87 Red Slot 13 Reset Output

DS88 Red Slot 12 Reset Output

DS89 Red Slot 11 Reset Output

DS90 Red Slot 10 Reset Output

DS91 Red Slot 9 Reset Output

DS92 Red Slot 8 Reset Output

DS93 Red Slot 7 Reset Output

DS94 Red Slot 6 Reset Output

DS95 Red Slot 5 Reset Output

DS96 Red Slot 4 Reset Output

DS97 Red Slot 3 Reset Output

DS98 Red Slot 2 Reset Output

DS99 Red Slot 1 Reset Output

DS100 Red Slot 0 Reset Output

DS326 Red Partition 7 Fundamental Reset Input

DS327 Red Partition 6 Fundamental Reset Input

DS328 Red Partition 5 Fundamental Reset Input

DS329 Red Partition 4 Fundamental Reset Input

DS330 Red Partition 3 Fundamental Reset Input

DS331 Red Partition 2 Fundamental Reset Input

DS332 Red Partition 1 Fundamental Reset Input

DS333 Red Partition 0 Fundamental Reset Input

DS415 Red Slot 20 Reset Header (J131)

Location Color Definition

Table 2.20 LED Indicators (Part 6 of 8)

ation Board 2 - 20 February 16, 2011

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DS416 Red Slot 16 Reset Header (J130)

DS417 Red Slot 12 Reset Header (J129)

DS418 Red Slot 4 Reset Header (J125)

DS419 Red Slot 6 Reset Header (J128)

DS420 Red Slot 4 Reset Header (J127)

DS421 Red Slot 2 Reset Header (J126)

DS422 Red Slot 0 Reset Header (J125)

DS334 Green Port23: Link Up Status Output

DS335 Green Port22: Link Up Status Output

DS336 Green Port21: Link Up Status Output

DS337 Green Port20: Link Up Status Output

DS338 Green Port19: Link Up Status Output

DS339 Green Port18: Link Up Status Output

DS340 Green Port17: Link Up Status Output

DS341 Green Port16: Link Up Status Output

DS342 Green Port15: Link Up Status Output

DS343 Green Port14: Link Up Status Output

DS344 Green Port13: Link Up Status Output

DS345 Green Port12: Link Up Status Output

DS346 Green Port11: Link Up Status Output

DS347 Green Port10: Link Up Status Output

DS348 Green Port9: Link Up Status Output

DS349 Green Port8: Link Up Status Output

DS350 Green Port7: Link Up Status Output

DS351 Green Port6: Link Up Status Output

DS352 Green Port5: Link Up Status Output

DS353 Green Port4: Link Up Status Output

DS354 Green Port3: Link Up Status Output

DS355 Green Port2: Link Up Status Output

DS356 Green Port1: Link Up Status Output

DS357 Green Port0: Link Up Status Output

DS358 Blue Port23: Link Activity Status Output

DS359 Blue Port22: Link Activity Status Output

DS360 Blue Port21: Link Activity Status Output

DS361 Blue Port20: Link Activity Status Output

DS362 Blue Port19: Link Activity Status Output

DS363 Blue Port18: Link Activity Status Output

Location Color Definition

Table 2.20 LED Indicators (Part 7 of 8)

ation Board 2 - 21 February 16, 2011

IDT Installation of the EB-LOGAN-23 Evaluation Board

89EB-LOGAN-23 Evalu

Notes

DS364 Blue Port17: Link Activity Status Output

DS365 Blue Port16: Link Activity Status Output

DS366 Blue Port15: Link Activity Status Output

DS367 Blue Port14: Link Activity Status Output

DS368 Blue Port13: Link Activity Status Output

DS369 Blue Port12: Link Activity Status Output

DS370 Blue Port11: Link Activity Status Output

DS371 Blue Port10: Link Activity Status Output

DS372 Blue Port9: Link Activity Status Output

DS373 Blue Port8: Link Activity Status Output

DS374 Blue Port7: Link Activity Status Output

DS375 Blue Port6: Link Activity Status Output

DS376 Blue Port5: Link Activity Status Output

DS377 Blue Port4: Link Activity Status Output

DS378 Blue Port3: Link Activity Status Output

DS379 Blue Port2: Link Activity Status Output

DS380 Blue Port1: Link Activity Status Output

DS381 Blue Port0: Link Activity Status Output

Location Color Definition

Table 2.20 LED Indicators (Part 8 of 8)

ation Board 2 - 22 February 16, 2011

IDT Installation of the EB-LOGAN-23 Evaluation Board

89EB-LOGAN-23 Evalu

Notes

EB-LOGAN-23 Board Figure

Figure 2.11 EB32NT24AG2 Evaluation Board

ation Board 2 - 23 February 16, 2011

IDT Installation of the EB-LOGAN-23 Evaluation Board

89EB-LOGAN-23 Evalu

Notes

ation Board 2 - 24 February 16, 2011

Notes

89EB-LOGAN-23 Evaluation Board 3 - 1 Febru

®

Chapter 3

Software For EB-LOGAN-23

IntroductionThis chapter discusses some of the main features of the available software to give users a better under-

standing of what can be achieved with the EB-LOGAN-23 evaluation board using the device managementsoftware.

Device management software and related user documentation are available on a CD which is includedin the Evaluation Board Kit. This information is also available on IDT FTP site and also at my.idt.com. Formore information, please go to: http://www.idt.com/?app=TechSupport&prodFamily=PCIe%20Switches oremail IDT at ssdhelp@idt.com.

Device Management SoftwareThe primary use of the Device Management Software package is to enable users of the evaluation

board to access all the registers in the PES32NT24AG2 device. This access can be achieved using the PCIExpress in-band configuration cycles through the upstream port on the PES32NT24AG2 or through theSMBUS salve interface available on the IDT PCIe switch.

This software also enables users to save a snapshot of the current register set into a dump file whichcan be used for debugging purposes. An export/import facility is also available to create and use “Configu-ration” files which can be used to initialize the switch device with specific values in specific registers.

A conversion utility is also provided to translate a configuration file into an EEPROM programmable datastructure. This enables the user to program an appropriate serial EEPROM with desirable register settingsfor the PES32NT24AG2, and then to populate that EEPROM onto the Evaluation Board. It is also possibleto program the EEPROM directly on the Evaluation Board using a feature provided by the softwarepackage.

The front-end of the Device Management Software is a user-friendly Graphical User Interface whichallows the user to quickly read or write the registers of interest. The GUI also permits the user to run thesoftware in “simulation” mode with no real hardware attached, allowing the creation of configuration files forthe PES32NT24AG2 in the absence of the actual device.

Much of the Device Management Software is written with device-independent and OS-independentcode. The software is expected to work on Linux (/sys interface) and MS Windows XP. It may function wellon various flavors of MS Windows, but may not be validated on all. The fact that the software is device-inde-pendent assures its scalability to future PCIe parts from IDT. Once users are familiar with the GUI, they willbe able to use the same GUI on all PCIe parts from IDT. This software is customized for each devicethrough an XML device description file which includes information on the number of ports, registers, typesof registers, information on bit-fields within each register, etc.

The actual program name of the Device Management Software is “PCIeBrowser” (an executable fileunder Windows or Linux). Revision 5.0.1 or later is required for devices in the PES32NT24AG2 productfamily family.

Device DriversThe PES32NT24AG2 and other members of this switch family offer Non-Transparent Bridging and built-

in DMA capability inside the device. Device drivers are needed to take advantage of these features. Samplecode for these drivers is available from IDT for the Linux operating system. Additionally, there a few othersoftware packages available from IDT. These packages are not related to the evaluation board per se, andtherefore not listed here. However, several of these packages may prove to be useful for specific device orsystem functionality. For more information, please go to http://www.idt.com/?app=TechSupport&prod-Family=PCIe%20Switches or email IDT at ssdhelp@idt.com.

ary 16, 2011

IDT Software For EB-LOGAN-23

89EB-LOGAN-23 Evalu

Notes

ation Board 3 - 2 February 16, 2011

Notes

EB-LOGAN-23 Evaluation Board 4 - 1 Febru

®

Chapter 4

Schematics

Schematics

ary 16, 2011

11.

1. TITLE PAGE / TABLE OF CONTENTS

LED - PORT STATUS (7 OF 7)MIN LOAD RESISTORS

PARTITION RESET SELECT HEADERS

PORT 0 CLOCK GENERATOR

PORT 4 CLOCK GENERATOR

PORT 8 CLOCK GENERATOR

LED - PORT STATUS (6 OF 7)

12PK RIBBON CONNECTORS

SLOT RESET SELECT HEADERS

LED - PORT STATUS (4 OF 7)LED - PORT STATUS (5 OF 7)

LED - PORT STATUS (3 OF 7)LED - PORT STATUS (2 OF 7)LED - PORT STATUS (1 OF 7)DIP SWITCHESRESET, SMBUS, EEPROM, JTAGPOWER REGULATOR - VDDPETAPOWER REGULATOR - VDDPEHAPOWER REGULATOR - VDDPEAPOWER REGULATOR - VDDCOREPOWER REGULATOR - VDDIO

38

41.

31.32.33.34.35.36.37.

45.

42.

44.

39.40.

27.

30.29.28.

43.

46. PORT 2 CLOCK GENERATOR

PORT 20 CLOCK GENERATOR

PORT 12 CLOCK GENERATORPORT 16 CLOCK GENERATOR

PORT 6 CLOCK GENERATOR

52.51.

49.50.

48.47.

CLOCK SELECTOR - DUT PCLK 0-20, GCLK 1-2

HOT PLUG CONTROL PORTS 16-20

CLOCK GENERATOR / SOURCE INPUT

32NT24AG2 - POWER, GNDIOEXPANDER 0-3IOEXPANDER 4-7

IOEXPANDER 12-13

MEZZANINE CONNECTOR PORTS 4, 6

32NT24AG2 - SERDES

MEZZANINE CONNECTOR PORTS 8, 12

IOEXPANDER 20-21HOT PLUG CONTROL PORTS 0-2HOT PLUG CONTROL PORTS 4-6

IOEXPANDER 8-11

IOEXPANDER 16-19

HOT PLUG CONTROL PORTS 8-12

SLOT RESETS AND WAKE PULL-UPS

2.

9.10.

3. 4.

8. 7. 6. 5.

15.

18.17.

14.

12.

16.

19.20.

13.

CLOCK BUFFER - 121.

CLOCK SELECTOR DUT PCLK 16CLOCK SELECTOR DUT PCLK 8

POWER CONNECTORSCLOCK SELECTOR - SLOTS 0-20

24.23.22.

26.25.

MEZZANINE CONNECTOR PORTS 16, 20

MEZZANINE CONNECTOR PORTS 0, 2

32NT24AG2 - CLK, CONFIG, GPIO

Thu Jul 01 15:00:52 2010 SHEET 1 OF 52

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B

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2010

1.0 INITIAL RELEASE 2009-12-05 T. TRAN

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

AUTHOR

6

A

TITLE

CHECKED BY

DCN DESCRIPTION DATEREV

8

8

6 5 4

4

2

2

DD

CC

BB

A

1

1

REV.SIZE

3

DRAWING NO.

REVISIONS

CHANGE BY

3

7

FAB P/N

57

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138COPYRIGHT (C) IDT

STK0CFG1 & STK0CFG0 SET BY MEZZ CARDS

X4 - STK0CFG1 = 0, STK0CFG0 = 1

X8 - STK0CFG1 = 0, STK0CFG0 = 0

Thu Jul 01 15:00:53 2010 SHEET 2 OF 52

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EB-LOGAN-23

B

W9

W7

W5

W3

W1

V8

V6

V4

V2

V10U9

U7

U5

U3

U1

T8

T6

T4

T2

T10R9

R7

R5

R3

R1

P8

P6

P4

P2

P10N9

N7

N5

N3

N1

M8

M6

M4

M2

M10L9

L7

L5

L3

L1

K8

K6

K4

K2

K10J9

J7

J5

J3

J1

H8

H6

H4

H2

H10G9

G7

G5

G3

G1

F8

F6

F4

F2

F10E9

E7

E5

E3

E1

D8

D6

D4

D2

D10C9

C7

C5

C3

C1

B8

B6

B4

B2

B10A9

A7

A5

A3

A1

J1

W19

W17

W15

W13

W11

V20

V18

V16

V14

V12

U19

U17

U15

U13

U11

T20

T18

T16

T14

T12

R19

R17

R15

R13

R11

P20

P18

P16

P14

P12

N19

N17

N15

N13

N11

M20

M18

M16

M14

M12

L19

L15

L13

L11

K20

K18

K16

K14

K12

J19

J15

J13

J11

H20

H18

H16

H14

H12

G19

G15

G13

G11

F20

F18

F16

F14

F12

E19

E15

E13

E11

D20

D18

D16

D14

D12

C19

C17

C15

C13

C11

B20

B18

B16

B14

B12

A19

A17

A15

A13

A11

J1

R10

R9

J49

R7R8

7 33

2

2

19 42

7 39 43 44

25

25

19 42

7 39 43 44

25

25

6

6

6

6

6

6

6

6

6

6

6

6

2

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

7 33

6

6

6

6

6

2

STK0CFG0

MEZZ_SMBDAT1MEZZ_SMBCLK1SLOT_WAKEN0SLOT_HDR_RSTN0

S0_CLKPS0_CLKN

M02_ID<1>

SLOT_WAKEN2SLOT_HDR_RSTN2

S2_CLKNS2_CLKP

PE00RP0PE00RN0

PE00TP0PE00TN0

PE00RP1PE00RN1

PE00TP1PE00TN1

PE01RP0PE01RN0

PE01TN0PE01TP0

100

100

100

S2_3V

S2_3VAUX

S0_3V

S0_3VAUX

100

470-1075-600 (2 of 2)470-1075-600 (1 of 2)

MEZZANINE CONNECTOR PORTS 0/2

+3V3

06031K

MEZZ_SMBDAT1PE01RP1

PE02RP0PE02RN0

PE02TP0PE02TN0

PE01TP1PE01TN1

PE01RN1

PE03TP0

PE03RN0

M02_ID<2>

PE02RN1

PE02TN1

PE03RP0

PE02RP1

PE02TP1

CPRSNTN0

STK0CFG1

CPRSNTN2

PE03TN0

PE03RP1PE03RN1

PE03TP1PE03TN1

MEZZ_SMBCLK1

S0_12V

S2_12V

1K

5%

0603

5%

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

ININ

ININ

OUTOUT

OUT

ININ

OUT

ININ

OUTOUT

BI

OUT

OUT

IN

IN

OUTIN

OUT

ININ

INOUTBI

OUT

IN

IN

ININ

OUTOUT

OUT

OUT

IN

OUT

IN

OUTOUT

OUT

OUT

ININ

OUTOUT

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 4

Wafer 3

Wafer 2

Wafer 1

Wafer 0

V8

T8

P8

M8

K8

H8

F8

D8

B8A7

C7

E7

G7

J7

L7

N7

R7

U7

W7

B6

D6

F6

H6

K6

M6

P6

T6

V6

W5

U5

R5

N5

L5

J5

G5

E5

C5

A5

V10

T10

P10

M10

K10

H10

F10

D10

B10A9

C9

E9

G9

J9

L9

N9

R9

U9

W9

B4

D4

F4

H4

K4

M4

P4

T4

V4

W3

U3

R3

N3

L3

J3

G3

E3

C3

A3

B2

D2

F2

H2

K2

M2

P2

T2

V2

W1

U1

R1

N1

L1

J1

G1

E1

C1

A1

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 9

Wafer 8

Wafer 7

Wafer 6

Wafer 5

V18

T18

P18

M18

K18

H18

F18

D18

B18A17

C17

E17

G17

J17

L17

N17

R17

U17

W17

B16

D16

F16

H16

K16

M16

P16

T16

V16

W15

U15

R15

N15

L15

J15

G15

E15

C15

A15

V20

T20

P20

M20

K20

H20

F20

D20

B20A19

C19

E19

G19

J19

L19

N19

R19

U19

W19

B14

D14

F14

H14

K14

M14

P14

T14

V14

W13

U13

R13

N13

L13

J13

G13

E13

C13

A13

B12

D12

F12

H12

K12

M12

P12

T12

V12

W11

U11

R11

N11

L11

J11

G11

E11

C11

A11

IN

OUT

OUT

STK1CFG1 & STK1CFG0 SET BY MEZZ CARDS

X8 - STK1CFG1 = 0, STK1CFG0 = 0

X4 - STK1CFG1 = 0, STK1CFG0 = 1

Thu Jul 01 15:00:53 2010 SHEET 3 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R21

R20

J50

W19

W17

W15

W13

W11

V20

V18

V16

V14

V12

U19

U17

U15

U13

U11

T20

T18

T16

T14

T12

R19

R17

R15

R13

R11

P20

P18

P16

P14

P12

N19

N17

N15

N13

N11

M20

M18

M16

M14

M12

L19

L17

L15

L13

L11

K20

K18

K16

K14

K12

J19

J17

J15

J13

J11

H20

H18

H16

H14

H12

G19

G17

G15

G13

G11

F20

F18

F16

F14

F12

E19

E17

E15

E13

E11

D20

D18

D16

D14

D12

C19

C17

C15

C13

C11

B20

B18

B16

B14

B12

A19

A17

A15

A13

A11

J2

R17R16

R19R18

W9

W7

W5

W3

W1

V8

V6

V4

V2

V10U9

U7

U5

U3

U1

T8

T6

T4

T2

T10R9

R7

R5

R3

R1

P8

P6

P4

P2

P10N9

N7

N5

N3

N1

M8

M6

M4

M2

M10L9

L7

L5

L3

L1

K8

K6

K4

K2

K10J9

J7

J5

J3

J1

H8

H6

H4

H2

H10G9

G7

G5

G3

G1

F8

F6

F4

F2

F10E9

E7

E5

E3

E1

D8

D6

D4

D2

D10C9

C7

C5

C3

C1

B8

B6

B4

B2

B10A9

A7

A5

A3

A1

J2

3

7 33

3

7 39 43 44

19 42

25

25

7 39 43 44

19 42

25

25

6

6

6

6

6

6

6

6

6

6

6

6

3

3

7 33

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

MEZZ_SMBDAT2

STK1CFG0

MEZZ_SMBCLK2

SLOT_HDR_RSTN4SLOT_WAKEN4

S4_CLKPS4_CLKN

M46_ID<1>

SLOT_HDR_RSTN6SLOT_WAKEN6

S6_CLKNS6_CLKP

PE04RP0PE04RN0

PE04TP0PE04TN0

PE04RP1PE04RN1

PE04TP1PE04TN1

PE05RP0PE05RN0

PE05TN0PE05TP0

100

100

100

S6_3VAUX

S6_3V

S4_3V

S4_3VAUX

100

470-1075-600 (2 of 2)

MEZZANINE CONNECTOR PORTS 4/6

+3V3

5%

06031K

5%

06031K

S6_12V

S4_12V

470-1075-600 (1 of 2)

MEZZ_SMBCLK2

MEZZ_SMBDAT2

M46_ID<2>

STK1CFG1

CPRSNTN6

PE07RP0

PE06TP1PE06TN1

PE07TN1

PE07RN1PE07RP1

PE06RP1

PE06TN0

PE07TP1

PE06RN1

PE07TN0PE07TP0

PE07RN0

CPRSNTN4

PE06TP0

PE05RP1

PE06RP0PE06RN0

PE05TP1PE05TN1

PE05RN1

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 4

Wafer 3

Wafer 2

Wafer 1

Wafer 0

V8

T8

P8

M8

K8

H8

F8

D8

B8A7

C7

E7

G7

J7

L7

N7

R7

U7

W7

B6

D6

F6

H6

K6

M6

P6

T6

V6

W5

U5

R5

N5

L5

J5

G5

E5

C5

A5

V10

T10

P10

M10

K10

H10

F10

D10

B10A9

C9

E9

G9

J9

L9

N9

R9

U9

W9

B4

D4

F4

H4

K4

M4

P4

T4

V4

W3

U3

R3

N3

L3

J3

G3

E3

C3

A3

B2

D2

F2

H2

K2

M2

P2

T2

V2

W1

U1

R1

N1

L1

J1

G1

E1

C1

A1

IN

BI

OUT

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 9

Wafer 8

Wafer 7

Wafer 6

Wafer 5

V18

T18

P18

M18

K18

H18

F18

D18

B18A17

C17

E17

G17

J17

L17

N17

R17

U17

W17

B16

D16

F16

H16

K16

M16

P16

T16

V16

W15

U15

R15

N15

L15

J15

G15

E15

C15

A15

V20

T20

P20

M20

K20

H20

F20

D20

B20A19

C19

E19

G19

J19

L19

N19

R19

U19

W19

B14

D14

F14

H14

K14

M14

P14

T14

V14

W13

U13

R13

N13

L13

J13

G13

E13

C13

A13

B12

D12

F12

H12

K12

M12

P12

T12

V12

W11

U11

R11

N11

L11

J11

G11

E11

C11

A11

OUT

ININ

OUTOUT

ININ

OUTOUT

OUT

ININ

OUTOUT

IN

ININ

OUT

IN

OUT

OUT

OUT

ININ

OUTOUT

OUT

OUT

IN

IN

IN

OUTOUT

ININ

OUT

OUT

IN

OUT

ININ

INOUT

INBI

OUT

OUT

X4 - STK2CFG1 = 0, STK2CFG0 = 1

X8 - STK2CFG1 = 0, STK2CFG0 = 0

STK2CFG1 & STK2CFG0 SET BY MEZZ CARDS

Thu Jul 01 15:00:53 2010 SHEET 4 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R32

R31

J51

W19

W17

W15

W13

W11

V20

V18

V16

V14

V12

U19

U17

U15

U13

U11

T20

T18

T16

T14

T12

R19

R17

R15

R13

R11

P20

P18

P16

P14

P12

N19

N17

N15

N13

N11

M20

M18

M16

M14

M12

L19

L17

L15

L13

L11

K20

K18

K16

K14

K12

J19

J17

J15

J13

J11

H20

H18

H16

H14

H12

G19

G17

G15

G13

G11

F20

F18

F16

F14

F12

E19

E17

E15

E13

E11

D20

D18

D16

D14

D12

C19

C17

C15

C13

C11

B20

B18

B16

B14

B12

A19

A17

A15

A13

A11

J3

R27R28

R30R29

W9

W7

W5

W3

W1

V8

V6

V4

V2

V10U9

U7

U5

U3

U1

T8

T6

T4

T2

T10R9

R7

R5

R3

R1

P8

P6

P4

P2

P10N9

N7

N5

N3

N1

M8

M6

M4

M2

M10L9

L7

L5

L3

L1

K8

K6

K4

K2

K10J9

J7

J5

J3

J1

H8

H6

H4

H2

H10G9

G7

G5

G3

G1

F8

F6

F4

F2

F10E9

E7

E5

E3

E1

D8

D6

D4

D2

D10C9

C7

C5

C3

C1

B8

B6

B4

B2

B10A9

A7

A5

A3

A1

J3

7 33

4

4

7 39 43 44

19 42

25

25

19 42

7 39 43 44

25

25

6

6

6

6

6

6

6

6

6

6

6

6

7 33

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

4

4

STK2CFG0

MEZZ_SMBDAT3MEZZ_SMBCLK3

SLOT_HDR_RSTN8SLOT_WAKEN8

S8_CLKPS8_CLKN

M812_ID<1>

SLOT_WAKEN12SLOT_HDR_RSTN12

S12_CLKPS12_CLKN

PE08RP0PE08RN0

PE08TN0PE08TP0

PE09RP0PE09RN0

PE09TP0PE09TN0

PE10RP0PE10RN0

PE10TP0PE10TN0

100

100

100

100

S12_3VAUX

S12_3V

S8_3V

S8_3VAUX

470-1075-600 (2 of 2)

STK2CFG1

CPRSNTN12

M812_ID<2>

PE13RP0

PE12TN0PE12TP0

PE11RP0

PE12RP0PE12RN0

PE11TP0PE11TN0

PE11RN0

PE13RN0

CPRSNTN8

PE13TP0

PE14TN0PE14TP0

PE14RN0PE14RP0

PE13TN0

PE15RN0PE15RP0

PE15TN0PE15TP0

MEZZ_SMBDAT3

MEZZ_SMBCLK3

470-1075-600 (1 of 2)

S12_12V

S8_12V

5%

1K

0603

5%

06031K

+3V3

MEZZANINE CONNECTOR PORTS 8/12

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

ININ

BI

OUT

OUT

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 9

Wafer 8

Wafer 7

Wafer 6

Wafer 5

V18

T18

P18

M18

K18

H18

F18

D18

B18A17

C17

E17

G17

J17

L17

N17

R17

U17

W17

B16

D16

F16

H16

K16

M16

P16

T16

V16

W15

U15

R15

N15

L15

J15

G15

E15

C15

A15

V20

T20

P20

M20

K20

H20

F20

D20

B20A19

C19

E19

G19

J19

L19

N19

R19

U19

W19

B14

D14

F14

H14

K14

M14

P14

T14

V14

W13

U13

R13

N13

L13

J13

G13

E13

C13

A13

B12

D12

F12

H12

K12

M12

P12

T12

V12

W11

U11

R11

N11

L11

J11

G11

E11

C11

A11

OUT

ININ

OUTOUT

ININ

OUTOUT

IN

IN

IN

OUTOUT

ININ

OUTOUT

OUT

IN

OUT

ININ

OUTOUT

OUT

OUT

ININ

OUT

OUT

OUT

ININ

INOUT

OUT

IN

OUT

IN

INOUTBIIN

OUT

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 4

Wafer 3

Wafer 2

Wafer 1

Wafer 0

V8

T8

P8

M8

K8

H8

F8

D8

B8A7

C7

E7

G7

J7

L7

N7

R7

U7

W7

B6

D6

F6

H6

K6

M6

P6

T6

V6

W5

U5

R5

N5

L5

J5

G5

E5

C5

A5

V10

T10

P10

M10

K10

H10

F10

D10

B10A9

C9

E9

G9

J9

L9

N9

R9

U9

W9

B4

D4

F4

H4

K4

M4

P4

T4

V4

W3

U3

R3

N3

L3

J3

G3

E3

C3

A3

B2

D2

F2

H2

K2

M2

P2

T2

V2

W1

U1

R1

N1

L1

J1

G1

E1

C1

A1

X4 - STK3CFG1 = 0, STK3CFG0 = 1

X8 - STK3CFG1 = 0, STK3CFG0 = 0

STK3CFG1 & STK3CFG0 SET BY MEZZ CARDS

Thu Jul 01 15:00:53 2010 SHEET 5 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R43

R42

J52

W19

W17

W15

W13

W11

V20

V18

V16

V14

V12

U19

U17

U15

U13

U11

T20

T18

T16

T14

T12

R19

R17

R15

R13

R11

P20

P18

P16

P14

P12

N19

N17

N15

N13

N11

M20

M18

M16

M14

M12

L19

L17

L15

L13

L11

K20

K18

K16

K14

K12

J19

J17

J15

J13

J11

H20

H18

H16

H14

H12

G19

G17

G15

G13

G11

F20

F18

F16

F14

F12

E19

E17

E15

E13

E11

D20

D18

D16

D14

D12

C19

C17

C15

C13

C11

B20

B18

B16

B14

B12

A19

A17

A15

A13

A11

J4

R38R39

R41R40

W9

W7

W5

W3

W1

V8

V6

V4

V2

V10U9

U7

U5

U3

U1

T8

T6

T4

T2

T10R9

R7

R5

R3

R1

P8

P6

P4

P2

P10N9

N7

N5

N3

N1

M8

M6

M4

M2

M10L9

L7

L5

L3

L1

K8

K6

K4

K2

K10J9

J7

J5

J3

J1

H8

H6

H4

H2

H10G9

G7

G5

G3

G1

F8

F6

F4

F2

F10E9

E7

E5

E3

E1

D8

D6

D4

D2

D10C9

C7

C5

C3

C1

B8

B6

B4

B2

B10A9

A7

A5

A3

A1

J4

7 33

19 42

7 39 43 44

5

5

25

25

19 42

25

25

7 39 43 44

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

7 33

5

5

STK3CFG0

SLOT_WAKEN16SLOT_HDR_RSTN16

MEZZ_SMBDAT4MEZZ_SMBCLK4

S16_CLKN

M1620_ID<1>

S16_CLKP

SLOT_WAKEN20

S20_CLKNS20_CLKP

SLOT_HDR_RSTN20

PE16RP0PE16RN0

PE16TP0PE16TN0

PE17RN0PE17RP0

PE17TN0PE17TP0

PE18RP0PE18RN0

PE18TP0PE18TN0

100

100

100

100

S16_3V

S20_3V

S20_3VAUX

470-1075-600 (2 of 2)

S16_3VAUX

PE19RN0

PE19TN0PE19TP0

PE20TN0PE20TP0

PE20RN0PE20RP0

PE19RP0

PE21RP0

PE22TN0PE22TP0

CPRSNTN20

PE22RP0

CPRSNTN16

PE22RN0

PE23RP0PE23RN0

PE23TP0PE23TN0

PE21TN0

PE21RN0

PE21TP0

STK3CFG1

M1620_ID<2>

MEZZ_SMBDAT4

MEZZ_SMBCLK4

470-1075-600 (1 of 2)

S16_12V

S20_12V

5%

06031K

06031K

5%

+3V3

MEZZANINE CONNECTOR PORTS 16/20

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUT

ININ

OUT

BI

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 9

Wafer 8

Wafer 7

Wafer 6

Wafer 5

V18

T18

P18

M18

K18

H18

F18

D18

B18A17

C17

E17

G17

J17

L17

N17

R17

U17

W17

B16

D16

F16

H16

K16

M16

P16

T16

V16

W15

U15

R15

N15

L15

J15

G15

E15

C15

A15

V20

T20

P20

M20

K20

H20

F20

D20

B20A19

C19

E19

G19

J19

L19

N19

R19

U19

W19

B14

D14

F14

H14

K14

M14

P14

T14

V14

W13

U13

R13

N13

L13

J13

G13

E13

C13

A13

B12

D12

F12

H12

K12

M12

P12

T12

V12

W11

U11

R11

N11

L11

J11

G11

E11

C11

A11

OUT

ININ

OUTOUT

OUTOUT

ININ

OUT

ININ

OUTOUT

ININ

IN

INOUT

OUT

IN

IN

IN

OUT

IN

OUT

BI

IN

ININ

OUTOUT

OUT

OUT

IN

OUT

IN

OUTOUT

OUT

OUT

ININ

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Common Power

Signal

Wafer 4

Wafer 3

Wafer 2

Wafer 1

Wafer 0

V8

T8

P8

M8

K8

H8

F8

D8

B8A7

C7

E7

G7

J7

L7

N7

R7

U7

W7

B6

D6

F6

H6

K6

M6

P6

T6

V6

W5

U5

R5

N5

L5

J5

G5

E5

C5

A5

V10

T10

P10

M10

K10

H10

F10

D10

B10A9

C9

E9

G9

J9

L9

N9

R9

U9

W9

B4

D4

F4

H4

K4

M4

P4

T4

V4

W3

U3

R3

N3

L3

J3

G3

E3

C3

A3

B2

D2

F2

H2

K2

M2

P2

T2

V2

W1

U1

R1

N1

L1

J1

G1

E1

C1

A1

OUT

OUT

Thu Jul 01 15:00:54 2010 SHEET 6 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

AB18AA18

V17W17

AB17AA17

V16W16

AB15AA15

V14W14

AB14AA14

V13W13

AB9AA9

V10W10

AB8AA8

V9W9

AB6AA6

V7W7

AB5AA5

V6W6

AB12AA12

AB11AA11

U1

U1U2

U5U4

T1T2

T5T4

P1P2

P5P4

N1N2

N5N4

L1L2

L5L4

K1K2

K5K4

H1H2

H5H4

G1G2

G5G4

V3W3

E3F3

U1

A5

A6

B5

B6

E7

E8

D7

D8

A8

A9

B8

B9

E10

E11

D10

D11

A15

A16

B15

B16

E14

E15

D14

D15

A18

A19

B18

B19

E17

E18

D17

D18

A11B11

A13B13

U1

G22

H22

G21

H21

G18

H18

G19

H19

K22

L22

K21

L21

K18

L18

K19

L19

N22

P22

N21

P21

N18

P18

N19

P19

T22

U22

T21

U21

T18

U18

T19

U19

E20F20

W20V20

U1

3

5

3

2

2

24

5

5

5

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

24

24

22

22

3

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

24

24

24

3

5

5

5

5

5

5

5

5

5

23

23

24

24

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

24

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

24

24

24

PE07TP0

PE23RN0

32NT24AG2 - SERDES

PE04TP1

PE01RN1

PE00RP0

P00CLKN

PE23TN0

PE22RP0

PE23TP0

PE15TN0PE15TP0

PE14TN0PE14TP0

PE13TN0PE13TP0

PE12TN0PE12TP0

PE11TN0PE11TP0

PE10TN0PE10TP0

PE09TN0PE09TP0

PE08TN0PE08TP0

PE15RN0PE15RP0

PE14RN0PE14RP0

PE13RN0PE13RP0

PE12RN0PE12RP0

PE11RN0PE11RP0

PE10RN0PE10RP0

PE09RN0PE09RP0

PE08RN0PE08RP0

P12CLKNP12CLKP

P08CLKNP08CLKP

PE07TN1

PE01TP0PE01TN0

PE00TN0

PE03TN0PE03TP0

PE03TN1PE03TP1

PE02TN0PE02TP0

PE02TN1PE02TP1

PE01TN1PE01TP1

PE00TP0

PE00TN1PE00TP1

PE03RN0PE03RP0

PE03RN1PE03RP1

PE02RN0PE02RP0

PE02RN1PE02RP1

PE01RN0PE01RP0

PE01RP1

PE00RN0

PE00RN1PE00RP1

P02CLKNP02CLKP

P00CLKP

PE05TP0

PE18TP0

PE19TN0

PE20TP0PE20TN0

PE19TP0

PE18TN0

PE17TN0PE17TP0

PE16TN0

P16CLKPP16CLKN

P20CLKPP20CLKN

PE16RP0PE16RN0

PE17RP0PE17RN0

PE18RP0PE18RN0

PE19RP0PE19RN0

PE20RP0PE20RN0

PE21RP0PE21RN0

PE22RN0

PE23RP0

PE16TP0

PE21TP0PE21TN0

PE22TP0PE22TN0

P06CLKN

PE07TN0

PE07TP1

PE06TN0PE06TP0

PE06TN1PE06TP1

PE05TN0

PE05TN1PE05TP1

PE04TN0PE04TP0

PE04TN1

PE07RN0PE07RP0

PE07RN1PE07RP1

PE06RN0PE06RP0

PE06RN1PE06RP1

PE05RN0PE05RP0

PE05RN1PE05RP1

PE04RN0PE04RP0

PE04RN1PE04RP1

P06CLKP

P04CLKNP04CLKP

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUT

OUTOUT

OUT

OUT

OUTOUT

OUTOUT

OUTIN

OUT

IN

ININ

ININ

ININ

IN

IN

IN

ININ

ININ

OUTOUT

OUTOUT

OUT

IN

OUT

OUTOUT

OUTOUT

OUTOUT

OUTOUT

OUT

IN

OUT

OUTOUT

OUTOUT

OUTOUT

OUTOUT

OUT

IN

OUT

OUTOUT

OUTOUT

OUTOUT

ININ

IN

ININ

ININ

ININ

ININ

ININ

IN

ININ

ININ

ININ

ININ

ININ

IN

ININ

IN

32NT24AG2 6/7

PE18TP0

PE19TN0

PE20TP0

PE20TN0

PE19TP0

PE18TN0

PE17TN0

PE17TP0

PE16TN0

P16CLKP

P16CLKN

P20CLKP

P20CLKN

PE16RP0

PE16RN0

PE17RP0

PE17RN0

PE18RP0

PE18RN0

PE19RP0

PE19RN0

PE20RP0

PE20RN0

PE21RP0

PE21RN0

PE22RP0

PE22RN0

PE23RP0

PE23RN0

PE16TP0

PE21TP0

PE21TN0

PE22TP0

PE22TN0

PE23TP0

PE23TN0

32NT24AG2 5/7

PE15TN0

PE15TP0

PE14TN0

PE14TP0

PE13TN0

PE13TP0

PE12TN0

PE12TP0

PE11TN0

PE11TP0

PE10TN0

PE10TP0

PE09TN0

PE09TP0

PE08TN0

PE08TP0

PE15RN0

PE15RP0

PE14RN0

PE14RP0

PE13RN0

PE13RP0

PE12RN0

PE12RP0

PE11RN0

PE11RP0

PE10RN0

PE10RP0

PE09RN0

PE09RP0

PE08RN0

PE08RP0

P12CLKN

P12CLKP

P08CLKN

P08CLKP

32NT24AG2 4/7

P06CLKN

PE07TN0

PE07TP0

PE07TN1

PE07TP1

PE06TN0

PE06TP0

PE06TN1

PE06TP1

PE05TN0

PE05TP0

PE05TN1

PE05TP1

PE04TN0

PE04TP0

PE04TN1

PE04TP1

PE07RN0

PE07RP0

PE07RN1

PE07RP1

PE06RN0

PE06RP0

PE06RN1

PE06RP1

PE05RN0

PE05RP0

PE05RN1

PE05RP1

PE04RN0

PE04RP0

PE04RN1

PE04RP1

P06CLKP

P04CLKN

P04CLKP

IN

32NT24AG2 3/7

PE01TP0

PE01TN0

PE00TN0

PE03TN0

PE03TP0

PE03TN1

PE03TP1

PE02TN0

PE02TP0

PE02TN1

PE02TP1

PE01TN1

PE01TP1

PE00TP0

PE00TN1

PE00TP1

PE03RN0

PE03RP0

PE03RN1

PE03RP1

PE02RN0

PE02RP0

PE02RN1

PE02RP1

PE01RN0

PE01RP0

PE01RN1

PE01RP1

PE00RN0

PE00RP0

PE00RN1

PE00RP1

P02CLKN

P02CLKP

P00CLKN

P00CLKP

OUTOUT

OUTOUT

OUT

OUTOUT

OUTOUT

IN

OUT

OUTOUT

OUTOUT

OUTOUT

OUT

OUTOUT

IN

ININ

ININ

ININ

ININ

IN

IN

IN

ININ

ININ

ININ

IN

ININ

IN

IN

ININ

ININ

ININ

INOUT

OUT

IN

IN

PLACE RESISTORS AS CLOSE TO U1 AS POSSIBLE

DUT RESET

Thu Jul 01 15:00:54 2010 SHEET 7 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

C21D21

D22Y22

C20A20

A22B21A21D20C22

Y21AA22AA21AB22Y20Y19AA20Y18AA19

U1

Y5Y4

AA3Y3

C3C1B3B2Y2

B1A3A2A1

AA2

AB20AB1

AB21Y1

AA4

D12

Y14Y9N6K6C9D13K17N17

B20

C16Y8

Y11

A12

Y12

B12

AB2

C2D2D3D1

B22AA1

U1R55

R24

R46R47R48R49R50R51R52R53R54

R45

9876543

20

2

19181716151413121110

1

J118

TP108

5 39 43 44

3 39 43 44

4 33

34

34

34

33

9 10 11 12 13 14 32

9 10 11 12 13 14 32

4 39 43 44

5 39 43 44

4 39 43 44

3 39 43 44

2 39 43 44

2 39 43 44

32 41 44 45 46 47 48 49 50 51 52

32

32

33

33

5 33

33

5 33

33

4 33

33

33

33

3 33

3 33

2 33

2 33

33

33

33

33

33

33

33

33

33

33

33

24

24

33

24

24

34

34

34

34

34

34

32

32

32

32

32

SLOT_HDR_RSTN16

+3V3

SLOT_HDR_RSTN4

STK2CFG0

GPIO4

GPIO6

GPIO8

32NT24AG2 CLK, CONFIG, GPIO

STK3CFG4

MSMBDAT

MSMBCLK

SLOT_HDR_RSTN12

SLOT_HDR_RSTN20

SLOT_HDR_RSTN8SLOT_HDR_RSTN6

SLOT_HDR_RSTN2SLOT_HDR_RSTN0MAIN_RSTN

SSMBDAT

SSMBCLK

SSMBADDR1

SSMBADDR2

STK3CFG0

STK3CFG2

STK3CFG1

STK3CFG3

STK2CFG1

STK2CFG2

STK2CFG4

STK2CFG3

STK1CFG0

STK1CFG1

STK0CFG1

STK0CFG0

CLKMODE0

CLKMODE1

G0

G1

G2

G3

SWMODE0

SWMODE1

SWMODE2

SWMODE3

RSTHALT

GCLK0P

GCLK0N

GCLKFSEL

GCLK1N

GCLK1P

REFRES03

REFRES00

PERSTN

REFRES07

REFRES06

REFRES05

REFRES04

REFRES02

REFRES01

REFRESPLL

GPIO7

GPIO3

GPIO5

GPIO1

GPIO2

GPIO0

DUT_JTAG_TRST_N

DUT_JTAG_TMS

DUT_JTAG_TCK

DUT_JTAG_TDI

DUT_JTAG_TDO

YEL

1K

0603

5%

1K

0603

5%

2.0MMVERT_SMNO-SHROUD

0

3.01K

3.01K

3.01K

3.01K

3.01K

3.01K

3.01K

3.01K

3.01K

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

32NT24AG2 2/7

GPIO08

GPIO07

GPIO06

GPIO05

GPIO04

GPIO03

GPIO02

GPIO01

GPIO00

JTAG_TRST_N

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

SSMBDAT

SSMBCLK

SSMBADDR1

SSMBADDR2

MSMBDAT

MSMBCLK

32NT24AG2 1/6

REFRES03

REFRES00

G3

G2

G1

G0

STK1CFG1

STK2CFG3

STK2CFG1

GCLKP1

GCLKN1

GCLKP0

GCLKN0

GCLKFSEL

PERSTN

RSTHALT

SWMODE3

SWMODE2

SWMODE1

SWMODE0

CLKMODE0

STK0CFG1

STK0CFG0

STK1CFG0

STK2CFG4

STK2CFG2

STK2CFG0

STK3CFG4

STK3CFG3

STK3CFG2

STK3CFG1

STK3CFG0

REFRES07

REFRES06

REFRES05

REFRES04

REFRES02

REFRES01

REFRESPLL

NC

NCCLKMODE1

ININ

ININ

INOUT

IN

IN

OUT

OUTOUTOUTOUTOUT

OUTOUTOUT

IN

IN

ININ

IN

IN

IN

ININININ

IN

IN

INININ

IN

ININ

IN

ININ

IN

IN

ININININ

IN

ININ

IN

ININ

OUTBI

ININ

BIIN

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

IN

LABEL:

3 NC

1 GND2 12V/5V

LABEL: FAN

Thu Jul 01 15:00:54 2010 SHEET 8 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

N12M8P15N11M5P12N8M4P11M3

A7 M2M1P8N3L20M22P3M21M20

M19

C14

L15J5K8J4J3J2J1L8K3

H20

B10

J22L3

J21J20J19H15J18K20H12J15

C13

H11J12

H8K15J11K12

J8K11

H3E16

C12

F19F18F17E13G20E12

E9G15

E6

E5

A4

F6F5G8F4F2F1D19G3D16F22

C11

F21C8B4C7C6D9C5C4D6D5

B7

D4A17A14

AB16AB10AB19

B17

AB13AB7AB4W18AB3W15Y17Y16W12Y15

C19

W11Y13

AA16W8

Y10AA13

W5Y7

AA10Y6

C18

V22AA7V21V19V18

T8V15V12V11

T3

B14

U6V8

R22U3

R21R20

V5R19

V4

R18

A10

V2T20V1R15U20R12T15R11U17R8

C17

R5R4M18R3R2N20R1M15P20N15

C15

C10

H6F14G17F13F12F11F10

U12U11U10

T6U9

F9

R17T17U14

R6U13P17

P6J6

H17J17

G6

R7H16

H7F16F15G16

F8F7

T7U8U7

R16T16U16U15

G7

J16K16J7G14G13G12G11

T14T13T12T11T10T9M17M16N16

G10

P16M7M6N7P7L17L16K7L7L6

G9

W1W22W21E4E2E1E22E21

W19W4W2

E19

H13J14H10J13

H9K14

R14R13R10

R9M14M13M12

J10

M11N14M10N13

M9P14N10P13

N9P10

K13

P9L14K10L13

K9L12L11L10

L9H14

J9

U1

4321

5678

CP7

4321

5678

CP4

4321

5678

CP2

C118

C115

C111

C109

4321

5678

CP8

4321

5678

CP5

4321

5678

CP3

4321

5678

CP1

C54

C49

C31

C119

C116

C98

C94

C83

C79

C75

C66

C62

C107

C104

C101

C97

C93

C90

C87

C82

C78

C74

C70

C65

C61

C57

C52

C47

C42

C39

C34

C30

C27

C23

C18

C13

C8

C3

C53

C48

C45

C40

C35

C26

C22

C17

C12

C7

C2

C114

4321

5678

CP9

4321

5678

CP6

C106

C103

C96

C91

C77

C69

C86

C92

C72

C55

C60

C43

C41

C51

C64

C46

C44

C33

C37

C24

C29

C25

C19

C14

C9

C4

C10

C15

C20

C5

C21

C16

C11

C6

C1

W31

321

W30

+2V5_PEHA

+1V0_PETA

+1V0_PETA

47UF

32NT24AG2 - POWER

0.1UF

0.1UF

0.1UF

0.1UF

+5V0_PS

0.01UF

0.1UF

0.1UF

0.1UF0.1UF

+1V0_PEA

1.0UF

47UF

47UF

47UF

47UF

0.01UF

0.01UF

0.1UF

0.1UF

0.1UF 0.1UF 0.1UF

0.1UF

0.1UF

0.1UF 0.1UF

+1V0_CORE

0.01UF

0.1UF

0.01UF

+2V5_PEHA

+3V3_IO

0.1UF

0.1UF

1.0UF

47UF

47UF

47UF

0.1UF

47UF

47UF

0.01UF

47UF

0.01UF

0.1UF

0.1UF

0.1UF

0.01UF

0.01UF

0.01UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

47UF

47UF

47UF

1.0UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

47UF

47UF

47UF

1.0UF

47UF

47UF

47UF

1.0UF

+1V0_CORE

+12V3_PS

+1V0_PEA+3V3_IO

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

32NT24AG2 7/7

VDDPETA

VDDPEA

VDDCORE

VDDCORE

VDDCORE

VDDPETA

VDDPETA

VDDPEA

VDDPEA VDDCORE

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDCORE

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDCORE

VDDCORE

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEHA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEA

VDDPEHA

VDDPEHA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPETA

VDDPEA

VDDPEA

VDDPEA

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VSS

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDCORE

VDDPEA

VDDIO

VDDPETA

VDDPETA

IOEXPANDER 3

ADDR: 0X26

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND

IOEXPANDER 2

ADDR: 0X24

ON SAME SIDE OF BOARD

IOEXPANDER 0

IOEXPANDER 1

ADDR: 0X22

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

ADDR: 0X20

PLACE RESISTORS ON CLOSE AND

Thu Jul 01 15:00:55 2010 SHEET 9 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R1614

R77R78

12

24

2322

20191817161514131110987654

1

32

21

U22

C186

R72R73

R71

R1615

R79R80

12

24

2322

20191817161514131110987654

1

32

21

U23

C187

R75R74

R76

R69

R1612

R66R65

R59R60R61

12

24

2322

20191817161514131110987654

1

32

21

U20

C184

R1613

R62R63

R68R67

R64

12

24

2322

20191817161514131110987654

1

32

21

U21

C185

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

9 10 11 12 13 14 34

18 37 42

14 19 37

36

34 42

18 35 42

36

18 35 42

34

36

36

14 19 37

17 37 42

17 35 42

34

34 42

17 35 42

34 42

34

15 35 42

15 35 42

15 37 42

36

36

14 19 37

34

34 42

16 35 42

16 35 42

36

36

16 37 42

14 19 37

9 10 11 12 13 14 34

9 10 11 12 13 14 34

9 10 11 12 13 14 34

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

14 19 37

18 37 42

36

18 35 42

36

18 35 42

34 42

34

17 37 42

14 19 37

36

36

17 35 42

34 42

17 35 42

34

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

34 42

34

15 35 42

15 35 42

15 37 42

36

36

14 19 37

34

34 42

16 35 42

16 35 42

36

36

16 37 42

14 19 37

MSMBDATMSMBCLK

MSMBDATMSMBCLK

IOEXPINTN

P16_PEPP16_RSTN

P16_PIN

P16_PDNP16_PFN

P16_AINP16_PWRGDN

P16_APN

P8_AINP8_PIN

P8_RSTNP8_PEP

P8_PWRGDN

P8_APNP8_PDNP8_PFN

P0_PDNP0_APN

P0_PFNP0_PWRGDN

P0_PEPP0_PINP0_AIN

P0_RSTNP4_APNP4_PDN

P4_PWRGDNP4_PFN

P4_PINP4_AIN

P4_PEPP4_RSTN

IOEXPINTN

+3V3

0

0

2.7K

0

0

0.1UF

+3V3

0

0

0

0

0

0.1UF

+3V3

0

MAX7311AUG

0

1K

MAX7311AUG

IOEXPINTN

IOEXPINTN

MSMBDATMSMBCLK

P20_RSTNP20_PEPP20_PIN

P20_PWRGDNP20_AIN

P20_PFNP20_PDNP20_APN

P12_PEPP12_RSTN

P12_PINP12_AINP12_PWRGDN

P12_PDNP12_PFN

P12_APN

MSMBDATMSMBCLK

P2_PDNP2_APN

P2_PFNP2_PWRGDN

P2_PEPP2_PINP2_AIN

P2_RSTNP6_APNP6_PDN

P6_PWRGDNP6_PFN

P6_PINP6_AIN

P6_PEPP6_RSTN

+3V3

0

0

0

2.7K

2.7K

0.1UF

0

+3V3

+3V3

MAX7311AUG

0

0

0

0

2.7K

0.1UF

0

MAX7311AUG

+3V3

IOEXPANDER 0-3

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

BIIN

OUT

INININ

INOUT

OUT

OUTOUT

IN

OUTINININ

OUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

BIIN

ININININ

OUTOUT

OUT

INOUT

ININ

OUT

INOUTOUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

INBI

IN

IN

INININ

OUTOUT

OUTOUT

INININBI

OUTIN

OUT

OUT

OUTOUT

OUT

ININ

OUT

INOUT

IN

OUT

ININ

OUTIN

IN

OUTOUT

OUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

ADDR: 0X2E

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

ADDR: 0X2C

IOEXPANDER 6

ON SAME SIDE OF BOARD

IOEXPANDER 7

PLACE RESISTORS ON CLOSE AND

IOEXPANDER 4

ADDR: 0X28

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

ADDR: 0X2A

IOEXPANDER 5

Thu Jul 01 15:00:55 2010 SHEET 10 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R1618

R1619

12

24

2322

20191817161514131110987654

1

32

21

U26

C190

R101R102

R95R96R97

12

24

2322

20191817161514131110987654

1

32

21

U27

C191

R98R99

R104R103

R100

R1616

R1617

12

24

2322

20191817161514131110987654

1

32

21

U24

C188

R89R90

R84R83

R85

12

24

2322

20191817161514131110987654

1

32

21

U25

C189

R91R92

R87R86

R88

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

34 42

34

35 42

35 42

37 42

36

36

14 19 37

34

34 42

35 42

35 42

36

36

37 42

14 19 37

9 10 11 12 13 14 34

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

34 42

34

35 42

35 42

37 42

36

36

14 19 37

34

34 42

35 42

35 42

36

36

37 42

14 19 37

9 10 11 12 13 14 34

9 10 11 12 13 14 34

9 10 11 12 13 14 34

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

14 19 37

37 42

36

36

35 42

35 42

34 42

14 19 37

34

37 42

36

36

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

34 42

34

35 42

35 42

37 42

36

36

14 19 37

34

34 42

35 42

35 42

36

36

37 42

14 19 37

35 42

35 42

34 42

34

MSMBDATMSMBCLK

P5_PDNP5_APN

P5_PFNP5_PWRGDN

P5_PEPP5_PINP5_AIN

P5_RSTNP7_APNP7_PDN

P7_PWRGDNP7_PFN

P7_PINP7_AIN

P7_PEPP7_RSTN

IOEXPINTN

MSMBDATMSMBCLK

P1_PDNP1_APN

P1_PFNP1_PWRGDN

P1_PEPP1_PINP1_AIN

P1_RSTNP3_APNP3_PDN

P3_PWRGDNP3_PFN

P3_PINP3_AIN

P3_PEPP3_RSTN

IOEXPINTN

0

0

0.1UF

MAX7311AUG

0

2.7K

+3V3

0

2.7K

2.7K

0

+3V3

0

+3V3

0

0

0.1UF

MAX7311AUG

0

+3V3

IOEXPINTN

IOEXPINTN

0.1UF

+3V3

MSMBDATMSMBCLK

P22_RSTNP22_PEP

P22_AINP22_PIN

P22_PFNP22_PWRGDN

P22_PDN

P18_RSTNP22_APN

P18_PEPP18_PINP18_AIN

MSMBDATMSMBCLK

P10_PDNP10_APN

P10_PFNP10_PWRGDN

P10_PEPP10_PINP10_AIN

P10_RSTNP14_APNP14_PDN

P14_PWRGDNP14_PFN

P14_PINP14_AIN

P14_PEPP14_RSTN

P18_PFNP18_PWRGDN

P18_PDNP18_APN

0

0

0

2.7K

+3V3

2.7K

2.7K

2.7K

2.7K

0

+3V3

0.1UF

0

0

MAX7311AUG

0

+3V3

MAX7311AUG

IOEXPANDER 4-7

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUTOUTOUT

OUT

ININ

OUTIN

OUT

OUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

BIIN

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

INBI

OUT

ININ

ININ

OUTOUTOUT

INOUT

IN

ININ

OUTOUT

OUTOUT

OUT

IN

ININ

IN

OUTOUT

OUT

INOUT

ININ

INOUTOUT

IN

OUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

BI

INBI

ININ

OUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

ININ

OUT

IN

ININ

OUT

IN

OUT

OUT

OUT

OUTOUT

INININ

INOUT

IN

ADDR: 0X52

PLACE RESISTORS ON CLOSE AND

ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND

ADDR: 0X50

ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND

ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND

ADDR: 0X56

IOEXPANDER 11

ADDR: 0X54

IOEXPANDER 9

IOEXPANDER 8 IOEXPANDER 10

ON SAME SIDE OF BOARD

Derek Huang

Thu Jul 01 15:00:55 2010 SHEET 11 OF 52

Logan Validation Board

B

2009

1.02.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

R119R120R121

R162212

24

2322

20191817161514131110987654

1

32

21

U30

R125R126

C194

R122R123R124

R162312

24

2322

20191817161514131110987654

1

32

21

U31

C195

R127R128

R108R107

R109

R162012

24

2322

20191817161514131110987654

1

32

21

U28

C192

R113R114

R110R111R112

R162112

24

2322

20191817161514131110987654

1

32

21

U29

C193

R116R115

9 10 11 12 13 14 34 9 10 11 12 13 14 34

9 10 11 12 13 14 34 9 10 11 12 13 14 34

14 19 37

35 42

34 42

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

14 19 37

34

35 42

35 42

36

36

37 42

14 19 37

37 42

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

34 42

34

35 42

35 42

36

36

34

34 42

35 42

36

37 42

14 19 37

36

35 42

34 42

34

14 19 37

37 42

36

36

35 42

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

14 19 37

34

34 42

35 42

35 42

36

36

37 42

14 19 37

37 42

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

34 42

34

35 42

35 42

36

36

34 42

34

35 42

35 42

37 42

36

36

14 19 37

34

34 42

35 42

35 42

36

36

37 42

IOEXPINTN IOEXPINTN

IOEXPINTNIOEXPINTN

+3V3

P19_RSTN

P9_PFN

IOEXPANDER 8-11

P15_PDNMSMBDATMSMBCLK

P13_RSTNP15_APN

P15_PWRGDNP15_PFN

P15_PINP15_AIN

P15_PEPP15_RSTN

P13_PEP

MSMBDATMSMBCLK

P13_PDNP13_APN

P13_PFNP13_PWRGDN

P13_PINP13_AIN

P9_APN

P11_PDN

P11_PWRGDNP11_AIN

P11_PEPP11_RSTN

P11_PIN

P11_PFN

P9_PDN

P11_APNP9_RSTNP9_PEPP9_PINP9_AINP9_PWRGDN

MSMBCLKMSMBDAT

P21_RSTNP23_APNP23_PDN

P23_PWRGDNP23_PFN

P23_PINP23_AIN

P23_PEPP23_RSTN

P21_PEP

MSMBDATMSMBCLK

P21_PDNP21_APN

P21_PFNP21_PWRGDN

P21_PINP21_AIN

P17_PDNP17_APN

P17_PFNP17_PWRGDN

P17_PEPP17_PINP17_AIN

P17_RSTNP19_APNP19_PDN

P19_PWRGDNP19_PFN

P19_PINP19_AIN

P19_PEP

0

0

0.1UF

MAX7311AUG

0

0

0

0

0

0

+3V3

0.1UF

MAX7311AUG

0

0

0

0

+3V3

+3V3

0

0

0.1UF

MAX7311AUG

0

0

2.7K

0

+3V3

0.1UF

0

0

MAX7311AUG

0

0

2.7K

0

+3V3

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

OUT

OUT

IN

ININ

IN

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

OUT

OUTOUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

ININ

ININ

INBI

OUT

OUTOUTOUTOUTININININ

OUTOUTOUTOUT

IN

ININ

INOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

IN

INBI

INBI

OUT

BI

OUTOUTININININ

OUT

IN

IN

IN

OUT

IN

OUT

OUT

IN

OUTOUT

IN

OUT

OUTOUT

OUT

ININ

OUTOUT

ININ

IN

OUTIN

OUT

OUT

ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND

ADDR: 0X5C

ADDR: 0X5E

IOEXPANDER 15

ON SAME SIDE OF BOARD

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

IOEXPANDER 12

IOEXPANDER 13

ADDR: 0X5A

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

IOEXPANDER 14

PLACE RESISTORS ON CLOSE AND

ADDR: 0X58

Thu Jul 01 15:00:55 2010 SHEET 12 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R1166R1167

R1160R1161R1162

R162612

24

2322

20191817161514131110987654

1

32

21

U96

C647

R162712

24

2322

20191817161514131110987654

1

32

21

U97

C648

R1168R1169

R1165R1164R1163

R1149R1148

R1154R1155

R1150

R162412

24

2322

20191817161514131110987654

1

32

21

U89

C645

R162512

24

2322

20191817161514131110987654

1

32

21

U90

C646

R1151R1152R1153

R1156R1157

38

38

38

38

9 10 11 12 13 14 34 9 10 11 12 13 14 34

9 10 11 12 13 14 34 9 10 11 12 13 14 34

39

39

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

38

38

38

38

38

38

38

38

38

38

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

38

38

38

38

38

38

38

38

38

38

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

38

38

38

38

38

38

38

38

39

39

39

39

39

39

39

39

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

39

39

39

39

39

39

38

38

38

38

38

38

38

38

P0_MRLNP1_MRLNP2_MRLN

P5_MRLN

IOEXPINTN IOEXPINTN

IOEXPINTNIOEXPINTN

P18_ILOCKP

P7_ILOCKP

IOEXPANDER 12-15

MSMBCLKMSMBDAT

P22_MRLN

P23_MRLN

P17_MRLNP19_MRLNP21_MRLN

P15_MRLNP13_MRLN

P9_MRLNP11_MRLN

P20_MRLN

MSMBCLKMSMBDAT

P16_MRLNP18_MRLN

P12_MRLNP14_MRLN

P10_MRLNP8_MRLNP7_MRLN

P4_MRLN

P6_MRLN

P3_MRLN

MSMBCLKMSMBDAT

P1_ILOCKSTP3_ILOCKSTP5_ILOCKSTP7_ILOCKSTP10_ILOCKSTP14_ILOCKSTP18_ILOCKSTP22_ILOCKSTP1_ILOCKP

P5_ILOCKPP3_ILOCKP

P10_ILOCKPP14_ILOCKP

P22_ILOCKP

P20_ILOCKPP16_ILOCKP

MSMBCLKMSMBDAT

P8_ILOCKPP12_ILOCKP

P4_ILOCKPP6_ILOCKP

P2_ILOCKPP0_ILOCKPP20_ILOCKST

P8_ILOCKSTP12_ILOCKSTP16_ILOCKST

P6_ILOCKSTP4_ILOCKST

P0_ILOCKSTP2_ILOCKST

+3V3

0

0

2.7K

0

0

0.1UF

MAX7311AUG

0

+3V3

0.1UF

MAX7311AUG

0

+3V3

2.7K

0

0

0

0

+3V3

+3V3

0

2.7K

2.7K

0

0

0.1UF

MAX7311AUG

0

+3V3

0.1UF

MAX7311AUG

0

2.7K

+3V3

2.7K

0

0

0

+3V3

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

INBI

OUT

OUTOUT

IN

ININ

IN

ININ

ININ

OUTOUTOUTOUTOUTOUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

OUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

BIIN

INININININININ

ININ

INININININ

INBI

OUT

IN

ININ

ININININ

ININ

ININ

BI

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

OUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

ININ

ININ

ININ

IN

OUTIN

OUTOUTOUTOUTOUT

ADDR: 0XA2

ON SAME SIDE OF BOARD

ON SAME SIDE OF BOARD

PLACE RESISTORS ON CLOSE AND

IOEXPANDER 19

ADDR: 0XA6

PLACE RESISTORS ON CLOSE ANDON SAME SIDE OF BOARD

ON SAME SIDE OF BOARDPLACE RESISTORS ON CLOSE AND

IOEXPANDER 17

PLACE RESISTORS ON CLOSE AND

ADDR: 0XA4

IOEXPANDER 18IOEXPANDER 16

ADDR: 0XB0

Thu Jul 01 15:00:56 2010 SHEET 13 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

12

24

2322

20191817161514131110987654

1

32

21

U87

C643

R1143R1142

R1137R1136

R1138

12

24

2322

20191817161514131110987654

1

32

21

U88

C644

R1145R1144

R1139R1140R1141

C641

R162812

24

2322

20191817161514131110987654

1

32

21

U85

R1131R1130

R1124R1125R1126

12

24

2322

20191817161514131110987654

1

32

21

U86

C642

R1132R1133

R1127R1128R1129

9 10 11 12 14 34

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

7 9 10 11 12 13 14 32

39

39

39

39

39

39

39

39

38

38

38

38

38

38

38

38

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

IOEXPINTN

MSMBCLK

+3V3

IOEXPANDER 16-19

MSMBDATMSMBCLK

P15_LINKUPNP14_LINKUPN

P12_LINKUPNP13_LINKUPN

P10_LINKUPNP11_LINKUPN

P9_LINKUPNP8_LINKUPNP7_LINKUPN

P4_LINKUPNP5_LINKUPNP6_LINKUPN

P3_LINKUPNP2_LINKUPN

P0_LINKUPNP1_LINKUPN

MSMBDAT

P23_ILOCKPP21_ILOCKP

P17_ILOCKPP19_ILOCKP

P13_ILOCKPP15_ILOCKP

P11_ILOCKPP9_ILOCKPP23_ILOCKST

P17_ILOCKSTP19_ILOCKSTP21_ILOCKST

P15_ILOCKSTP13_ILOCKST

P9_ILOCKSTP11_ILOCKST

MSMBCLKMSMBDAT

P16_LINKUPN

P18_LINKUPNP17_LINKUPN

P19_LINKUPNP20_LINKUPNP21_LINKUPN

P23_LINKUPNP22_LINKUPN

P16_ACTIVENP17_ACTIVENP18_ACTIVENP19_ACTIVENP20_ACTIVENP21_ACTIVEN

P23_ACTIVENP22_ACTIVEN

MSMBCLKMSMBDAT

P15_ACTIVENP14_ACTIVEN

P12_ACTIVENP13_ACTIVEN

P10_ACTIVENP11_ACTIVEN

P9_ACTIVENP8_ACTIVENP7_ACTIVEN

P4_ACTIVENP5_ACTIVENP6_ACTIVEN

P3_ACTIVENP2_ACTIVEN

P0_ACTIVENP1_ACTIVEN

+3V3

0

0

2.7K

0

0

0.1UF

MAX7311AUG

0

0

0

0

0

MAX7311AUG

00.1UF

+3V3

+3V3

0

0

2.7K

0

0

0.1UF

MAX7311AUG

+3V3

0

0

0

0

0

0.1UF

+3V3

MAX7311AUG

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

BIIN

OUT

OUT

OUTOUT

OUTOUT

OUTOUT

OUTOUTOUT

OUT

OUTOUT

OUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

BIIN

ININ

ININ

ININ

IN

OUTIN

OUTOUTOUTOUTOUT

OUTOUT

OUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

INBI

OUTOUTOUTOUTOUTOUTOUTOUTOUT

BIOUTOUTOUTOUTOUTOUTOUT

OUTOUTOUT

OUTOUT

OUTOUTOUTOUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

OUTOUT

OUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

IN

ADDR: 0XA8

ADDR: 0XAA

IOEXPANDER 21

ON SAME SIDE OF BOARD

ON SAME SIDE OF BOARD

PLACE RESISTORS ON CLOSE AND

PLACE RESISTORS ON CLOSE AND

IOEXPANDER 20

Thu Jul 01 15:00:56 2010 SHEET 14 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R131R132

R137R138

R133

R163312

24

2322

20191817161514131110987654

1

32

21

U83

C196

R135R134

R136

R139R140

12

24

2322

20191817161514131110987654

1

32

21

U84

C197

9 10 11 12 13 34

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

10 19 37

11 19 37

11 19 37

11 19 37

10 19 37

11 19 37

11 19 37

10 19 37

11 19 37

11 19 37

10 19 37

11 19 37

10 19 37

10 19 37

10 19 37

7 9 10 11 12 13 14 32

7 9 10 11 12 13 14 32

10 19 37

39 43

39 43

39 43

39 43

39 43

39 43

39 43

39 43

9 19 37

9 19 37

9 19 37

9 19 37

9 19 37

9 19 37

9 19 37

9 19 37

IOEXPINTN

MSMBDATMSMBCLK

P22_RSTNP23_RSTN

P19_RSTNP21_RSTN

P18_RSTNP17_RSTNP15_RSTNP14_RSTNP13_RSTNP11_RSTNP10_RSTNP9_RSTNP7_RSTNP5_RSTNP3_RSTN

MSMBDATMSMBCLK

P1_RSTN

PART7_PERSTNPART6_PERSTNPART5_PERSTNPART4_PERSTN

PART2_PERSTNPART3_PERSTN

PART1_PERSTNPART0_PERSTNP20_RSTNP16_RSTNP12_RSTNP8_RSTNP6_RSTNP4_RSTNP2_RSTNP0_RSTN

0

2.7K

0

0

0

+3V3

0

0

0

0

0

+3V3

0.1UF

0

+3V3

0.1UF

MAX7311AUG

MAX7311AUG

IOEXPANDER 20-21

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUTOUTOUTOUTOUTOUTOUTOUTIN

ININ

BI

IN

ININ

IN

INBI

OUT

ININ

OUT

OUTOUT

OUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

OUT

OUTOUT

OUTOUTOUT

OUTOUT

OUTOUTOUT

A0

A2

VSS

A1

V+

SDA

SCL

P1

P0

P2

P3

P6

P5

P4

P7

P8

P9

P11

P10

P13

P12

P14

P15

INT_N

Thu Jul 01 15:00:56 2010 SHEET 15 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

W4

W3

C253

R186R184

8765

4321

Q3

C251

R182

R180

R178

8765

4321

Q1

R176

W5

W6

W7

W8C254

R187R185

8765

4321

Q4

C252

R183

R181

8765

4321

Q2

R177

7

19

33

14

38

3926

15

37

17

35

16

36

20

32

25

27

13

1

8

6

18

34

10

4

12

2

9

5

11

3

22

30

24

28

21

31

23

29

U45

R179

R175

R174

R173

R171

R172

R169

R170

R168

R167

C250

R154

R153

R156R155

R157R158R159

R161R160

R162

R164

R166R165

R163

9 37 42

9 35 42

9 35 42

9 35 42

9 35 42

9 37 42

HOT PLUG CONTROL PORTS 0-2

10K

P2_PEP

P2_PWRGDN

P2_PFN

P0_PWRGDN

P0_PFN

P0_PEP

100

100

100

100

100

100

100

100

100

100

100

100

10K

10K

1.0UF

10K

10K

10K

10K

10K

10K

10K

33

+3V3_PS +12V3_PS

10

0.008

51

0.013

0.015UF

10 15

0.047UF

S2_12V

S2_3V

S2_3VAUX

0.008

10

51

0.013

0.015UF

10 15

0.047UF

S0_3VAUX

S0_12V

+3V3_PS

S0_3V

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

NMOSFET

S S S G

D D D D

IN

NMOSFET

S S S G

D D D D

OUT

NMOSFET

S S S G

D D D D

OUT

NMOSFET

S S S G

D D D D

LTC4242CUHF

FON2

ENN2

GND2

GND1

ENN1

FON1

3VIN2

3VGATE2

3VSENSE2

3VOUT2

AUXOUT2

AUXOUT1

3VOUT1

3VGATE1

3VIN1

3VSENSE1

12VOUT2

12VGATE2

12VSENSE2

12VIN2

AUXIN2

AUXON2

ON2

PGOODN2

AUXPGOODN2

AUXFAULTN2

FAULTN2

AUXPGOODN1

PGOODN1

AUXFAULTN1

FAULTN1

ON1

AUXON1

AUXIN1

VCC

12VSENSE1

12VIN1

12VOUT1

12VGATE1

OUT

OUT

IN

Thu Jul 01 15:00:57 2010 SHEET 16 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R221R219 W9

W10

C258

W11

W12

W13

W14C259

8765

4321

Q7

C256

R215

R217

R222R220

8765

4321

Q8

C257

R216

R218

R211

R213

8765

4321

Q5

R210

R212

8765

4321

Q6

R214

7

19

33

14

38

3926

15

37

17

35

16

36

20

32

25

27

13

1

8

6

18

34

10

4

12

2

9

5

11

3

22

30

24

28

21

31

23

29

U46

C255

R207

R209

R208

R205

R206

R204

R203

R202

R190R191R192R193R194R195R196R197

R189

R188

R199R198

R201R200

9 37 42

9 35 42

9 35 42

9 35 42

9 35 42

9 37 42

HOT PLUG CONTROL PORTS 4-6

P6_PEP

P6_PWRGDN

P6_PFN

P4_PWRGDN

P4_PFN

P4_PEP

100

100

100

100

10K

10K

100

100

100

100

100

100

100

100

10K

10K

10K

10K

10K

10K

10K

10K

1.0UF

10

0.008

33

10

+3V3_PS +12V2_PS

0.008

0.013

51

0.015UF

10 15

0.013

51

0.015UF

0.047UF

S6_12V

S6_3V

S6_3VAUX

S4_3VAUX

0.047UF

S4_12V

10 15

+3V3_PS

S4_3V

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

NMOSFET

S S S G

D D D D

OUT

NMOSFET

S S S G

D D D D

OUT

NMOSFET

S S S G

D D D D

NMOSFET

S S S G

D D D D

LTC4242CUHF

FON2

ENN2

GND2

GND1

ENN1

FON1

3VIN2

3VGATE2

3VSENSE2

3VOUT2

AUXOUT2

AUXOUT1

3VOUT1

3VGATE1

3VIN1

3VSENSE1

12VOUT2

12VGATE2

12VSENSE2

12VIN2

AUXIN2

AUXON2

ON2

PGOODN2

AUXPGOODN2

AUXFAULTN2

FAULTN2

AUXPGOODN1

PGOODN1

AUXFAULTN1

FAULTN1

ON1

AUXON1

AUXIN1

VCC

12VSENSE1

12VIN1

12VOUT1

12VGATE1

OUT

OUT

IN

Thu Jul 01 15:00:57 2010 SHEET 17 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

W15

W16

C263

R256R254

8765

4321

Q11

C261

R250

R252

R248

R246

8765

4321

Q9

R245

W17

W18

W19

W20C264

R257R255

C262

R251

8765

4321

Q12

R253

R247

7

19

33

14

38

3926

15

37

17

35

16

36

20

32

25

27

13

1

8

6

18

34

10

4

12

2

9

5

11

3

22

30

24

28

21

31

23

29

U47

C260

R249

8765

4321

Q10

R244

R243

R241

R242

R240

R239

R238

R237

R225R226R227R228R229R230R231R232R233R234R235R236

R224

R223

9 37 42

9 35 42

9 35 42

9 35 42

9 37 42

9 35 42

+3V3_PS

S12_12V

S12_3V

S12_3VAUX

S8_3VAUX

+12V2_PS

S8_12V

+3V3_PS

S8_3V

HOT PLUG CONTROL PORTS 8-12

P12_PEP

P12_PWRGDN

P12_PFN

P8_PWRGDN

P8_PEP

P8_PFN10K

10K

100

100

100

100

100

100

100

100

100

100

100

100

10K

10K

10K

10K

10K

10K

10K

10K

10

1.0UF

0.008

0.013

51

0.015UF

10 15

0.047UF

33

0.008

10

0.013

51

0.015UF

10 15

0.047UF

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

NMOSFET

S S S G

D D D D

OUT

NMOSFET

S S S G

D D D D

IN

NMOSFET

S S S G

D D D D

OUT

LTC4242CUHF

FON2

ENN2

GND2

GND1

ENN1

FON1

3VIN2

3VGATE2

3VSENSE2

3VOUT2

AUXOUT2

AUXOUT1

3VOUT1

3VGATE1

3VIN1

3VSENSE1

12VOUT2

12VGATE2

12VSENSE2

12VIN2

AUXIN2

AUXON2

ON2

PGOODN2

AUXPGOODN2

AUXFAULTN2

FAULTN2

AUXPGOODN1

PGOODN1

AUXFAULTN1

FAULTN1

ON1

AUXON1

AUXIN1

VCC

12VSENSE1

12VIN1

12VOUT1

12VGATE1

NMOSFET

S S S G

D D D D

OUT

OUT

IN

Thu Jul 01 15:00:57 2010 SHEET 18 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

W21

C268

R291R289

C266

R285

R281

W22

W23

W24

W25

W26

8765

4321

Q15

R292

C269

R290

8765

4321

Q16

C267

R287

R283

8765

4321

Q13

R286

R288

R284

7

19

33

14

38

3926

15

37

17

35

16

36

20

32

25

27

13

1

8

6

18

34

10

4

12

2

9

5

11

3

22

30

24

28

21

31

23

29

U48

R282

8765

4321

Q14

R280

R278

R279

R277

R276

R275

R274

R273

R272

R261R260

R263R262

R264R265R266

R268R267

R269R270R271

C265

R258

R259

9 35 42

9 35 42

9 37 42

9 35 42

9 35 42

9 37 42

HOT PLUG CONTROL PORTS 16-20

P20_PWRGDN

P20_PFN

P20_PEP

P16_PFN

P16_PWRGDN

P16_PEP

10K

10K

1.0UF

100

100

100

100

100

100

100

100

100

100

100

100

10K

10K

10K

10K

10K

10K

10K

10K

33

0.008

10

0.013

51

10

0.013

0.015UF

10

0.047UF

15S20_12V

S20_3V

S20_3VAUX

S16_3VAUX

S16_12V

+3V3_PS +12V3_PS

0.008

51

0.015UF

10 15

0.047UF

+3V3_PS

S16_3V

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

NMOSFET

S S S G

D D D D

OUT

NMOSFET

S S S G

D D D D

NMOSFET

S S S G

D D D D

OUT

LTC4242CUHF

FON2

ENN2

GND2

GND1

ENN1

FON1

3VIN2

3VGATE2

3VSENSE2

3VOUT2

AUXOUT2

AUXOUT1

3VOUT1

3VGATE1

3VIN1

3VSENSE1

12VOUT2

12VGATE2

12VSENSE2

12VIN2

AUXIN2

AUXON2

ON2

PGOODN2

AUXPGOODN2

AUXFAULTN2

FAULTN2

AUXPGOODN1

PGOODN1

AUXFAULTN1

FAULTN1

ON1

AUXON1

AUXIN1

VCC

12VSENSE1

12VIN1

12VOUT1

12VGATE1

NMOSFET

S S S G

D D D D

IN

OUT

OUT

Thu Jul 01 15:00:57 2010 SHEET 19 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R1285R1286R1287R1288

R1289R1290R1291R1292

R1293R1294R1295R1296

R1297

R1299R1298

R1300

R1301

R1303R1302

R1304

R1305R1306R1307R1308

R36

R37

R44

R1280

R1281

4

51

3

2

U108

4

51

3

2

U109

4

51

3

2

U110

4

51

3

2

U111

4

51

3

2

U112

R1282

R1283

R1284

C672

C671

C670

C669

4

51

3

2

U113

4

51

3

2

U114

4

51

3

2

U115

R15

R22

R23

R25

R26

4

51

3

2

U100

4

51

3

2

U101

4

51

3

2

U102

4

51

3

2

U103

4

51

3

2

U104

R1

R2

R3

4

51

3

2

U4

4

51

3

2

U5

R4

R11

4

51

3

2

U6

4

51

3

2

U7

4

51

3

2

U8

R33

R34

R35

C668

C667

C666

C665

4

51

3

2

U105

4

51

3

2

U106

4

51

3

2

U107

R12

R13

R14

4

51

3

2

U9

4

51

3

2

U10

C664

C663

C662

C661

4

51

3

2

U11

42

42

42

4 42

2 42

42

2 42

42

3 42

42

3 42

42

4 42

42

42

42

42

42

5 42

42

42

42

5 42

42

42 44 42 44

41 42 43

41 42 43

41 42 43

42 44

41 42 43

41 42 43

41 42 43

42 44

41 42 43

41 42 43

41 42 43

42 44

41 42 43

41 42 43

41 42 43

42 44

41 42 43

42 44

41 42 43

42 44

41 42 43

41 42 43

9 14 37

11 14 37

9 14 37

11 14 37

10 14 37

11 14 37

9 14 37

11 14 37

10 14 37

11 14 37

10 14 37

11 14 37

9 14 37

11 14 37

10 14 37

11 14 37

9 14 37

10 14 37

9 14 37

10 14 37

9 14 37

10 14 37

9 14 37

10 14 37

SLOT_WAKEN23

SLOT_WAKEN19

SLOT_WAKEN14

SLOT_WAKEN12

SLOT_WAKEN0SLOT_WAKEN1SLOT_WAKEN2SLOT_WAKEN3

SLOT_WAKEN4SLOT_WAKEN5SLOT_WAKEN6SLOT_WAKEN7

SLOT_WAKEN8SLOT_WAKEN9SLOT_WAKEN10SLOT_WAKEN11

SLOT_WAKEN13

SLOT_WAKEN15

SLOT_WAKEN16SLOT_WAKEN17SLOT_WAKEN18

SLOT_WAKEN22

SLOT_WAKEN20SLOT_WAKEN21

SLOT_RSTN0SLOT_RSTN16

SLOT_RSTN17

SLOT_RSTN18

SLOT_RSTN19

SLOT_RSTN20

SLOT_RSTN21

SLOT_RSTN22

SLOT_RSTN23

SLOT_RSTN8

SLOT_RSTN9

SLOT_RSTN10

SLOT_RSTN11

SLOT_RSTN12

SLOT_RSTN13

SLOT_RSTN14

SLOT_RSTN15

SLOT_RSTN2

SLOT_RSTN3

SLOT_RSTN4

SLOT_RSTN5

SLOT_RSTN6

SLOT_RSTN7

SLOT_RSTN1

P16_RSTN

P17_RSTN

0.1UF

0.1UF

0.1UF

0.1UF

10K

10K

P8_RSTN

P9_RSTN

P18_RSTN

P19_RSTN

P20_RSTN

P21_RSTN

P22_RSTN

P23_RSTN

10K

10K

P10_RSTN

P11_RSTN

10K

10K

10K

P12_RSTN

P13_RSTN

P14_RSTN

+3V3

10K

P15_RSTN

0.1UF

0.1UF

0.1UF

0.1UF

10K

10K

P0_RSTN

P1_RSTN

0.1UF

0.1UF

0.1UF

10K

0.1UF

10K

10K

P2_RSTN

P3_RSTN

10K

10K

10K

P4_RSTN

P5_RSTN

P6_RSTN

+3V3

10K

P7_RSTN

10K

10K

10K

10K

10K

10K

+3V3

10K

SLOT RESETS AND WAKE PULL-UPS

+3V3

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

SN74LVC1G125

Y

VCCOE_N

A

GND

OUT

OUT

OUT

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

IN

OUT

IN

OUT

IN

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

OUT

IN

OUT

IN

OUT

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

IN

IN

OUT

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

IN

OUT

IN

IN

OUT

IN

SN74LVC1G125

Y

VCCOE_N

A

GND

OUTOUT

OUT

OUT

OUT

OUTOUT

OUTOUT

OUTOUT

OUTOUT

OUTOUTOUTOUT

OUTOUTOUTOUT

OUTOUTOUTOUT

OUT

OUT

SN74LVC1G125

Y

VCCOE_N

A

GND

OUT

OUT

OUT

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

SN74LVC1G125

Y

VCCOE_N

A

GND

PLACE R317 & R318 U51

NC

NCNC

NC

PLACE J6 CLOSE TO U51

Thu Jul 01 15:00:58 2010 SHEET 20 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R70

R57

R58

R56

C28C32C36C38

MTG2MTG1

7654321

J121

C281

5 4

32

1

J119

5 4

32

1

J120

FB1

C280

C279

C278

C277

R306

C276

C275

C274

C273

TP2

R309

R307

R308

R310

R302

R301

R304

R303

R305

R299

R297

R295

C270

R298

R296

R294

21

X1

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U49R

300

R293

C271

R311

R313

R315

R317

R318

R316

R314

R312

MTG2MTG1

7654321

J8

54

3 2

1

J7

5 4

32

1

J5

98765432

10

1

J6

21

20

20

21

20

20

33

33

32

20

20

20

20

CLOCK

1.0UF

221789-0

CONNSMA

221789-0

CONNSMA

0805

120OHM

400MA

0.1UF

10UF

0.1UF

0.1UF

5%0603

10

0.1UF

0.1UF

0.1UF

10UF

16V

YEL

0402

1%

DNP

DNP

0402

1%

0402

1%

DNP

DNP

1%

1%

DNP

475

1%

CONNSMA

221789-0

CONNSMA

221789-0

2.00MMVERT-SMNO-SHROUD

MAIN_CLKN

SATAIN_CLKN

CGCLKNSMAIN_CLKNSMAIN_CLKP

MAIN_CLKP

SATAIN_CLKP

CGCLKP

22PF

22PF

ICS_FS

0402

0402

ICS_SSM

SATAIN_RSTN

DNP

10K

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

0.1UF

0.1UF

0.1UF

0.1UF

CG_SATA_CLKNCG_SATA_CLKP

CG_SMA_CLKPCG_SMA_CLKN

CGCLKNCGCLKP

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

+3V3

SATAIN_CLKNSATAIN_CLKP

+3V3

DNP

DNP

DNP

DNP

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

OUTOUT

HDR_2x5

109

87

65

1 2

3 4

12

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

OUT

IN

IN

IN

OUTOUT

OUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

OUT

IN

SILKSCREEN LABEL:

-------------------

SWITCH S11

4 P6_CLK_EN

6 P12_CLK_EN 5 P8_CLK_EN

1 P0_CLK_EN 2 P2_CLK_EN 3 P4_CLK_EN

-------------------POS DESCRIPTION

8 P20_CLK_EN 7 P16_CLK_EN

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

18-691-001 2.0

SHEET 21 OF 52

Derek Huang

2010

B

Thu Jul 01 15:00:58 2010

R411R410

C50C56

C59C58

C303

C302

C301

FB3

C300

C752

C751

C299

C298

C297

C296

C295

R386

C294

C293

54

3 2

1

J122

54

3 2

1

J123

R388R389

R390R391

R393R392

R394R395

R398

R396R397

R399

R400R401

R403R402

R1638R1639

R1640R1641

R408R409

R433

R432

R1645

R1644

R1643

R1642

R427

R425

R426

R423

R424

R422

R420

R421

R419

R418

R417

R415

R416

R414

R413

R412

R381

R379

R377

R376

R375

R372

R374

R373

R371

R1637

R387

36

64

5748412417

81

3332

52

47

44

39

26

21

18

13

10

60

55

5

29

62

30

564940251694

313461

23

5150

4645

4342

3837

2728

2223

1920

1415

1112

5958

5453

67

35

63

U51

R385

R384

R383

R382

R380

R378

R1636

R1635

R1634

98107116125134143152161

S11

R1649

R1647

MTG2MTG1

7654321

J124

24

24

24

24

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

25

20

20

+3V3

+3V3

BGCLK1PBGCLK1N

BGCLK0PBGCLK0N

BS00CLKPBS00CLKN

BS02CLKP

BS04CLKPBS04CLKN

BS20CLKN

BS02CLKN

BS06CLKP

BS08CLKPBS08CLKN

BS06CLKN

BS12CLKPBS12CLKN

BS16CLKNBS16CLKP

BS20CLKP

SATAOUT_CLKNSATAOUT_CLKP0.1UF

SMAOUT_CLKNSMAOUT_CLKP

0.1UF

0.1UF

0.1UF

33.2

SMAOUT_CLKN_RSMAOUT_CLKP_R

BS20CLKN_RBS20CLKP_R

BS16CLKN_RBS16CLKP_R

BS12CLKN_RBS12CLKP_R

BS08CLKN_RBS08CLKP_R

BS06CLKN_RBS06CLKP_R

BS04CLKN_RBS04CLKP_R

BS02CLKN_RBS02CLKP_R

BS00CLKN_RBS00CLKP_R

BGCLK1N_RBGCLK1P_R

BGCLK0N_RBGCLK0P_R

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

CLOCK BUFFER - 1

10K

0402

0.1UF

10UF

10K

SATAOUT_CLKNSATAOUT_CLKP

MAIN_CLKNMAIN_CLKP

10K

10K

10K

DNP

10K

DNP

10K

1%

475

10K

10K

10K

10K

10K

10K

10K

10K

DNP

10K

221789-0

CONNSMA

CONNSMA

221789-0

0.1UF

1.0UF

10

5%0603

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

120OHM

0805 400MA

0.1UF

0.1UF

1.0UF

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUT

OUTOUT

OUTOUT

OUTOUT

OUTOUT

OUTOUT

ININ

IDT ICS9DB1200yGLF

DIF_0_P

DIF_0_N

DIF_1_P

DIF_1_N

DIF_2_P

DIF_2_N

DIF_3_P

DIF_3_N

DIF_4_P

DIF_4_N

DIF_5_P

DIF_5_N

DIF_6_N

DIF_6_P

DIF_7_N

DIF_7_P

DIF_8_N

DIF_8_P

DIF_9_N

DIF_9_P

DIF_10_N

DIF_10_P

DIF_11_N

DIF_11_P

OE0_N

OE1_N

OE2_N

OE3_N

OE4_N

OE5_N

OE6_N

OE7_N

OE8_N

OE9_N

OE10_N

OE11_N

FS0

FS1

FS2

DIF_IN_N

DIF_IN_P

GND6

GND5

GND4

GND3

GND2

GND1

GND0

VDDA

VDD6

VDD5

VDD4

VDD3

VDD2

VDD1

VDD0

AGND

IREF

VTTPWRGD_N_PD

BYPASS_N_PLL

SMBDAT

SMBCLK

HIGH_BW_N

N_C

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

OUTOUT

OUTOUT

OUTOUT

OUTOUT

OUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

DEFAULT DIPSW SETTING

LP8CLK - LOCAL CLOCK GEN. PORT 8 CLK

P08CLK - DUT PORT 8 CLK

P8SHXXCLK - TO SLOT CLK HEADERS

ON (DISABLE)

U18 OUTPUTS

PLACE R502 CLOSE TO U18

OFF (ENABLE)

PLACE 470 AND 56 OHM RESISTORS CLOSE TO DESTINATION.

C136 CLOSE TO VDDA

S19:3 OFF (PLL)

S19:6 ON (100MHZ)

S19:1 OFF (SATACLK)

S19:4 OFF (2.2MHZ)S19:5 OFF (U17 OUTPUT ON)

18-691-001

2010

B

EB-LOGAN-23

2.0SCH-PESEB-001

Tony Tran Derek Huang

Tue Aug 10 13:51:12 2010 SHEET 22 OF 52

MTG2MTG1

7654321

J57

MTG2MTG1

7654321

J56

5 4

32

1

J74

54

3 2

1

J72

R632

R629

R627

R623

R625

R621

R619

R617

R613

R615

R611

R609

R607

R605

R603

R634

R631

R628

R626

R624

R622

R620

R618

R616

R614

R612

R610

R608

R606

R604

R602

R586

C148C149C150C151C152C153C154C155

C156C157C158C159C160C161C162C163

R585

R584

R568

R567

R566

R550

R549

R548

R532

R531

R530

R514

R513

R512

R503

R504

R511

R505

C147

C146

C144

C145

C143

C142

C141

C139

C140

C138

R50298

7

6

5

48

47464544

4342

4140

4

3938

3736

35343332

3130

3

29282726

2524

23222120

2

1918

17161514

13

12

11

10

1

U18

9

8

7

6

5

43

202

19

1817

1615

141312

1110

1

U17

C137

C136

R501

R652

R648

R653

R650

R645R647

TP129

R499

R500

C135

MTG2MTG1

7

65

4 321

J62

R498

R497

R496

98107116125134143152161

S20

768594103112121

S19

25

25

22

22

22

22

25

25

22

22

22 44

22

22

22

22

22 44

22

22

25

25

25

25

6

6

22 44

49

49

P8SH16_CLKPP8SH16_CLKN

P8SATA_CLK1N

P8SATA_CLK2NP8SMA_CLKPP8SMA_CLKN

P8SH4_CLKN

P8SH4_CLKP

P8SATA_CLK2P

P8SATA_CLK1P

P8_OEB3

470

221789-0

CONNSMAP8_SATARSTN

221789-0

CONNSMA

P8SMA_CLKNP8SMA_CLKP

P8SATA_CLK2PP8SATA_CLK2N

P8_SATARSTN

P8SATA_CLK1PP8SATA_CLK1N

0.1UF

P8SH2_CLKN

P8SH2_CLKPP8SH0_CLKN

P8SH0_CLKPP08CLKNP08CLKP0.1UF

P8JA_PLL_SEL

P8ECLK_ENABLE

P8ECLK_SEL

P8JA_BW_SEL

P8JA_FSEL0P8_OEB1P8_OEB2P8_OEB3

P8_OEB0P8_OEA3

P8_OEA0

P8_OEA2P8_OEA1

P8_SATARSTN

P8_SATACLKPP8_SATACLKN

P8JA_PLL_SELP8JA_BW_SEL

P8JA_FSEL0

P8ECLK_ENABLE

LP8_CLKN

P8ECLK_SEL

P8_OEB2

P8_OEB0P8_OEB1

LP8_CLKP

P8_OEA1P8_OEA2P8_OEA3

P8_OEA0

4.7K

4.7K

4.7K

0.1UF

4.7K

4.7K

+3V3

YEL

0

0

DNP

DNP

DNP

DNP

+3V3

0603 5%

10

0.1UF

+3V3

10UF

+3V3

100

0.1UF

0.1UF

0.1UF

+3V3

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

180

180

DNP

DNP

+3V3

180

180

180

180

180

180

180

180

180

180

180

180

180

180

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

56

470

470

470

470

470

470

470

470

470

470

+3V3

470

470

470

470

470

CLOCK SELECTOR DUT PCLK 8

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

678005005

3

21

4

7

MTG1

MTG2

5

6

ININ

ICS853S1208I

OEA1

QB2

VCC

QB3

OEA2

nCLK1

OEA3

QB0

VEE

QA2

nQA2

QA3

nQA3

VCC

nQB3

nQB2

VEE

VCC

OEB0

OEB1

VEE

DIV_SELA

VCC

VCC

nQB1

VCC

OEA0

VCC

CLK1

OEB2

OEB3

VCC

VEE

QA0

CLK0

QB1

nQA0

NC

VEE

VCC

nQA1

QA1

VEE

VCC

CLK_SEL

nCLK0

nQB0

DIV_SELB

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

ICS874001I-02

NC

NC

PLL_SEL

NC

F_SEL0

VDDO

GND

NC

NCBW_SEL

nQ

Q

NC

nCLK

CLK

OE

VDDA

MRF_SEL1

VDD

OUT

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

IN678005005

MTG2

MTG1

7

6

5

4

3

2

1

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

IN

IN

ININ

IN

IN

OUTOUT

OUT

OUTOUT

OUTOUTOUT

OUTOUT

OUTOUT

OUTOUT

OUTOUT

U16 OUTPUTS

ON (DISABLE)

C85 CLOSE TO VDDA

OFF (ENABLE)

PLACE R367 CLOSE TO U16

P16SHXXCLK - TO SLOT CLK HEADERS

P16CLK - DUT PORT 16 CLK

PLACE 470 AND 56 OHM RESISTORS CLOSE TO DESTINATION.

LP16CLK - LOCAL CLOCK GEN. PORT 16 CLK

DEFAULT DIPSW SETTING

S17:5 OFF (U15 OUTPUT ON)

S17:3 OFF (PLL)S17:4 OFF (2.2MHZ)

S17:6 ON (100MHZ)

S17:1 OFF (SATACLK)

2010 Tue Aug 10 13:51:21 2010 SHEET 23 OF 52

Derek HuangTony Tran

B SCH-PESEB-001 18-691-001 2.0

EB-LOGAN-23

+3V3

R657

5 4

32

1

J55

54

3 2

1

J54

MTG2MTG1

7654321

J42

MTG2MTG1

7654321

J41

98

7

6

5

48

47464544

4342

4140

4

3938

3736

35343332

3130

3

29282726

2524

23222120

2

1918

17161514

13

12

11

10

1

U16

R470

R466

R468

R464

R460

R462

R458

R456

R454

R452

R450

R446

R448

R444

R442

R440

C215

C218

C216C217

C219C220

R471

R469

R467

R465

R463

R461

R457

R459

R455

R453

R451

R449

R447

R445

R443

R441

C221C222

C224C223

C131

C225C130

C132C133C134

R439

R438

R437

R436

R435

R434

R431

R430

R429

R761

R428

R760

R407

R406

R405

R369

R368

R367

R404

C212

C213

C214

C209

C210

C211

C207

C208

C205

C206

C204

C203

R366

C202

9

8

7

6

5

43

202

19

1817

1615

141312

1110

1

U15

R638

R640

R635R636

R643

R639

TP131MTG2MTG1

7

65

4 321

J64

98107116125134143152161

S18

R759

R654

R655

R656

768594103112121

S17

P16CLKP

P16SH12_CLKN

P16SMA_CLKP

DNP

P16_OEB3

LP16_CLKN

+3V3

P16SH6_CLKN

P16SH20_CLKN

P16SMA_CLKN

56

56

P16SATA_CLK2N

10UF

LP16_CLKP

56

23

23

25

23

23

23

23

25

6

6

23

23 44

23

23

23 44

23

23

23

25

25

25

25

25

25

23 44

51

51

+3V3

+3V3

+3V3

+3V3

+3V3

P16SH20_CLKP

P16SATA_CLK2PP16SATA_CLK1NP16SATA_CLK1P

P16CLKN

470

CONNSMA

P16SMA_CLKP

221789-0

P16_SATARSTN

P16SATA_CLK1NP16SATA_CLK1P

P16_SATARSTN

P16SATA_CLK2NP16SATA_CLK2P

P16SMA_CLKN

221789-0

CONNSMA

P16SH12_CLKPP16ECLK_SEL

P16_OEA2P16_OEA1P16_OEA0

0.1UF

56

56

P16SH8_CLKNP16SH8_CLKP

P16SH6_CLKP0.1UF

0.1UF

0.1UF

0.1UF

56

P16_SATACLKP

P16JA_PLL_SEL

P16ECLK_SEL

P16ECLK_ENABLEP16JA_BW_SEL

P16JA_FSEL0

P16_OEB0P16_OEB1P16_OEB2P16_OEB3

P16_OEA1P16_OEA2P16_OEA3

P16_OEA0

P16_SATACLKN

P16_SATARSTN

P16JA_PLL_SELP16JA_BW_SEL

P16ECLK_ENABLE

P16JA_FSEL0

P16_OEB0P16_OEB1P16_OEB2

P16_OEA3

4.7K

4.7K

4.7K

4.7K

4.7K

YEL

DNP

DNP

0

0 DNP

DNP

0.1UF

0603

10

5%

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

180

100

DNP

180

180

180

180

180

180

180

180

180

180

180

180

180

180

180

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

56

56

56

56

56

56

56

56

56

56

0.1UF

0.1UF

0.1UF

470

470

470

470

470

470

470

470

470

470

470

470

470

470

470

CLOCK SELECTOR DUT PCLK 16

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

ININ

ICS874001I-02

NC

NC

PLL_SEL

NC

F_SEL0

VDDO

GND

NC

NCBW_SEL

nQ

Q

NC

nCLK

CLK

OE

VDDA

MRF_SEL1

VDD

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

ININ

678005005

MTG2

MTG1

7

6

5

4

3

2

1

ININ

IN

OUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

ININ

IN

ICS853S1208I

OEA1

QB2

VCC

QB3

OEA2

nCLK1

OEA3

QB0

VEE

QA2

nQA2

QA3

nQA3

VCC

nQB3

nQB2

VEE

VCC

OEB0

OEB1

VEE

DIV_SELA

VCC

VCC

nQB1

VCC

OEA0

VCC

CLK1

OEB2

OEB3

VCC

VEE

QA0

CLK0

QB1

nQA0

NC

VEE

VCC

nQA1

QA1

VEE

VCC

CLK_SEL

nCLK0

nQB0

DIV_SELB

OUTOUTOUTOUTOUTOUT

OUTOUT

OUTOUT

OUTOUT

OUT

OUTOUT

OUT

678005005

3

21

4

7

MTG1

MTG2

5

6

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

SHXXCLK - SLOT HDR. CLK

PXXCLK - DUT CLK

LPXXLCK - LOCAL CLOCK GEN. PORT CLK

Thu Jul 01 15:00:59 2010 SHEET 24 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R144

R146

R143

R145

R106

R118

R117

R105

R323

R321

R326

R332

R325

R331

R324

R322

R320

R151

R319

R152

R149

R147

R150

R148

R329

R335

R336

R330

R333

R327

R328

R334

MTG2MTG1

7654321

J21

54

3 2

1

J67

5 4

32

1

J66

MTG2MTG1

7654321

J22

54

3 2

1

J20

98765432

10

1

J18

98765432

10

1

J19

5 4

32

1

J17

TP126

TP125

TP127

MTG2MTG1

7

65

4 321

J58

MTG2MTG1

7

65

4 321

J59

654321

J9

654321

J10

654321

J11

MTG2MTG1

7

65

4 321

J60

TP128

TP130

MTG2MTG1

7

65

4 321

J61

MTG2MTG1

7

65

4 321

J63

TP132MTG2MTG1

7

65

4 321

J65

654321

J12

654321

J14

654321

J16

24

24

24

24

24

24

21

24

24

47

46

45 45

46

47

48 48

50 50

52 52

24

6 6

6 6

6 6

6 6

6 6

6 6

24

24

24 24

24 24

24 24

24

24

24

24

24

7

24

21

7

7

24

24

24

21

7

24

24

24

21

24

24

24

YEL

YELP20_SATARSTN

P20_SATACLKNP20_SATACLKP

P12_SATACLKN

P4_SATACLKP

P2_SATARSTN

P2_SATACLKP

P0_SATARSTN

P2_SATACLKN

BGCLK1P

P12_SATACLKP

P0_SATACLKPP0_SATACLKN

P2_SATACLKPP2_SATACLKN

P4_SATACLKPP4_SATACLKN

P6_SATACLKPP6_SATACLKN

P12_SATACLKPP12_SATACLKN

P20_SATACLKPP20_SATACLKN

DNP

DNP

DNP

DNP

+3V3

DNP

DNP

DNP

DNP

+3V3

DNP

DNP

DNP

+3V3

DNP

DNP

DNP

DNP

+3V3

DNP

DNP

DNP

DNP

+3V3

DNP

DNP

DNP

DNP

+3V3

DNP

P2_SATACLKP

LP4_CLKP

LP2_CLKP

LP0_CLKP LP0_CLKN

LP2_CLKN

LP4_CLKN

LP6_CLKNLP6_CLKP

LP12_CLKP LP12_CLKN

LP20_CLKNLP20_CLKP

VERT-SM

P0_SATACLKP

P00CLKP P00CLKN

P20CLKP P20CLKN

P12CLKNP12CLKP

P06CLKNP06CLKP

P04CLKNP04CLKP

P02CLKNP02CLKP

P4_SATACLKP

P2_SATACLKN

VERT-SM

NO-SHROUDVERT-SM 2.00MM

P20_SATACLKP P20_SATACLKN

NO-SHROUDVERT-SM 2.00MM

P12_SATACLKP P12_SATACLKN

NO-SHROUDVERT-SM 2.00MM

P6_SATACLKP P6_SATACLKN

NO-SHROUDVERT-SM 2.00MM

P4_SATACLKN

NO-SHROUD2.00MM

NO-SHROUD2.00MM

P0_SATACLKN

P6_SATACLKP

P0_SATACLKN

P12_SATARSTN YEL

DNP

DNP

+3V3

DNP

DNP

+3V3

DNP

DNP

DNP

DNP

221789-0

G1_SATACLKP

GCLK1P

G0_SATACLKP

BGCLK0P

GCLK0P

GCLK1N

G1_SATACLKNG1_SATACLKP

G0_SATACLKN

BGCLK0N

GCLK0N

G0_SATACLKNG0_SATACLKP

G1_SATACLKN

BGCLK1N

221789-0

CONNSMA

CONNSMA

221789-0

CONNSMA

NO-SHROUD2.00MMVERT-SM

221789-0

CONNSMA

VERT-SM 2.00MMNO-SHROUD

CLOCK SELECTOR DUT PCLK 0-20, GCLK 0-1

YEL

YEL

YEL

P0_SATACLKP

P4_SATARSTN

P4_SATACLKN

P6_SATARSTN

P6_SATACLKN

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUTOUT

INOUT

678005005

3

21

4

7

MTG1

MTG2

5

6

678005005

3

21

4

7

MTG1

MTG2

5

6

IN

OUTIN

IN

INOUTIN

HDR_2X31

3

5

2

4

6

HDR_2X31

3

5

2

4

6

HDR_2X31

3

5

2

4

6

OUTIN

IN

OUTIN

IN

IN

INOUT

678005005

3

21

4

7

MTG1

MTG2

5

6

OUTOUT

OUTOUT

OUT

678005005

3

21

4

7

MTG1

MTG2

5

6OUTIN

OUT

IN

678005005

3

21

4

7

MTG1

MTG2

5

6OUT

HDR_2X31

3

5

2

4

6

IN

IN

OUT

OUT

678005005

3

21

4

7

MTG1

MTG2

5

6

IN

IN

IN

HDR_2X31

3

5

2

4

6

HDR_2X31

3

5

2

4

6

OUTIN

IN

OUTOUT

OUT

OUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

OUT

OUTOUT

IN

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

OUT

IN

IN

HDR_2x5

109

87

65

1 2

3 4

HDR_2x5

109

87

65

1 2

3 4

IN

IN

OUT

IN

IN

OUTOUT

OUTOUT

IN

IN

SXXCLK - SLOT CLK

LSXXCLK - LOCAL CLOCK GEN. SLOT CLK

BSXXLCK - BUFFER SLOT CLK

SHXXCLK - SLOT HDR.CLK

Thu Jul 01 15:00:59 2010 SHEET 25 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

TP93

TP94

TP95

MTG2MTG1

7654321

J35

98765432

121110

1

J31

MTG2MTG1

7654321

J36

MTG2MTG1

7654321

J37

98765432

121110

1

J32

98765432

121110

1

J33

TP89

TP90

TP91

TP96

MTG2MTG1

7654321

J38

98765432

121110

1

J34TP92

MTG2MTG1

7654321

J27

98765432

121110

1

J23

MTG2MTG1

7654321

J28

MTG2MTG1

7654321

J29

98765432

121110

1

J24

98765432

121110

1

J25

MTG2MTG1

7654321

J30

98765432

121110

1

J26

25 25

23 23

21 21

48 48 44

25

25

3

25

22

3

21

47

25

22

21

2

46

25

22

2

21

45

25

22

21

47

25

22

21

46

3

3

44

25

25

2

44

25

25

25

22

21

45

2

44

25

25

25

23

21

5

52

21

22

25

5

51

25

25

25

44

23

21

4

50

25

4

21

23

25

23

21

52

25

22

21

51

25

23

21

50

5

44

25

25

5

44

25

25

25

23

21

4

44

25

25

4

49 49

S6_SATACLKP S6_SATACLKN

P16SH6_CLKNP16SH6_CLKPBS06CLKNBS06CLKP

LS6_CLKP LS6_CLKNS6_SATA_WAKES6_SATA_RSTN

S6_SATACLKNS6_SATACLKP

S6_CLKP

S4_SATACLKP

P8SH4_CLKP

S4_CLKPBS04CLKP

LS4_CLKP

S2_SATACLKP

P8SH2_CLKPBS02CLKPS2_CLKPLS2_CLKP

S0_SATACLKP

P8SH0_CLKP

S0_CLKPBS00CLKP

LS0_CLKP

S4_SATACLKN

P8SH4_CLKNBS04CLKN

LS4_CLKN

S2_SATACLKN

P8SH2_CLKNBS02CLKN

LS2_CLKN

S6_CLKN

S4_CLKN S4_SATA_WAKES4_SATA_RSTN

S4_SATACLKNS4_SATACLKP

S2_CLKN S2_SATA_WAKES2_SATA_RSTN

S2_SATACLKNS2_SATACLKP

S0_SATACLKN

P8SH0_CLKNBS00CLKN

LS0_CLKNS0_CLKN

S20_SATA_WAKES20_SATA_RSTN

S20_SATACLKNS20_SATACLKP

S20_SATACLKP

P16SH20_CLKPBS20CLKPS20_CLKPLS20_CLKP

BS16CLKPP8SH16_CLKP

S16_SATACLKP

S16_CLKPLS16_CLKP

S12_SATACLKP

S0_SATACLKPS0_SATACLKN

S0_SATA_RSTNS0_SATA_WAKE

P16SH12_CLKPBS12CLKPS12_CLKPLS12_CLKP

S8_SATACLKP

S8_CLKPBS08CLKPP16SH8_CLKP

S20_SATACLKN

P16SH20_CLKNBS20CLKN

LS20_CLKN

S16_SATACLKN

P8SH16_CLKNBS16CLKN

LS16_CLKN

S12_SATACLKN

P16SH12_CLKNBS12CLKN

LS12_CLKN

S20_CLKN

S16_SATA_WAKES16_SATA_RSTN

S16_SATACLKNS16_SATACLKP

S16_CLKN

S12_SATA_WAKES12_SATA_RSTN

S12_SATACLKNS12_SATACLKP

S8_SATACLKN

P16SH8_CLKNBS08CLKN

S12_CLKN

S8_SATA_RSTN

S8_SATACLKNS8_SATACLKP

S8_SATA_WAKE

S8_CLKN

NO-SHROUD2.00MMVERT-SM

VERT-SMNO-SHROUD2.00MM

2.00MMVERT-SMNO-SHROUD

NO-SHROUD2.00MMVERT-SM

DNP

DNP

DNP

DNP 2.00MMVERT-SMNO-SHROUD

VERT-SM 2.00MMNO-SHROUD

2.00MMNO-SHROUD

VERT-SM

NO-SHROUDVERT-SM 2.00MM

DNP

DNP

DNP

DNP

LS8_CLKP LS8_CLKN

CLOCK SELECTOR SLOTS 0-20

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

OUTININ

OUTOUT

OUT

IN

OUTIN

ININ

IN

OUTIN

ININ

IN

IN

OUTOUT

OUT

OUTOUT

OUT

OUT

IN

OUT

OUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

IN

IN

OUT

HDR_2x6

1211

109

87

65

1 2

3 4

IN

HDR_2x6

1211

109

87

65

1 2

3 4INOUTININ

IN

OUT

OUTIN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

INOUTININ

IN

HDR_2x6

1211

109

87

65

1 2

3 4

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

OUT

OUT

ININ

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

INOUT

ININ

IN

IN

HDR_2x6

1211

109

87

65

1 2

3 4

HDR_2x6

1211

109

87

65

1 2

3 4

INOUTININ

IN

INOUTIN

IN

IN

IN

INOUTIN

IN

OUTOUT

OUT

OUT

IN

OUT

OUT

OUTOUT

OUT

OUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

IN

OUT

ININ

HDR_2x6

1211

109

87

65

1 2

3 4

678005005

MTG2

MTG1

7

6

5

4

3

2

1

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

IN

IN

OUT

IN

IN

HDR_2x6

1211

109

87

65

1 2

3 4

IN

ININ

OUT

IN

HDR_2x6

1211

109

87

65

1 2

3 4

OUT

IN

RIGHT ANGLED

USE W28/W29 FOR LIGHTLYLOADED SYSTEMS

GND TEST POINTS

+12.0V -> +3.3V

RIGHT ANGLED

SCATTER AROUND BOARD

WITH ONLY 24-PIN CONNECTORPOPULATE W28/W29 FOR POWER SUPPLIES

Thu Jul 01 15:01:00 2010 SHEET 26 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS

4R

337

C367

C364

C362

C360

C358

C356

C354

C352

C350

C348

C346

C344

C342

C340

C337

C334

C332

TP28TP29

C369

C366

5

7

6

8

2

9

101

1143

VR1

R509

C339

C336

TP

32

TP

31

TP

30

C330

C328

C326

C324

C322

R506

23

1U98

54

23

1

S1

W27

R508

R507

DS

2

DS

1

C321

C320

W28

W29

TP

27

TP

26

TP

25

TP

24

TP

23

TP

22

C319

C318

TP

21

TP

20

TP19TP18TP17

8

16

24

191817

15

7

5

3

20

14

9

232221

6

4

13

12

21

1110

J69

C317

C316

C315

8765

4321

J68

TP16

42

+3V3_PS

0.1UF

GRN

150

GRN

150

GRN

1.21K

+12V3_PS

47UF

+12V1_PS

WHT

DNP

25V

25V

DNP

PS_ENABLEN

+3V3_PS

POWER CONNECTORS

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

+3V3

YEL

YEL

220UF

10V

47UF

1%

060322UF

25V

22UF

25V

WHT

WHT

WHT

0.1UF

0.1UF

47UF

47UF

47UF

+5V0_PS

1K

5%0603

+3V3_PS

+12V3_PS

+5V0_PS

330

25V

22UF

+12V2_PS

WHT

WHT

WHT

WHT

WHT

10UF

10UF

WHT

WHT

0039291247

47UF

22UF

25V

10UF

+12V3_PS

0039301080

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

PTH08T240WAD

SYNC

Vout

VO_SEN-

Vin VO_SEN+

TURBOTRANS

Track

GND2

GND1Vo_Adj

Inhibit

OUT

MMBT3904

C

E

B

SPDT_TGLON

OFFB

A

MTG1MTG2

COM

POWER 8-PIN

P12V22

P12V21

P12V12

P12V11

GND4

GND3

GND2

GND1

+3.3V_4-12V_1

GND_4PS-ONGND_5

+3.3V_3+12V3_2+12V3_1+5VAB

GND_8+5V_5+5V_4

+5V_2GND_2+5V_1GND_1+3.3V_2+3.3V_1

GND_3PWROK

+5V_3-5V

GND_7GND_6

------------------------------

------------------------------

------------------------------HIGH | HIGH | NO MARGIN

MARG1 | MARG0 | MODE

------------------------------LOW | LOW | NO MARGIN

LOW | HIGH | MARGIN UP

HIGH | LOW | MARGIN DOWN

PLACE W33 CLOSE TO J112

MARGINING CONTROL

1%

2%

4%

8%

ROUTE AS POWER NET OR ISLAND

VDD_IO, 3.3V

PLACE R526 & R527 CLOSE TO U57, NOISE-FREE ROUTINGPLACE R528 & R529 CLOSE TO U1, NOISE-FREE ROUTING

PLACE CLOSE TO U1

Thu Jul 01 15:01:00 2010 SHEET 27 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

1

J78

1

J79

C396

C395

FB5

C394

C392

C391

C390

C389

C388

C387

R528R529R527

R526

C386

R525

C385

C384

R524

R523

TP37

R516

R515

W33

C381

C380

TP38

C383

R519

R518R517

R522

R521R520

R1390

R1389

768594103112121

S9

L12

J9J8J7J6J5

M11M10M9M8

J4

M7M6M5M4M3M2M1L11L10L9

J3

L8L7L6L5L4L3L2L1K11K10

J2

K9K8K7K6K5K4K3K2K1J10

J1

J12M12

B3B2B1A6A5A4A3A2

C6C5C4C3C2C1B6B5B4

A1

F12

A9

H12

A10

A8

G12

A12

D12C12

A7

E3E2E1D6D5

H9

D4

H8H7H6H5H4H3H2H1G9G8

D3

G7G6G5G4

G3G2G1F9F8F7

D2

F6F5F4F3F2F1E7E6E5E4

D1

B12

E12

K12

A11

U56 POWER REGULATOR - VDDIO

10UF

0

100UF

16V

51.1K

18.2K

100PF

191K

+3V3_IO

BLK

1.0UF

RED

PS_IO_MARG0

PS_IO_MARG1

PS_IO_CTRL2

PS_IO_CTRL1

PS_IO_CTRL0

PS_IO_CTRL3

REG_2V5_VDDIO10K

10K

1.96M

1.96M

1.96M

487K

487K

487K

DNP

DNP

+3V3

10UF

10UF

100K

100K

DNP

+3V3

+12V3_PS

0.01UF

0

0

0

47UF

47UF

47UF

47UF

1.0UF

1.0UF

0.1UF

26NH

6.5A

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

LTM4603

GND40

GND39

GND38

VIN18

VIN17

VIN16

VIN15

VIN14

VIN13

VOSNSN

VOUT43

VOUT42

VOUT41

VOUT40

VOUT39

VOUT38

VOUT37

VOUT36

VOUT35

VOUT34

VOUT33

VOUT_LCL

VOUT32

VOUT31

VOUT30

VOUT29

VOUT28

VOUT27

VOUT26

VOUT25

VOUT24

VOUT23

VOUT22

DIFFVOUT

VOUT21

VOUT20

VOUT19

VOUT18

VOUT17

VOUT16

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOSNSP

VOUT10

VOUT9

VOUT8

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

SGND

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

PGOOD

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22

VFB

GND21

GND20

GND19

GND18

GND17

GND16

GND15

GND14

DRVCC

GND13

GND12

GND11

GND10

GND9

GND8

GND7

MARG1

GND6

GND5

GND4

GND3

GND2

GND1

MARG0

FSET

VIN12

VIN11

VIN10

VIN9

VIN8

VIN7

MPGM

COMP

RUN

TRACK/SS

PLLIN

INTVCC

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

CONN BANANA

CONN BANANA

ROUTE AS POWER NET OR ISLAND

PLACE R546 & R547 CLOSE TO U1, NOISE-FREE ROUTINGPLACE R544 & R545 CLOSE TO U57, NOISE-FREE ROUTING

VDD_CORE, 1.0V

PLACE CLOSE TO U1

8%

4%

2%

1%

PLACE W34 CLOSE TO J114

MARGINING CONTROL

HIGH | HIGH | NO MARGIN

MARG1 | MARG0 | MODE------------------------------

------------------------------

------------------------------

------------------------------

LOW | LOW | NO MARGIN

LOW | HIGH | MARGIN UP

HIGH | LOW | MARGIN DOWN

Thu Jul 01 15:01:00 2010 SHEET 28 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

1

J114

1

J113

FB6

C413

C412

C411

C409

C408

C407

R546R547

C406

C405

C404

R544R545

R534

R533

C398

C397

C403

C401

R543

R542

R541

TP41

TP42

C400

C402

L12

J9J8J7J6J5

M11M10M9M8

J4

M7M6M5M4M3M2M1L11L10L9

J3

L8L7L6L5L4L3L2L1K11K10

J2

K9K8K7K6K5K4K3K2K1J10

J1

J12M12

B3B2B1A6A5A4A3A2

C6C5C4C3C2C1B6B5B4

A1

F12

A9

H12

A10

A8

G12

A12

D12C12

A7

E3E2E1D6D5

H9

D4

H8H7H6H5H4H3H2H1G9G8

D3

G7G6G5G4

G3G2G1F9F8F7

D2

F6F5F4F3F2F1E7E6E5E4

D1

B12

E12

K12

A11

U59

W34

R1391

R1392

R535R536

R537

R539R538

768594103112121

S6

R540

100UF

16V

0

PS_CORE_CTRL1

PS_CORE_CTRL0

PS_CORE_CTRL3

PS_CORE_CTRL2

PS_CORE_MARG1

PS_CORE_MARG0

REG_1V0_CORE

1.96M

1.96M

1.96M

487K

487K

487K

10K

10K

0.01UF

DNP

DNP

DNP

1%

127K

1%

316K

191K

100PF

+3V3

10UF

10UF

100K

100K

+3V3

+12V3_PS

0

47UF

47UF

47UF

0

0

47UF

1.0UF

1.0UF

0.1UF

10UF

1.0UF

6.5A

26NH

BLK

RED

+1V0_CORE

POWER REGULATOR - VDDCORE

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

CONN BANANA

CONN BANANA

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

LTM4603

GND40

GND39

GND38

VIN18

VIN17

VIN16

VIN15

VIN14

VIN13

VOSNSN

VOUT43

VOUT42

VOUT41

VOUT40

VOUT39

VOUT38

VOUT37

VOUT36

VOUT35

VOUT34

VOUT33

VOUT_LCL

VOUT32

VOUT31

VOUT30

VOUT29

VOUT28

VOUT27

VOUT26

VOUT25

VOUT24

VOUT23

VOUT22

DIFFVOUT

VOUT21

VOUT20

VOUT19

VOUT18

VOUT17

VOUT16

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOSNSP

VOUT10

VOUT9

VOUT8

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

SGND

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

PGOOD

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22

VFB

GND21

GND20

GND19

GND18

GND17

GND16

GND15

GND14

DRVCC

GND13

GND12

GND11

GND10

GND9

GND8

GND7

MARG1

GND6

GND5

GND4

GND3

GND2

GND1

MARG0

FSET

VIN12

VIN11

VIN10

VIN9

VIN8

VIN7

MPGM

COMP

RUN

TRACK/SS

PLLIN

INTVCC

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

MARGINING CONTROL

1%

------------------------------

HIGH | HIGH | NO MARGIN

MARG1 | MARG0 | MODE------------------------------

------------------------------

------------------------------

LOW | LOW | NO MARGIN

LOW | HIGH | MARGIN UP

HIGH | LOW | MARGIN DOWN

PLACE W35 CLOSE TO J115

2%

4%

8%

ROUTE AS POWER NET OR ISLAND

PLACE CLOSE TO U1

VDD_PEA, 1.0V

PLACE R562 & R563 CLOSE TO U60, NOISE-FREE ROUTINGPLACE R564 & R565 CLOSE TO U1, NOISE-FREE ROUTING

Thu Jul 01 15:01:00 2010 SHEET 29 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

1

J115

FB7

C429

C430

C428

C426

C425

C424

C423

C422

C421

R564R565

C420

R562R563

R561

C419

R560

TP45

R552

R551

C418

R559

TP46

W35

C417

R553

R555

R554

R556R557

C415

C414

R1394

R1393

768594103112121

S7

R558

L12

J9J8J7J6J5

M11M10M9M8

J4

M7M6M5M4M3M2M1L11L10L9

J3

L8L7L6L5L4L3L2L1K11K10

J2

K9K8K7K6K5K4K3K2K1J10

J1

J12M12

B3B2B1A6A5A4A3A2

C6C5C4C3C2C1B6B5B4

A1

F12

A9

H12

A10

A8

G12

A12

D12C12

A7

E3E2E1D6D5

H9

D4

H8H7H6H5H4H3H2H1G9G8

D3

G7G6G5G4

G3G2G1F9F8F7

D2

F6F5F4F3F2F1E7E6E5E4

D1

B12

E12

K12

A11

U62

16V

100UF

PS_PEA_CTRL0

PS_PEA_CTRL1

PS_PEA_MARG1

PS_PEA_MARG0

PS_PEA_CTRL3

PS_PEA_CTRL2

REG_1V0_PEA

1.96M

10K

10K

+3V3

10UF

10UF

1.96M

1.96M

487K

487K

487K

DNP

DNP

127K

1%

100PF

100K

100K

DNP

+3V3

+12V3_PS

316K

1%

0.01UF

191K

0

0

0

0

47UF

47UF

47UF

47UF

1.0UF

1.0UF

0.1UF

1.0UF

10UF

6.5A

26NH

RED

+1V0_PEA

POWER REGULATOR - VDDPEA

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

CONN BANANA

LTM4603

GND40

GND39

GND38

VIN18

VIN17

VIN16

VIN15

VIN14

VIN13

VOSNSN

VOUT43

VOUT42

VOUT41

VOUT40

VOUT39

VOUT38

VOUT37

VOUT36

VOUT35

VOUT34

VOUT33

VOUT_LCL

VOUT32

VOUT31

VOUT30

VOUT29

VOUT28

VOUT27

VOUT26

VOUT25

VOUT24

VOUT23

VOUT22

DIFFVOUT

VOUT21

VOUT20

VOUT19

VOUT18

VOUT17

VOUT16

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOSNSP

VOUT10

VOUT9

VOUT8

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

SGND

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

PGOOD

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22

VFB

GND21

GND20

GND19

GND18

GND17

GND16

GND15

GND14

DRVCC

GND13

GND12

GND11

GND10

GND9

GND8

GND7

MARG1

GND6

GND5

GND4

GND3

GND2

GND1

MARG0

FSET

VIN12

VIN11

VIN10

VIN9

VIN8

VIN7

MPGM

COMP

RUN

TRACK/SS

PLLIN

INTVCC

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

LOW | HIGH | MARGIN UP

HIGH | HIGH | NO MARGIN

MARG1 | MARG0 | MODE------------------------------

------------------------------

------------------------------

------------------------------

LOW | LOW | NO MARGIN

HIGH | LOW | MARGIN DOWN

MARGINING CONTROL

PLACE W36 CLOSE TO J116

1%

2%

4%

8%

PLACE CLOSE TO U1

VDD_PEHA, 2.5V

ROUTE AS POWER NET OR ISLAND

PLACE R580 & R581 CLOSE TO U63, NOISE-FREE ROUTINGPLACE R582 & R583 CLOSE TO U1, NOISE-FREE ROUTING

Thu Jul 01 15:01:01 2010 SHEET 30 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

C447

1J116

C446

FB8

C445

C443

C442

C441

C440

C439

C438

TP49

R582R583R581

R580

C435

C437

R579

R578

R577

C436

TP50

C434

L12

J9J8J7J6J5

M11M10M9M8

J4

M7M6M5M4M3M2M1L11L10L9

J3

L8L7L6L5L4L3L2L1K11K10

J2

K9K8K7K6K5K4K3K2K1J10

J1

J12M12

B3B2B1A6A5A4A3A2

C6C5C4C3C2C1B6B5B4

A1

F12

A9

H12

A10

A8

G12

A12

D12C12

A7

E3E2E1D6D5

H9

D4

H8H7H6H5H4H3H2H1G9G8

D3

G7G6G5G4

G3G2G1F9F8F7

D2

F6F5F4F3F2F1E7E6E5E4

D1

B12

E12

K12

A11

U65

C432

C431

R570

R569

W36

R1396

R1395

R571R572

R573

R574R575

R576

768594103112121

S8

+3V3

+3V3

+12V3_PS

+2V5_PEHA

16V

100UF

PS_PEHA_MARG1

PS_PEHA_MARG0

PS_PEHA_CTRL3

PS_PEHA_CTRL0

PS_PEHA_CTRL1

PS_PEHA_CTRL2

REG_2V5_PEHA

1.96M

1.96M

1.96M

487K

487K

487K

10K

10K

100K

100K

10UF

10UF

DNP

DNP

0.01UF

42.2K

34.8K

DNP

100PF

0

0 0

0

DNP

47UF

47UF

47UF

47UF

1.0UF

1.0UF

0.1UF

6.5A

26NH

10UF

RED

1.0UF

POWER REGULATOR - VDDPEHA

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

CONN BANANA

LTM4603

GND40

GND39

GND38

VIN18

VIN17

VIN16

VIN15

VIN14

VIN13

VOSNSN

VOUT43

VOUT42

VOUT41

VOUT40

VOUT39

VOUT38

VOUT37

VOUT36

VOUT35

VOUT34

VOUT33

VOUT_LCL

VOUT32

VOUT31

VOUT30

VOUT29

VOUT28

VOUT27

VOUT26

VOUT25

VOUT24

VOUT23

VOUT22

DIFFVOUT

VOUT21

VOUT20

VOUT19

VOUT18

VOUT17

VOUT16

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOSNSP

VOUT10

VOUT9

VOUT8

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

SGND

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

PGOOD

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22

VFB

GND21

GND20

GND19

GND18

GND17

GND16

GND15

GND14

DRVCC

GND13

GND12

GND11

GND10

GND9

GND8

GND7

MARG1

GND6

GND5

GND4

GND3

GND2

GND1

MARG0

FSET

VIN12

VIN11

VIN10

VIN9

VIN8

VIN7

MPGM

COMP

RUN

TRACK/SS

PLLIN

INTVCC

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

------------------------------

------------------------------

------------------------------

------------------------------

MARGINING CONTROL

LOW | HIGH | MARGIN UP

HIGH | HIGH | NO MARGIN

MARG1 | MARG0 | MODE

LOW | LOW | NO MARGIN

HIGH | LOW | MARGIN DOWN

PLACE W37 CLOSE TO J117

2%

4%

8%

1%

ROUTE AS POWER NET OR ISLAND

PLACE CLOSE TO U1

VDD_PETA, 1.0V

PLACE R598 & R599 CLOSE TO U66, NOISE-FREE ROUTINGPLACE R600 & R601 CLOSE TO U1, NOISE-FREE ROUTING

Thu Jul 01 15:01:01 2010 SHEET 31 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

1J117

C463

C464

FB9

C462

C460

R588

R587

C449

C448

C459

C458

C457

R600R601

C456

C455

C454

R598R599

C452

TP53

TP54

W37

C451

R597

R596

C453

R595

L12

J9J8J7J6J5

M11M10M9M8

J4

M7M6M5M4M3M2M1L11L10L9

J3

L8L7L6L5L4L3L2L1K11K10

J2

K9K8K7K6K5K4K3K2K1J10

J1

J12M12

B3B2B1A6A5A4A3A2

C6C5C4C3C2C1B6B5B4

A1

F12

A9

H12

A10

A8

G12

A12

D12C12

A7

E3E2E1D6D5

H9

D4

H8H7H6H5H4H3H2H1G9G8

D3

G7G6G5G4

G3G2G1F9F8F7

D2

F6F5F4F3F2F1E7E6E5E4

D1

B12

E12

K12

A11

U68

R590R589

R591

R592R593

R594

R1398

R1397

768594103112121

S10

16V

100UF

PS_PETA_CTRL0

PS_PETA_MARG1

PS_PETA_CTRL1

PS_PETA_CTRL2

PS_PETA_CTRL3

PS_PETA_MARG0

REG_1V0_PETA

+3V3

10K

10K

1.96M

1.96M

1.96M

487K

487K

487K

1%

127K

0.01UF

1%

316K

191K

DNP

DNP

DNP

100PF

0

0

47UF

47UF

0

0

47UF

47UF

1.0UF

10UF

10UF

100K

+3V3

100K

+12V3_PS

1.0UF

0.1UF

6.5A

26NH

1.0UF

10UF

+1V0_PETA

RED

POWER REGULATOR - VDDPETA

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

CONN BANANA

SM_SW6

S1A

S6B

S5B

S4B

S3B

S2B

S1B

S6A

S5A

S4A

S3A

S2A

LTM4603

GND40

GND39

GND38

VIN18

VIN17

VIN16

VIN15

VIN14

VIN13

VOSNSN

VOUT43

VOUT42

VOUT41

VOUT40

VOUT39

VOUT38

VOUT37

VOUT36

VOUT35

VOUT34

VOUT33

VOUT_LCL

VOUT32

VOUT31

VOUT30

VOUT29

VOUT28

VOUT27

VOUT26

VOUT25

VOUT24

VOUT23

VOUT22

DIFFVOUT

VOUT21

VOUT20

VOUT19

VOUT18

VOUT17

VOUT16

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOSNSP

VOUT10

VOUT9

VOUT8

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

SGND

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

PGOOD

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22

VFB

GND21

GND20

GND19

GND18

GND17

GND16

GND15

GND14

DRVCC

GND13

GND12

GND11

GND10

GND9

GND8

GND7

MARG1

GND6

GND5

GND4

GND3

GND2

GND1

MARG0

FSET

VIN12

VIN11

VIN10

VIN9

VIN8

VIN7

MPGM

COMP

RUN

TRACK/SS

PLLIN

INTVCC

VIN6

VIN5

VIN4

VIN3

VIN2

VIN1

RESET

FUNDAMENTAL

SOCKETED (52-298-000)

BOOT EEPROM

JTAG

A0-2 INTERNALLY PULLED DOWN

Thu Jul 01 15:01:01 2010 SHEET 32 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

TP

61R646

R644

DS

3

C491

R662

R660

98765432

1413121110

1

J73

R661

872

56

431

U73

R642

C487

C489

R659

C499

R658

4

51

3

2

U72

TP

60

54

12

3

S3

R641

7

856

4

321

U77

R1335

R1333

R1334

R651

R649

J71

7

7

7 9 10 11 12 13 14

7 9 10 11 12 13 14

20

7

7

7

7

7

7 41 44 45 46 47 48 49 50 51 52

5%

SSMBDAT

SSMBCLK

5%

06031K

5%

06031K

+3V3

1K

1K

MOMSW_RSTN

MSMBCLKMSMBDAT

SATAIN_RSTN

DUT_JTAG_TRST_N

DUT_JTAG_TDI

DUT_JTAG_TDO

DUT_JTAG_TMS

DUT_JTAG_TCK

MAIN_RSTN

DNP

DNP

DNP

+3V3

+3V3

+3V3

YEL

0603

1%

DNP

0.1UF

06031K

5%

0.1UF

0.1UF

+3V3 +3V3

0603

5%

1K

+3V3

06031K

SHROUDVERT-TH 2.54MM

1K

0603

5%

+3V3

1K

5%

0603

+3V3

0.1UF

RED

1K

5%0603

+3V3

YEL

+3V3

RESET, SMBUS, EEPROM, JTAG

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

INBI

OUT

OUT

BI

HDR_2x7

1413

1211

109

87

65

1 2

3 4

TLC7733D

GNDRESETN

RESETVCC

CTCONTROLSENSERESINN

OUTOUTINBIBI

SN74LVC1G125

OE_N VCC

YGND

A

NC

SPDT_MOM

NO

COM

MTG2MTG1

A

B

24LC512

SCL

A2A1A0

SDA

WP

GND

VCC

MODE

STK03CFG

(GREEN) ACTIVE HIGH - DIP STK12CFG

(GREEN) ACTIVE HIGH - DIP STK03CFG

(GREEN) ACTIVE HIGH - DIP MODE

CLOCK

STK12CFG

(GREEN) ACTIVE HIGH - DIP CLOCK

Thu Jul 01 15:01:01 2010 SHEET 33 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R1365

R1364

R1366

R1367

DS109

R1363

R1362

R1361

R1360

R803

DS103

DS102R796

R797

910111213141516

87654321

SW10

DS104

DS105

DS106

DS108

DS107

R798

R799

R800

R801

R802

DS118

DS119

DS120

DS121

DS122

DS124

DS123

R812

R813

R814

R815

R816

R817

R818

DS110

DS111

DS112

DS114

DS113

DS116

DS115

R804

R805

R806

R807

R808

R809

R810

DS125

DS126

DS127

DS129

DS128

DS131

DS130

R819

R820

R821

R822

R823

R824

R825

R826 DS132

R1357

R1354

R1351

TP106

TP107

R1358

R1355

R1352

R1342

R1345

R1348

R1336

R1339

R1349

R1346

R1343

R1340

R1337

910111213141516

87654321

SW8

910111213141516

87654321

SW9

R1359

R1353

R1356

R1350

R1347

R1344

R1341

R1338

54637281

S4

54637281

S5

7 33

4 7 33

2 7 33

2 7 33

2 7 33

7 33

7 33

5 7 33

7 33

7 33

7 33

7 33

7 33

7 33

7 33

7 33

7 33

5 7 33

3 7 33

3 7 33

7 33

7 33

7 33

4 7 33

7 33

7 33

2 7 33

5 7 33

5 7 33

7 33

7 33

7 33

7 33

7 33

7 33

7 33

4 7 33

4 7 33

3 7 33

7 33

7 33

7 33

3 7 33

7 33

7 33

20 33

7 33

7 33

7 33

7 33

7 33

20 33

7 33

20 33

7 33

20 33

7 33

7 33

7 33

7 33

STK2CFG2

150

GRN

GRN

150

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

STK2CFG1

150

150

STK0CFG0

DNP

GRN

STK0CFG1STK0CFG0STK3CFG4STK3CFG3

+3V3

+3V3

STK3CFG1

SWMODE3SWMODE2SWMODE1SWMODE0

G3G2G1G0

STK3CFG2

STK3CFG0

SPARE2 DNP

SPARE1

STK1CFG0STK1CFG1

STK2CFG4STK2CFG3STK2CFG2

STK2CFG0

G3

SWMODE0

STK0CFG1

STK3CFG0

STK3CFG1

SWMODE1

SWMODE3

G1

G0

SWMODE2

G2

STK2CFG3

STK2CFG1

STK2CFG0

STK1CFG1

STK3CFG4

STK3CFG2

STK3CFG3

STK1CFG0

STK2CFG4

GCLKFSEL

ICS_SSM

RSTHALT

SSMBADDR2

SSMBADDR1

CLKMODE1

CLKMODE0

ICS_FS

GCLKFSELICS_SSMRSTHALT

ICS_FS

SSMBADDR2SSMBADDR1CLKMODE1CLKMODE0

+3V3

GRN150

150

150

150

150

150

GRN

GRN

YEL

GRN

YEL

YEL

YEL

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

GRN

GRN

GRN

150

150 GRN

GRN

150 GRN

+3V3

DIP SWITCHES

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUTOUTOUTOUTOUTOUT

OUTOUTOUT

OUT

OUTOUT

DIPSW8

ONOFF

A1

A5

A6

A7

A8

B1

B2

B3

B4

B5

B6

B7

B8

A4

A3

A2

SM_SW4

S1A

S4B

S3B

S2B

S1B

S4A

S3A

S2A

DIPSW8

ONOFF

A1

A5

A6

A7

A8

B1

B2

B3

B4

B5

B6

B7

B8

A4

A3

A2

IN

IN

IN

IN

IN

IN

IN

IN

SM_SW4

S1A

S4B

S3B

S2B

S1B

S4A

S3A

S2A

OUT

OUT

OUT

OUTOUT

OUT

OUTOUT

OUT

OUT

OUT

OUT

DIPSW8

ONOFF

A1

A5

A6

A7

A8

B1

B2

B3

B4

B5

B6

B7

B8

A4

A3

A2

IN

OUT

OUT

OUTOUT

IN

IN

IN

IN

IN

OUT

PORT 22

PORT 17

PORT 18

PORT 20

PORT 19

PORT 21

PORT 23

PORT 16

PORT 15

PORT 10

PORT 11

PORT 12

PORT 13

PORT 14

PORT 7

PORT 8

PORT 9

PORT 23

PORT 21

PORT 20

PORT 10

PORT 18

PORT 17

PORT 14

PORT 15

PORT 16

PORT 13

PORT 12

PORT 6PORT 11

PORT 5

PORT 2

PORT 4

PORT 3

PORT 1

PORT 0

PORT 10

PORT 9

PORT 8

PORT 7

PORT 6

PORT 2

PORT 3

PORT 4

PORT 5

PORT 1

PORT 0

(YELLOW) ACTIVE LOW - PRESENCE DETECT

6 | FAILOVER1 | FAILOVER3

5 | GPEN | P0ACTIVEN

3 | PART3PERSTN | P4ACTIVEN

2 | PART2PERSTN | P4LINKUPN-----------------------------------1 | PART1PERSTN | P16ACTIVEN-----------------------------------0 | PART0PERSTN | P16LINKUPN-----------------------------------

-----------------------------------

-----------------------------------

GPIO | ALT0 | ALT1

4 | FAILOVER0 | P0LINKUPN-----------------------------------

-----------------------------------

7 | FAILOVER2 | P8LINKUPN

PORT 22

| W1:1-2 | W1:2-38 | IOEXPINTN | P8ACTIVEN-----------------------------------

-----------------------------------

(YELLOW) ACTIVE LOW - GPIO

(GREEN) ACTIVE LOW - ATTENTION INPUT

Thu Jul 01 15:01:02 2010 SHEET 34 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

TP58

W1

DS183

DS182

DS184

DS185

DS186

DS187

DS188

R876

R877

R878

R879

R880

R881

R882

DS189

DS190

DS191

DS192

DS193

DS194

DS195

DS196

DS197

DS198

R883

R884

R885

R886

R887

R888

R889

R890

R891

R892

TP

88

TP

87

DS406

DS409

DS408

DS407

DS411

DS410

DS414

DS413

R1368

R1371

R1370

R1369

R1373

R1372

R1376

R1375

DS159

DS158

DS162

DS161

DS160

DS163

DS164

DS167

DS165

DS166

DS168

DS169

R893 DS199DS170

DS200

DS201

DS202

DS203

DS204

DS205

R894

R895

R896

R897

R898

R899

DS172

DS171

DS173

DS174

DS175

DS176

DS177

DS178

DS179

DS180

DS181

TP

86

TP

85

TP

84

TP

83

TP

82

TP

81

TP

80

R852

R853

R854

R855

R856

R857

R858

R859

R860

R861

R862

R863

R864

R865

R866

R867

R868

R869

R870

R871

R872

R873

R874

R875

11

11

11

9

7

11

9 10 11 12 13 14

7

7

7

7

7

7

7

7

9

10

9

10

9

9

10

9

10

11

10

11

10

11

10

9

9

11

10

9 42

10 42

9 42

10 42

9 42

10 42

9 42

9 42

11 42

11 42

10 42

11 42

9 42

11 42

10 42

9 42

11 42

10 42

11 42

9 42

11 42

10 42

11 42

10 42

P21_APN

P17_APN

P19_APN

P20_APN

YEL

GPIO5

150

P15_APN

ORG

IOEXPINTN

YEL

GPIO8

GPIO6

GPIO7

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

YEL

YEL

YEL

YEL

YEL

YEL

YEL

ORG

+3V3

P2_APN

P1_APN

P0_APN

P3_APN

P4_APN

P6_APN

P5_APN

P8_APN

P7_APN

P9_APN

P10_APN

P11_APN

P18_APN

P13_APN

P14_APN

P16_APN

P12_APN

P23_APN

P22_APN

P0_PDN

P1_PDN

P2_PDN

P3_PDN

P4_PDN

P5_PDN

P6_PDN

P8_PDN

P19_PDN

P13_PDN

P14_PDN

P15_PDN

P16_PDN

P17_PDN

P18_PDN

P20_PDN

P21_PDN

P22_PDN

P23_PDN

P12_PDN

P9_PDN

P10_PDN

P11_PDN

P7_PDN

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

150

150

150

150

150

150

YEL

YEL

YEL

YEL

YEL

YEL

ORG YEL150

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

150

150

150

150

150

150

150

YEL

YEL

YEL

YEL

YEL

YEL

YEL

YEL

+3V3

150

150

150

150

150

150

150

150

150

150

YEL

YEL

YEL

YEL

YEL

YEL

YEL

YEL

YEL

YEL

150

150

150

150

150

150

150

YEL

YEL

YEL

YEL

YEL

YEL

YEL

+3V3

LED - PORT STATUS (1 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

IN

IN

IN IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PORT 11

PORT 10

PORT 9

PORT 8

PORT 12

PORT 13

PORT 14

PORT 15

PORT 16

PORT 21

PORT 20

PORT 17

PORT 18

PORT 10

PORT 23

PORT 22

PORT 7

(GREEN) ACTIVE LOW - POWER GOOD

PORT 6

PORT 0

PORT 5

PORT 1

PORT 4

PORT 2

PORT 3

PORT 17

PORT 10

PORT 20

PORT 16

PORT 15

PORT 14

PORT 13

PORT 12

PORT 11

PORT 9

PORT 18

PORT 3

PORT 10

PORT 8

PORT 4

PORT 5

PORT 2

PORT 21

PORT 23

PORT 22

(RED) ACTIVE LOW - POWER FAULT

PORT 0

PORT 1

PORT 6

PORT 7

Thu Jul 01 15:01:02 2010 SHEET 35 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS29

DS31

DS30

DS32

DS34

DS33

DS37

DS36

DS35

DS39

DS38

DS42

DS41

DS40

DS44

DS43

R687

R688

R689

R690

R691

R692

R695

R694

R693

R696

R697

R700

R698

R699

R701

R702

R703 DS45

DS47

DS46

DS49

DS48

DS50

DS51

DS52

R704

R705

R706

R707

R708

R710

R709

DS5

DS7

DS6

DS8

DS10

DS9

DS13

DS12

DS11

DS15

DS14

DS18

DS16

DS17

DS19

DS20

R663

R664

R665

R666

R667

R668

R669

R670

R671

R672

R673

R675

R674

R676

R677

R678

R679 DS21

DS23

DS22

DS25

DS24

DS26

DS28

DS27

R680

R681

R682

R683

R684

R685

R686 9 15 42

11 42

10 42

11 42

9 18 42

11 42

10 42

11 42

9 18 42

11 42

10 42

11 42

9 17 42

11 42

10 42

11 42

9 17 42

10 42

9 16 42

10 42

9 16 42

10 42

9 15 42

10 42

11 42

10 42

11 42

9 18 42

11 42

10 42

11 42

9 18 42

11 42

10 42

11 42

9 17 42

11 42

10 42

9 17 42

10 42

9 16 42

10 42

9 16 42

10 42

9 15 42

10 42

9 15 42

11 42

P0_PWRGDN

P23_PWRGDN

P22_PWRGDN

P21_PWRGDN

P20_PWRGDN

P19_PWRGDN

P18_PWRGDN

P17_PWRGDN

P16_PWRGDN

P15_PWRGDN

P14_PWRGDN

P13_PWRGDN

P12_PWRGDN

P11_PWRGDN

P10_PWRGDN

P9_PWRGDN

P8_PWRGDN

P7_PWRGDN

P6_PWRGDN

P5_PWRGDN

P4_PWRGDN

P3_PWRGDN

P2_PWRGDN

P1_PWRGDN

P23_PFN

P22_PFN

P21_PFN

P20_PFN

P19_PFN

P18_PFN

P17_PFN

P16_PFN

P15_PFN

P14_PFN

P13_PFN

P12_PFN

P11_PFN

P10_PFN

P8_PFN

P7_PFN

P6_PFN

P5_PFN

P4_PFN

P3_PFN

P2_PFN

P1_PFN

P0_PFN

P9_PFN

150 GRN

+3V3

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150 GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

+3V3

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K RED

RED

RED

RED

RED

RED

RED

1K

1K

1K

1K

1K

1K

1K RED

RED

LED - PORT STATUS (2 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PORT 21

PORT 10

PORT 20

PORT 23

PORT 22

PORT 18

PORT 17

PORT 16

PORT 14

PORT 15

PORT 13

PORT 12

PORT 10

PORT 9

PORT 11

PORT 8

PORT 7

PORT 5

PORT 6

PORT 4

PORT 3

PORT 2

PORT 0

PORT 1

(GREEN) ACTIVE LOW - POWER INDICATOR

PORT 22

PORT 23

PORT 21

PORT 10

PORT 20

PORT 18

PORT 17

PORT 16

PORT 14

PORT 15

PORT 13

PORT 8

PORT 5

PORT 6

PORT 9

PORT 10

PORT 12

PORT 7

PORT 11

PORT 3

PORT 0

(ORANGE) ACTIVE LOW - ATTENTION OUTPUT

PORT 1

PORT 2

PORT 4

Thu Jul 01 15:01:02 2010 SHEET 36 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS231

DS230

DS232

DS233

DS234

DS237

DS235

DS236

DS238

DS239

DS240

DS241

DS242

DS243

DS244

R924

R926

R925

R927

R928

R929

R930

R931

R932

R933

R934

R935

R936

R937

R938

R939 DS245

DS247

DS246

DS250

DS249

DS248

DS252

DS251

DS253

R940

R941

R942

R944

R943

R945

R946

R947

DS206

DS207

DS208

DS209

DS210

DS213

DS211

DS212

DS215

DS214

DS216

DS218

DS217

DS220

DS219

R900

R901

R902

R903

R904

R905

R906

R907

R908

R909

R910

R911

R912

R913

R914

R915 DS221

DS223

DS222

DS224

DS225

DS226

DS228

DS227

DS229

R916

R917

R918

R919

R920

R921

R922

R923

9

11

10

11

9

11

10

11

9

11

10

11

9

11

10

11

9

10

9

10

10

9

10

9

11

10

11

9

11

10

11

9

11

10

11

9

11

10

11

9

10

9

10

9

10

9

10

9

P4_PIN

P23_PIN

P22_PIN

P21_PIN

P20_PIN

P19_PIN

P18_PIN

P17_PIN

P16_PIN

P15_PIN

P14_PIN

P13_PIN

P12_PIN

P11_PIN

P10_PIN

P9_PIN

P8_PIN

P7_PIN

P6_PIN

P5_PIN

P3_PIN

P2_PIN

P1_PIN

P0_PIN

P23_AIN

P22_AIN

P21_AIN

P20_AIN

P19_AIN

P18_AIN

P17_AIN

P16_AIN

P15_AIN

P14_AIN

P13_AIN

P12_AIN

P11_AIN

P10_AIN

P9_AIN

P8_AIN

P7_AIN

P6_AIN

P5_AIN

P4_AIN

P3_AIN

P2_AIN

P1_AIN

P0_AIN

+3V3

GRN

GRN

GRN

GRN

150

150

150

150

150 GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

+3V3

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

ORG

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

LED - PORT STATUS (3 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

(GREEN) ACTIVE HIGH - POWER ENABLE

PORT 2

PORT 1

PORT 3

PORT 4

PORT 0

PORT 9

PORT 8

PORT 5

PORT 6

PORT 7

PORT 13

PORT 10

PORT 12

PORT 11

PORT 14

PORT 17

PORT 10

PORT 18

PORT 15

PORT 16

PORT 20

PORT 22

PORT 23

PORT 21

(RED) ACTIVE LOW - HP SLOT RST

PORT 1

PORT 3

PORT 4

PORT 2

PORT 9

PORT 8

PORT 5

PORT 7

PORT 6

PORT 11

PORT 13

PORT 12

PORT 10

PORT 14

PORT 17

PORT 10

PORT 18

PORT 15

PORT 16

PORT 23

PORT 22

PORT 20

PORT 21

PORT 0

Thu Jul 01 15:01:03 2010 SHEET 37 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS77

DS78

DS79

DS80

DS81

DS82

DS83

DS84

DS85

DS86

DS87

DS89

DS88

DS90

DS92

DS91

DS94

DS93

DS95

DS96

DS97

R735

R736

R737

R738

R739

R740

R741

R742

R743

R744

R745

R746

R747

R748

R749

R750

R751

R752

R753

R754

R755

R756 DS98

DS100

DS99R757

R758

DS53R711

DS54

DS55

DS56

DS57

DS58

DS61

DS60

DS59

DS62

DS63

DS66

DS65

DS64

DS68

DS67

DS71

DS70

DS69

DS73

DS72

R712

R713

R714

R715

R716

R717

R718

R719

R720

R721

R722

R723

R724

R725

R726

R728

R727

R729

R730

R731

R732 DS74

DS76

DS75

R734

R733

9 15 42

10 42

9 15 42

9 16 42

10 42

9 16 42

10 42

10 42

11 42

9 17 42

10 42

9 17 42

11 42

10 42

11 42

11 42

11 42

9 18 42

10 42

11 42

9 18 42

11 42

10 42

11 42

9 14 19

10 14 19

9 14 19

9 14 19

10 14 19

9 14 19

10 14 19

10 14 19

9 14 19

11 14 19

10 14 19

9 14 19

11 14 19

10 14 19

11 14 19

11 14 19

9 14 19

11 14 19

11 14 19

10 14 19

9 14 19

10 14 19

11 14 19

11 14 19

P0_PEP

P1_PEP

P2_PEP

P4_PEP

P3_PEP

P6_PEP

P5_PEP

P7_PEP

P9_PEP

P8_PEP

P10_PEP

P12_PEP

P11_PEP

P14_PEP

P13_PEP

P15_PEP

P17_PEP

P16_PEP

P18_PEP

P19_PEP

P20_PEP

P21_PEP

P22_PEP

P23_PEP

P0_RSTN

P1_RSTN

P2_RSTN

P4_RSTN

P3_RSTN

P6_RSTN

P5_RSTN

P7_RSTN

P8_RSTN

P9_RSTN

P10_RSTN

P12_RSTN

P11_RSTN

P14_RSTN

P13_RSTN

P15_RSTN

P16_RSTN

P17_RSTN

P19_RSTN

P18_RSTN

P20_RSTN

P22_RSTN

P21_RSTN

P23_RSTN

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN150

150

150

150

GRN

GRN

GRN

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

+3V3

RED

1K

LED - PORT STATUS (4 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

(GREEN) ACTIVE HIGH - INTERLOCK INPUT

PORT 20

PORT 21

PORT 23

PORT 22

PORT 15

PORT 16

PORT 17

PORT 18

PORT 10

PORT 13

PORT 14

PORT 11

PORT 12

PORT 10

PORT 9

PORT 7

PORT 5

PORT 8

PORT 6

PORT 3

PORT 2

PORT 1

PORT 0

PORT 4

PORT 0

(RED) ACTIVE LOW - MRL

PORT 20

PORT 10

PORT 18

PORT 17

PORT 16

PORT 15

PORT 11

PORT 12

PORT 14

PORT 13

PORT 10

PORT 9

PORT 6

PORT 7

PORT 8

PORT 5

PORT 1

PORT 3

PORT 4

PORT 23

PORT 21

PORT 22

PORT 2

Thu Jul 01 15:01:03 2010 SHEET 38 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS278

DS279

DS280

DS281

DS282

DS283

DS284

DS286

DS285

DS287

DS288

DS289

DS290

DS291

DS292

DS293

DS294

DS295

DS296

R972

R973

R974

R975

R976

R977

R978

R979

R980

R981

R982

R983

R984

R985

R986

R987

R988

R989

R990

DS297

DS298

DS299

DS300

DS301

R991

R992

R993

R994

R995

DS254

DS255

DS256

DS257

DS259

DS258

DS262

DS261

DS260

DS264

DS263

DS267

DS265

DS266

DS268

DS269

DS272

DS270

DS271

R948

R949

R950

R951

R952

R953

R954

R955

R956

R957

R958

R959

R960

R961

R962

R963

R964

R965

R966

DS273

DS274

DS275

DS277

DS276

R967

R968

R969

R970

R971

12

12

12

12

12

12

12

12

12

12

12

13

12

13

12

13

12

13

13

12

12

13

12

12

13

13

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

P13_MRLN

P11_MRLN

P0_ILOCKST

P1_ILOCKST

P2_ILOCKST

P4_ILOCKST

P3_ILOCKST

P5_ILOCKST

P6_ILOCKST

P7_ILOCKST

P8_ILOCKST

P9_ILOCKST

P10_ILOCKST

P11_ILOCKST

P12_ILOCKST

P13_ILOCKST

P14_ILOCKST

P15_ILOCKST

P17_ILOCKST

P16_ILOCKST

P18_ILOCKST

P19_ILOCKST

P20_ILOCKST

P22_ILOCKST

P21_ILOCKST

P23_ILOCKST

P0_MRLN

P1_MRLN

P2_MRLN

P3_MRLN

P4_MRLN

P5_MRLN

P6_MRLN

P7_MRLN

P8_MRLN

P9_MRLN

P10_MRLN

P12_MRLN

P14_MRLN

P15_MRLN

P17_MRLN

P16_MRLN

P18_MRLN

P19_MRLN

P20_MRLN

P23_MRLN

P22_MRLN

P21_MRLN

150 GRN

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150 GRN

GRN

GRN

RED1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

1K

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

RED

+3V3

1K

LED - PORT STATUS (5 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PORT 0

PORT 1

(GREEN) ACTIVE HIGH - INTERLOCK OUTPUT

(RED) ACTIVE LOW - PARTITION FUND. RESET

PORT 4

PORT 2

PORT 3

PORT 5

PORT 6

PORT 8

PORT 10

PORT 9

PORT 7

PORT 11

PORT 13

PORT 14

PORT 12

PORT 15

PORT 16

PORT 18

PORT 21

PORT 20

PORT 10

PORT 17

PORT 22

PORT 23

PART 0

PART 2

PART 1

PART 3

PART 7

PART 6

PART 5

PART 4

(RED) ACTIVE LOW - SLOT HEADER RESET

SLOT 4

SLOT 2

SLOT 0

SLOT 6

SLOT 8

SLOT 12

SLOT 16

SLOT 20

Thu Jul 01 15:01:03 2010 SHEET 39 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS415

DS416

DS417

DS418

R1651

R1650

R1652

R1653

DS419

DS420

DS421

DS422

R1655

R1654

R1656

R1657

DS326

DS327

DS328

DS329

R1021

R1020

R1022

R1023

DS330

DS331

DS332

DS333

DS302

DS303

R1024

R1025

R1026

R1027

R996

R997

DS304

DS305

DS306

DS307

DS308

DS309

DS310

DS311

DS312

DS313

R998

R999

R1000

R1001

R1002

R1003

R1004

R1005

R1006

R1007

DS314

DS315

DS316

DS317

DS318

DS319

DS320

DS321

DS322

DS323

R1008

R1009

R1010

R1011

R1012

R1013

R1014

R1015

R1016

R1017

DS324R1018

DS325R101912

12

14 43

14 43

14 43

14 43

14 43

14 43

14 43

14 43

12

12

13

13

12

12

12

12

12

12

13

12

13

12

13

12

13

12

13

13

12

12

2 7 43 44

2 7 43 44

5 7 43 44

4 7 43 44

3 7 43 44

5 7 43 44

3 7 43 44

4 7 43 44

P0_ILOCKP

P1_ILOCKP

PART3_PERSTN

PART2_PERSTN

PART6_PERSTN

PART7_PERSTN

PART1_PERSTN

PART0_PERSTN

PART4_PERSTN

PART5_PERSTN

P4_ILOCKP

P10_ILOCKP

P9_ILOCKP

P11_ILOCKP

P8_ILOCKP

P3_ILOCKP

P7_ILOCKP

P6_ILOCKP

P5_ILOCKP

P12_ILOCKP

P13_ILOCKP

P14_ILOCKP

P15_ILOCKP

P20_ILOCKP

P21_ILOCKP

P22_ILOCKP

P23_ILOCKP

P18_ILOCKP

P17_ILOCKP

P19_ILOCKP

P16_ILOCKP

P2_ILOCKP

SLOT_HDR_RSTN0

SLOT_HDR_RSTN2

SLOT_HDR_RSTN16

SLOT_HDR_RSTN12

SLOT_HDR_RSTN6

SLOT_HDR_RSTN20

SLOT_HDR_RSTN4

SLOT_HDR_RSTN8

150 GRN

150 GRN

150

150

150

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

1K

1K

1K

1K

GRN

GRN

RED

RED

RED

RED

1K

1K

1K

1K

RED

RED

RED

RED

+3V3

1K

1K

1K

1K

RED

RED

RED

RED

1K

1K

1K

1K

RED

RED

RED

RED

+3V3

LED - PORT STATUS (6 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

(GREEN) ACTIVE LOW - LINK UP

PORT 5

PORT 4

PORT 3

PORT 2

PORT 1

PORT 0 PORT 0

PORT 5

PORT 4

PORT 2

PORT 1

PORT 7

PORT 8

PORT 9

PORT 10

PORT 11

PORT 13

PORT 12

PORT 14

PORT 15

PORT 6

PORT 16

PORT 22

PORT 23

PORT 21

PORT 20

PORT 17

PORT 18

PORT 10

(BLUE) ACTIVE LOW - LINK ACTIVITY

PORT 9

PORT 10

PORT 8

PORT 6

PORT 7

PORT 12

PORT 13

PORT 11

PORT 14

PORT 15

PORT 20

PORT 10

PORT 18

PORT 17

PORT 16

PORT 23

PORT 22

PORT 21

PORT 3

Thu Jul 01 15:01:04 2010 SHEET 40 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

DS358

DS359

DS360

DS361

DS362

R1196

R1197

R1198

R1199

R1200

DS363

DS364

DS365

DS366

DS367

R1201

R1202

R1203

R1204

R1205

DS370

DS369

DS368

DS372

DS371

R1206

R1207

R1208

R1209

R1210

R1211 DS373

DS374

DS375

DS377

DS378

DS376

R1212

R1213

R1214

R1215

R1216

DS379

DS380

DS381

R1217

R1218

R1219

DS334

DS335

DS336

DS337

DS338

DS339

DS340

DS341

DS342

DS343

DS344

DS345

DS346

DS347

DS348

R1172

R1173

R1174

R1175

R1176

R1177

R1178

R1179

R1180

R1181

R1182

R1183

R1184

R1185

R1186

R1187 DS349

DS350

DS351

DS352

DS353

DS354

DS355

DS356

DS357

R1188

R1189

R1190

R1191

R1192

R1193

R1194

R1195 13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

13

P0_ACTIVEN

P2_ACTIVEN

P0_LINKUPN

P1_LINKUPN

P2_LINKUPN

P3_LINKUPN

P4_LINKUPN

P5_LINKUPN

P6_LINKUPN

P7_LINKUPN

P8_LINKUPN

P9_LINKUPN

P10_LINKUPN

P11_LINKUPN

P12_LINKUPN

P13_LINKUPN

P14_LINKUPN

P15_LINKUPN

P16_LINKUPN

P18_LINKUPN

P17_LINKUPN

P19_LINKUPN

P20_LINKUPN

P21_LINKUPN

P22_LINKUPN

P23_LINKUPN

P1_ACTIVEN

P3_ACTIVEN

P5_ACTIVEN

P4_ACTIVEN

P7_ACTIVEN

P6_ACTIVEN

P8_ACTIVEN

P9_ACTIVEN

P10_ACTIVEN

P12_ACTIVEN

P11_ACTIVEN

P13_ACTIVEN

P15_ACTIVEN

P14_ACTIVEN

P16_ACTIVEN

P18_ACTIVEN

P17_ACTIVEN

P19_ACTIVEN

P20_ACTIVEN

P21_ACTIVEN

P22_ACTIVEN

P23_ACTIVEN

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

150

150

150

150

150

150

150

150

GRN

GRN

GRN

GRN

GRN

GRN

GRN

GRN

+3V3

549R

549R

549R

549R

549R

BLUE

BLUE

BLUE

BLUE

BLUE

549R

549R

549R

549R

549R

549R

549R

549R

549R

549R

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

549R

549R

549R

549R

549R

549R

549R

549R

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

+3V3

BLUE

BLUE549R

LED - PORT STATUS (7 OF 7)

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

MINIMUM POWER SUPPLY LOADS

NOTE: DNP JUMPERS WHEN IOEXPANDER IS ENABLED

Thu Jul 01 15:01:04 2010 SHEET 41 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

TP

133

98765432

16151413121110

1

J133

98765432

16151413121110

1

J134

R1120

R1116

R1112

R1108

R1121

R1117

R1113

R1109

R1104

R1100

R1096

R1092

R1105

R1101

R1097

R1093

R1088

R1084

R1080

R1076

R1073

R1089

R1085

R1081

R1077

R1074

R1123

R1122

R1118

R1114

R1110

R1106

R1102

R1098

R1094

R1090

R1086

R1082

R1078

R1038

R1042

R1034

R1030

R1070

R1067

R1064

R1059

R1055

R1051

R1071

R1068

R1065

R1060

R1056

R1052

R1047

R1043

R1039

R1035

R1031

R1048

R1044

R1040

R1036

R1032

R1062

R1061

R1057

R1053

R1049

R1045

R1041

R1037

R1033

7 32 44 45 46 47 48 49 50 51 52

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

19 42 43

MAIN_RSTN

SLOT_RSTN21

SLOT_RSTN15SLOT_RSTN14

SLOT_RSTN23SLOT_RSTN22

SLOT_RSTN19SLOT_RSTN18SLOT_RSTN17

2.54MMVERTNO-SHROUD

+12V2_PS

SLOT_RSTN13SLOT_RSTN11SLOT_RSTN10SLOT_RSTN9SLOT_RSTN7SLOT_RSTN5

SLOT_RSTN1SLOT_RSTN3

VERT 2.54MMNO-SHROUD

YEL

1206

1206

1%

1206

1%

+5V0_PS

1%

53.6

1206

1%

53.6

1206

1206

53.6

1%

1%

53.6

1206

1206

1%

53.6

1%

1206

53.6

1%

1206

53.6

1%

53.6

1206

1%

53.6

1206

+3V3_PS

+12V3_PS

+12V2_PS

+12V1_PS

715

1206

1%

1%

715

1206

1%

715

1206

1206

1%

715

+3V3_PS

1%

1206

715

1%

715

1206

1%

715

1206

1206

715

1%

1%

1206

715

+12V3_PS

715

1%

1206

1%

1206

715

1%

715

1206

1%

715

1206

1%

715

1206

715

1%

1206

1%

1206

715

+12V3_PS

1%

1206

715

715

1206

1%

1206

1%

715

715

1206

1%

715

1%

1206

715

1%

715

1%

1206

1%

715

1206

715

1206

1%

1%

715

1206

+12V2_PS +12V2_PS

1206

124

1%

1206

1%

124

124

1%

1206

1206

1%

124

1206

124

1%

1%

124

1206

124

1%

1206

1206

1%

124

1206

124

1%

1206

124

1%

1206

124

1%

1%

1206

124

1%

124

1206

715

1%

1206

+5V0_PS

715

1%

1206

715

1%

1206

715

1%

715

1206

+12V3_PS

715

1206

1%

+12V3_PS

1%

1206

715

1%

715

1206

1%

1206

715

1%

715

1206

1206

1%

715

1206

715

715

1206

1%

+5V0_PS

1206

715

1%

1206

1%

715

1%

1206

715

1%

1206

715

+12V3_PS

1%

715

+12V2_PS +12V2_PS

1%

715

1206

1%

715

1206

1206

715

1%

1%

1206

715

1%

1206

715

1%

715

1206

1206

1%

715

1%

715

1206

MIN LOAD RESISTORS

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUTOUT

OUT

OUTOUTOUT

OUTOUT

OUTOUTOUTOUT

OUTOUT

OUTOUT

HDR_2x8

1615

1413

1211

109

87

65

1 2

3 4IN

HDR_2x8

1615

1413

1211

109

87

65

1 2

3 4

PORTS 4,5,6,7PORTS 12,13,14,15PORTS 8,9,10,11

POWERGOODWAKEN

PWR_ENABLE

PS_ENABLEN

WAKEN

PWR_FLTN

CABLE SENSE

SLOT_RESETNCARD_PRESENTN

CARD_PRESENTN

PS_ENABLENCABLE SENSE

POWERGOOD

SLOT_RESETN

PORTS 0,1,2,3PORTS 16,17,18,19

PWR_ENABLECLOCK_ENABLEN

PORTS 20,21,22,23

CLOCK_ENABLEN

PWR_FLTN

Thu Jul 01 15:01:04 2010 SHEET 42 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R1237

98107116125134143152161

S13

R1261

R1260

R1262

R1263

R1264

R1265

R1267

R1266

R1268

R1269

987

60

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J47

R1270

R1271

R1272

R1273

R1274

R1275

R1240

R1241

R1242

R1243

R1244

R1245

R1247

R1246

R1248

987

60

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J45

R1249

R1250

R1251

R1252

R1254

R1253

R1255

R1276

R1277

987

60

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J48

R1256

R1257

987

60

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J46

98107116125134143152161

S15

R1220

R1221

R1223

R1222

R1224

R1225

R1227

R1226

R1228

R1229

R1230

R1231

R1232

R1234

R1233

R1235

987

60

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J43

R1236

987

60

6

59585756555453525150

5

49484746454443424140

4

39383736353433323130

3

29282726252423222120

2

19181716151413121110

1

J44

98107116125134143152161

S14

19

11 37

11 35

11 35

19

11 34

19 41 43

10 37

10 35

10 35

10 34

19 41 43

11 37

11 35

11 35

19

11 34

19 41 43

9 18 35

9 18 35

5 19

9 34

19 44

9 18 37

26 42

11 37

11 35

11 35

19

11 34

19 41 43

10 37

10 35

10 35

19

10 34

19 41 43

11 35

11 35

19

11 34

11 37

19 41 43

9 18 37

9 18 35

9 18 35

19 44

5 19

9 34

26 42

10 37

10 35

10 35

19

10 34

19 41 43

9 15 37

9 15 35

9 15 35

2 19

9 34

19 44

10 37

10 35

10 35

19

10 34

19 41 43

9 15 37

9 15 35

9 15 35

19 44

2 19

9 34

26 42

19

11 37

11 35

11 35

11 34

10 37

10 35

10 35

10 34

11 37

11 35

11 35

11 34

9 34

9 17 35

9 17 35

9 17 37

26 42

19 41 43

19

19 41 43

19

19 41 43

4 19

19 44

11 37

11 35

11 35

11 34

10 37

10 35

10 35

10 34

11 37

11 35

11 35

11 34

9 34

9 17 35

9 17 35

9 17 37

26 42

19

19 41 43

19

19 41 43

19

19 41 43

4 19

19 44

10 37

10 35

10 35

10 34

9 16 37

9 16 35

9 16 35

9 34

10 37

10 35

10 35

10 34

9 34

9 16 35

9 16 35

9 16 37

26 42

19

19 41 43

3 19

19 44

19

19 41 43

3 19

19 44

SLOT_WAKEN22

P23_CLK_ENP23_PEP

P23_PWRGDNP23_PFN

SLOT_WAKEN23P23_PDN

SLOT_RSTN23P22_CLK_EN

P22_PEPP22_PFN

P22_PWRGDN

P22_PDNSLOT_RSTN22

P21_PEPP21_CLK_EN

P21_PFNP21_PWRGDN

SLOT_WAKEN21P21_PDN

SLOT_RSTN21

P20_PFNP20_PWRGDN

SLOT_WAKEN20P20_PDN

SLOT_RSTN20

P20_CLK_ENP20_PEP

100

P11_CLK_EN

PS_ENABLENP19_CLK_EN

P19_PEPP19_PFN

P19_PWRGDNSLOT_WAKEN19

P19_PDNSLOT_RSTN19P18_CLK_EN

P18_PEPP18_PFN

P18_PWRGDNSLOT_WAKEN18

P18_PDNSLOT_RSTN18

P17_PFNP17_PWRGDN

SLOT_WAKEN17P17_PDN

P17_CLK_ENP17_PEP

SLOT_RSTN17

P16_PEPP16_CLK_EN

P16_PFNP16_PWRGDN

SLOT_RSTN16

SLOT_WAKEN16P16_PDN

PS_ENABLENP3_CLK_EN

P3_PEPP3_PFN

P3_PWRGDNSLOT_WAKEN3

P3_PDNSLOT_RSTN3P2_CLK_EN

P2_PEPP2_PFN

P2_PWRGDNSLOT_WAKEN2

P2_PDNSLOT_RSTN2P1_CLK_EN

P1_PEPP1_PFN

P1_PWRGDNSLOT_WAKEN1

P1_PDNSLOT_RSTN1P0_CLK_EN

P0_PEPP0_PFN

P0_PWRGDN

SLOT_RSTN0

SLOT_WAKEN0P0_PDN

PS_ENABLEN100

100

100

100

100

100

100

100

100

SLOT_WAKEN11

100

P11_CLK_ENP11_PEPP11_PFN

P11_PWRGDN

P11_PDN

P10_CLK_ENP10_PEPP10_PFN

P10_PWRGDN

P10_PDN

P9_CLK_ENP9_PEPP9_PFN

P9_PWRGDN

P9_PDN

P8_PDN

P8_PWRGDNP8_PFNP8_PEP

P8_CLK_EN

PS_ENABLEN

SLOT_RSTN11

SLOT_WAKEN10

SLOT_RSTN10

SLOT_WAKEN9

SLOT_RSTN9

SLOT_WAKEN8

SLOT_RSTN8

P15_CLK_ENP15_PEPP15_PFN

P15_PWRGDN

P15_PDN

P14_CLK_ENP14_PEPP14_PFN

P14_PWRGDN

P14_PDN

P13_CLK_ENP13_PEPP13_PFN

P13_PWRGDN

P13_PDN

P12_PDN

P12_PWRGDNP12_PFNP12_PEP

P12_CLK_EN

PS_ENABLEN

SLOT_WAKEN15

SLOT_RSTN15

SLOT_WAKEN14

SLOT_RSTN14

SLOT_WAKEN13

SLOT_RSTN13

SLOT_WAKEN12

SLOT_RSTN12

P7_CLK_ENP7_PEPP7_PFN

P7_PWRGDN

P7_PDN

P6_CLK_ENP6_PEPP6_PFN

P6_PWRGDN

P6_PDN

P5_CLK_ENP5_PEPP5_PFN

P5_PWRGDN

P5_PDN

P4_PDN

P4_PWRGDNP4_PFNP4_PEP

P4_CLK_EN

PS_ENABLEN

SLOT_WAKEN7

SLOT_RSTN7

SLOT_WAKEN6

SLOT_RSTN6

SLOT_WAKEN5

SLOT_RSTN5

SLOT_WAKEN4

SLOT_RSTN4

0.050X0.1SHROUD

VERT

100

100

100

100

100

100

100

VERTSHROUD0.050X0.1

100

100

100

100

100

100

100

100

100

VERT 0.050X0.1SHROUD

100

100

100

SHROUD0.050X0.1VERT

100

100

100

100

100

100

0.050X0.1SHROUD

VERT

100

100

100

100

100

100

100

100

100

VERTSHROUD0.050X0.1

100

100

100

100

100

100

100

100

100

SIDEBAND CONNECTORSP7_CLK_ENP6_CLK_ENP5_CLK_ENP4_CLK_ENP3_CLK_ENP2_CLK_ENP1_CLK_ENP0_CLK_EN

P23_CLK_ENP22_CLK_ENP21_CLK_ENP20_CLK_ENP19_CLK_ENP18_CLK_ENP17_CLK_ENP16_CLK_EN

P15_CLK_ENP14_CLK_ENP13_CLK_ENP12_CLK_EN

P10_CLK_ENP9_CLK_ENP8_CLK_EN

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

HDR_2x30

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

2

4

6

8

10

12

14

16

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

1

3

5

7

9

13

11

15

INBI

OUTBI

OUTOUTIN

HDR_2x30

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

2

4

6

8

10

12

14

16

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

1

3

5

7

9

13

11

15

ININ

BIOUT

OUTBI

OUT

ININ

BIOUTBI

OUTOUT

ININ

BI

BIOUT

OUTOUTIN

BI

IN

OUT

OUTIN

OUTBI

IN

IN

HDR_2x30

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

2

4

6

8

10

12

14

16

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

1

3

5

7

9

13

11

15

OUT

OUT

IN

IN

HDR_2x30

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

2

4

6

8

10

12

14

16

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

1

3

5

7

9

13

11

15

OUTIN

BI

HDR_2x30

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

2

4

6

8

10

12

14

16

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

1

3

5

7

9

13

11

15

OUTBI

OUT

INOUT

IN

IN

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

OUTOUTBI

OUTBI

OUTBI

BIININ

INBI

IN

OUTOUT

OUT

OUTBI

INOUT

IN

OUTBI

OUTBI

OUT

INININ

BIOUT

IN

OUTIN

BIOUT

OUTOUTBI

OUTBI

OUTBI

BI

IN

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

IN

BI

ININ

OUTOUT

OUTOUTBI

OUTBI

OUTBI

BIININ

INBI

INOUTOUT

OUT

OUTBI

INOUT

HDR_2x30

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

2

4

6

8

10

12

14

16

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

1

3

5

7

9

13

11

15

IN

OUTOUTBI

OUTBI

INININ

BIOUTBI

OUTOUTININ

BIOUTBI

OUTOUTININ

BIOUTBI

IN

BI

OUTOUTIN

OUTBI

BIOUTOUTININBI

BIOUT

OUTOUT

IN

BIIN

OUTBI

OUTOUT

Thu Jul 01 15:01:05 2010 SHEET 43 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

TP143

TP144

TP145

TP146

TP147

TP148

TP150

TP149

TP142

TP141

TP140

TP139

TP138

TP137

TP136

TP135

TP

113

9876543

20

2

19181716151413121110

1

J84

TP

114

9876543

20

2

19181716151413121110

1

J85

TP

115

9876543

20

2

19181716151413121110

1

J86

TP

116

9876543

20

2

19181716151413121110

1

J87

TP

109

9876543

20

2

19181716151413121110

1

J80

TP

110

9876543

20

2

19181716151413121110

1

J81

TP

111

9876543

20

2

19181716151413121110

1

J82

TP

112

9876543

20

2

19181716151413121110

1

J83

2 7 39 43 44

2 7 39 43 44

3 7 39 43 44

3 7 39 43 44

4 7 39 43 44

4 7 39 43 44

14 39

19 41 42

14 39

14 39

14 39

14 39

19 41 42

19 41 42

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

19 41 42

19 41 42

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

2 7 39 43 44

3 7 39 43 44

2 7 39 43 44

19 41 42

19 41 42

19 41 42

19 41 42

14 39

14 39

14 39

19 41 42

19 41 42

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

19 41 42

19 41 42

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

19 41 42

19 41 42

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

19 41 42

5 7 39 43 44

5 7 39 43 44

SLOT_HDR_RSTN2SLOT_HDR_RSTN0

SLOT_HDR_RSTN4SLOT_HDR_RSTN6SLOT_HDR_RSTN8SLOT_HDR_RSTN12

PART0_PERSTN

SLOT_RSTN3

PART6_PERSTN

PART7_PERSTN

PART4_PERSTN

PART5_PERSTN

SLOT_RSTN23SLOT_RSTN22SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4

SLOT_HDR_RSTN0SLOT_HDR_RSTN2

SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8

SLOT_HDR_RSTN4SLOT_HDR_RSTN6

SLOT_HDR_RSTN0SLOT_HDR_RSTN2

SLOT_RSTN15SLOT_RSTN14SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4

SLOT_HDR_RSTN0SLOT_HDR_RSTN2

SLOT_HDR_RSTN16SLOT_HDR_RSTN20

SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6

SLOT_HDR_RSTN2SLOT_HDR_RSTN4

SLOT_HDR_RSTN0

SLOT_RSTN21SLOT_RSTN19

SLOT_RSTN18SLOT_RSTN17

YEL

YEL

YEL

YEL

YEL

YEL

2.0MMVERT_SMNO-SHROUD

YEL

YEL

YEL

YEL

2.0MMVERT_SMNO-SHROUD

YEL

YEL

2.0MMVERT_SMNO-SHROUD

2.0MMVERT_SMNO-SHROUD

PART3_PERSTN

PART2_PERSTN

PART1_PERSTN

SLOT_RSTN13SLOT_RSTN11SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4

SLOT_HDR_RSTN0SLOT_HDR_RSTN2

SLOT_RSTN10SLOT_RSTN9SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4

SLOT_HDR_RSTN0SLOT_HDR_RSTN2

SLOT_RSTN7SLOT_RSTN5SLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4

SLOT_HDR_RSTN0SLOT_HDR_RSTN2

SLOT_RSTN1SLOT_HDR_RSTN20SLOT_HDR_RSTN16

YEL

2.0MMVERT_SMNO-SHROUD

YEL

2.0MMVERT_SMNO-SHROUD

YEL

YEL

YEL

YEL

YEL

YEL2.0MMVERT_SMNO-SHROUD

YEL

2.0MMVERT_SMNO-SHROUD

YEL

YEL

YEL

PARTITION RESET SELECT HEADERS

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

OUT

OUT

OUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4OUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

OUT

OUT

OUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

IN

INININININININININ

IN

INININININININININ

IN

INININININININININ

IN

INININININININININ

IN

INININININININININ

IN

INININININININININ

INININININININININ

IN

ININININININININININ

OUT

Thu Jul 01 15:01:05 2010 SHEET 44 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

TP

121

9876543

20

2

19181716151413121110

1

J129

TP

122

9876543

20

2

19181716151413121110

1

J130

TP

123

9876543

20

2

19181716151413121110

1

J131

TP

124

9876543

20

2

19181716151413121110

1

J132

TP

117

9876543

20

2

19181716151413121110

1

J125

TP

118

9876543

20

2

19181716151413121110

1

J126

TP

119

9876543

20

2

19181716151413121110

1

J127

TP

120

9876543

20

2

19181716151413121110

1

J128

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

5 7 39 43 44

25

3 7 39 43 44

4 7 39 43 44

4 7 39 43 44

5 7 39 43 44

2 7 39 43 44

2 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

25

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

7 32 41 44 45 46 47 48 49 50 51 52 19 42

25

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

7 32 41 44 45 46 47 48 49 50 51 52 19 42

19 42

7 32 41 44 45 46 47 48 49 50 51 52

25

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

2 7 39 43 44

7 32 41 44 45 46 47 48 49 50 51 52 19 42

5 7 39 43 44

25

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

5 7 39 43 44

4 7 39 43 44

4 7 39 43 44

25

5 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

22

7 32 41 44 45 46 47 48 49 50 51 52 19 42

25

5 7 39 43 44

5 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

7 32 41 44 45 46 47 48 49 50 51 52 19 42

19 42

7 32 41 44 45 46 47 48 49 50 51 52

25

5 7 39 43 44

4 7 39 43 44

3 7 39 43 44

3 7 39 43 44

2 7 39 43 44

2 7 39 43 44

23

7 32 41 44 45 46 47 48 49 50 51 52 19 42

SLOT_HDR_RSTN8

SLOT_HDR_RSTN6

NO-SHROUD

NO-SHROUD

SLOT_HDR_RSTN6

SLOT_HDR_RSTN20S6_SATA_RSTN

SLOT_HDR_RSTN4SLOT_HDR_RSTN8SLOT_HDR_RSTN12SLOT_HDR_RSTN16

SLOT_HDR_RSTN2SLOT_HDR_RSTN0

SLOT_HDR_RSTN4

SLOT_HDR_RSTN2

SLOT_HDR_RSTN0

S4_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN2SLOT_HDR_RSTN0

MAIN_RSTNSLOT_RSTN4

S2_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12

SLOT_HDR_RSTN6SLOT_HDR_RSTN4SLOT_HDR_RSTN0

MAIN_RSTNSLOT_RSTN2

SLOT_RSTN6MAIN_RSTN

S0_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8

SLOT_HDR_RSTN4SLOT_HDR_RSTN2

MAIN_RSTNSLOT_RSTN0

YEL

2.0MMVERT_SMNO-SHROUD

YEL

2.0MMVERT_SM

YEL

2.0MMVERT_SM

YEL

2.0MMVERT_SMNO-SHROUD

SLOT_HDR_RSTN20

S20_SATA_RSTNSLOT_HDR_RSTN16SLOT_HDR_RSTN12SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4SLOT_HDR_RSTN2SLOT_HDR_RSTN0

SLOT_HDR_RSTN16

SLOT_HDR_RSTN12

SLOT_HDR_RSTN8

S16_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN12SLOT_HDR_RSTN6SLOT_HDR_RSTN4SLOT_HDR_RSTN2SLOT_HDR_RSTN0P8_SATARSTN

MAIN_RSTNSLOT_RSTN16

S12_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN16SLOT_HDR_RSTN8SLOT_HDR_RSTN6SLOT_HDR_RSTN4SLOT_HDR_RSTN2SLOT_HDR_RSTN0

MAIN_RSTNSLOT_RSTN12

SLOT_RSTN20MAIN_RSTN

S8_SATA_RSTNSLOT_HDR_RSTN20SLOT_HDR_RSTN12SLOT_HDR_RSTN6SLOT_HDR_RSTN4SLOT_HDR_RSTN2SLOT_HDR_RSTN0P16_SATARSTN

MAIN_RSTNSLOT_RSTN8

YEL

2.0MMVERT_SMNO-SHROUD

YEL

2.0MMVERT_SMNO-SHROUD

YEL

2.0MMVERT_SMNO-SHROUD

YEL

2.0MMVERT_SMNO-SHROUD

SLOT RESET SELECT HEADERS

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUT

OUT

OUT

OUTOUTOUTOUTOUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

OUT

OUTOUT

OUTOUTOUT

OUT

OUTOUTOUT

OUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

OUT

OUTOUT

OUTOUTOUTOUTOUTOUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

BI

BI

BI

BI

OUT

OUTOUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

OUTOUT

OUTOUT

OUTOUTOUT

OUTOUTOUT

BI

OUT

OUTOUT

OUTOUTOUTOUT

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

BI

HDR_2x10

2019

1817

1615

1413

1211

109

87

65

1 2

3 4

OUTOUT

OUT

OUTOUT

OUT

OUTOUT

OUT

BI

OUT

OUT

OUTOUT

OUT

OUTOUTOUTOUT

OUTOUT

OUT

OUT

OUT

OUTBI

NC

NCNC

PCLK_SSM

NC

PCLK_MR

PCLK_FSEL

Thu Jul 01 15:01:05 2010 SHEET 45 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R770

TP

59

C63C67C68C71

R1433

R1430

R1431

R1434

R1427

R1428

R1424

R1421

R1418

R1415

R1412

98107116125134143152161

SW1

R1422

R1425

R1419

R1416

R1413

98107116125134143152161

SW2

C680

C679

5 4

32

1

J89

5 4

32

1

J90

FB10

C484

C678

R1404

C677

C480

C676

C476

C675

R1400

TP97

R637

R1405

R1608

R1609

R1401

R1402R1406

R630R1403

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U116

R1607

R1435

R1432

R1429

R1423

R1426

R1417

R1420

R1414

98107116125134143152161

SW3

MTG2MTG1

7654321

J88

R1411

R1409

R633

R1410

R1408

R1611

R1610

R1407R

1606

R1605

C673R

1604

21

X2

C674

R1399

7 32 41 44 46 47 48 49 50 51 52

50

49

25

25

24

24

52

51

48

47

46

52

51

50

49

48

47

46

52

51

50

49

48

47

46

MAIN_RSTN

DNP

0

LSATA0_CLKN

LSATA0_CLKP

P12_ICS_FSEL0

P8_ICS_FSEL0

49.9

49.9

10UF

0.1UF

0.1UF

0.1UF

0.1UF LSMA0_CLKN

LSMA0_CLKP

49.9

LS0_CLKN

LS0_CLKP

LP0_CLKN

LP0_CLKP

33.2

33.2

33.2

33.2

33.2

33.2

33.2

49.9

49.9

49.9

49.9

49.9

33.2

P0_ICS_SSM

33.2

10K

475

P0_ICS_FSEL0

P20_ICS_FSEL0

P16_ICS_FSEL0

P6_ICS_FSEL0

P4_ICS_FSEL0

P2_ICS_FSEL0

P0_ICS_FSEL0

4.7K

DNP

PORT 0 CLOCK GENERATOR

P20_ICS_SSM

P16_ICS_SSM

P12_ICS_SSM

P8_ICS_SSM

P6_ICS_SSM

P4_ICS_SSM

P2_ICS_SSM

P0_ICS_SSM

P20_ICS_MR

P16_ICS_MR

P12_ICS_MR

P8_ICS_MR

P6_ICS_MR

P4_ICS_MR

P2_ICS_MR

P0_ICS_MR

YEL

CONNSMA

221789-0

CONNSMA

221789-0

22PF

22PF

P0_ICS_MR

1%

DNP

0402

1%

DNP

0402

1%

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

DNP

0402

1%

16V

10UF

0.1UF

0.1UF

0.1UF

0.1UF

0603

10

5%

0.1UF

0805

120OHM

400MA

0.1UF

1.0UF

+3V3

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

+3V3

4.7K

4.7K

+3V3

4.7K

4.7K

+3V3

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

OUTOUTOUTOUTOUT

OUTOUT

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

OUTOUT

OUTOUT

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

12

OUT

OUTOUT

OUTOUT

OUTOUT

SM_SW8

S1A

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S8A

S7A

S6A

S5A

S4A

S3A

S2A

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

OUTOUTOUT

OUTOUT

OUTOUT

NCNC

NCNC

Thu Jul 01 15:01:06 2010 SHEET 46 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R771

TP

62

C73C76C80C81

5 4

32

1

J107

5 4

32

1

J108

FB16

C739

C738

MTG2MTG1

7654321

J106

R1578

R1576

R1574

R1572

R1579

R1577

R1575

R1573

TP103

R1567

R1560

R1558

C737

C736

C735

C734

C733

C732

R1568

R1569

R1570

R1571

R1562

R1563

R1564

R1566

R1565

C731

R1559

R1557

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U122

21

X8

C729

C730

R1556

R1561

45

45

45

24

25

25

24

7 32 41 44 45 47 48 49 50 51 52

+3V3

0805

120OHM

400MA

1.0UF

0.1UF

0603

10

5%

1%

0402

DNP

0402

DNP

1%

10UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

16V

10UF

0402

1%

475

DNP

1%

22PF

22PF

221789-0

CONNSMA

YEL

PORT 2 CLOCK GENERATOR

221789-0

CONNSMA

DNP

10K

33.2

P2_ICS_SSM

P2_ICS_MR

P2_ICS_FSEL0

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

LP2_CLKN

LS2_CLKN

LS2_CLKP

LP2_CLKP

0.1UF

0.1UF

0.1UF

0.1UF LSMA2_CLKP

LSMA2_CLKN

LSATA2_CLKP

LSATA2_CLKN

0DNP

MAIN_RSTN

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

OUTOUTOUT

OUTIN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

12

NC

NC

NC

NC

Thu Jul 01 15:01:06 2010 SHEET 47 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R772

TP

63

C84C85C88C89

5 4

32

1

J110

5 4

32

1

J111

C750

C749

FB17

MTG2MTG1

7654321

J109

R1602

R1600

R1598

R1603

R1601

R1599

R1597

R1596

C748

C747

C746

R1591

C745

C744

C743

C742

R1584

R1582

TP104

R1592R1587

R1588

R1586

R1595

R1593

R1594R1589

R1590

R1583

R1581

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U123

C740

21

X9

C741

R1580

R1585

7 32 41 44 45 46 48 49 50 51 52

24

25

25

24

45

45

45

+3V3

MAIN_RSTN

DNP

0

LSATA4_CLKN

LSATA4_CLKP

LSMA4_CLKN

LSMA4_CLKP

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

LP4_CLKP

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

LS4_CLKN

LS4_CLKP

LP4_CLKN

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

10K

DNP

P4_ICS_FSEL0

22PF

DNP

0.1UF

PORT 4 CLOCK GENERATOR

CONNSMA

221789-0

CONNSMA

221789-0

22PF

0402

P4_ICS_SSM

P4_ICS_MR

1%

475

1%

0402

YEL

0402

DNP

1%

1%

DNP 16V

10UF

0.1UF

0603

10

5%

0.1UF

0.1UF

10UF

0805

120OHM

400MA

0.1UF

1.0UF

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

12

IN

INOUTOUT

OUTOUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

IN

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

NCNCNCNC

Thu Jul 01 15:01:06 2010 SHEET 48 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R773

TP

64

C100C99C95

C102

5 4

32

1

J92

5 4

32

1

J93

FB11

C691

C690

C689

C688

C687

TP98

R1448

R1449

R1450

R1451

MTG2MTG1

7654321

J91

R1458

R1456

R1454

R1452

R1459

R1457

R1455

R1453

C686

R1447

R1440

R1438

C685

C684

C683

R1442

R1443

R1444

R1445

R1446

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U117

R1439

R1437

21

X3R

1436

C681

C682

R1441

7 32 41 44 45 46 47 49 50 51 52

24 45

24

25

25

45

45

MAIN_RSTN

DNP

0

LSATA6_CLKN

LSATA6_CLKP

LP6_CLKP

LSMA6_CLKN

LSMA6_CLKP

P6_ICS_FSEL0

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

LP6_CLKN

LS6_CLKP

LS6_CLKN

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

10K

33.2

DNP

475

P6_ICS_MR

P6_ICS_SSM

PORT 6 CLOCK GENERATOR

CONNSMA

221789-0

CONNSMA

221789-0

22PF

22PF

1%

1%

DNP

0402

16V

10UF

0.1UF

0.1UF

0402

DNP

1%

1%

0402

DNP

0603

10

5%

0.1UF

YEL

0.1UF

10UF

0.1UF

1.0UF

0805

120OHM

400MA

+3V3

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

OUTOUTOUTOUT

IN

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

12

NCNCNC

NC

Thu Jul 01 15:01:06 2010 SHEET 49 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R774

TP

65

C105C108C110C112

5 4

32

1

J95

5 4

32

1

J96

FB12

C702

C701

R1471

R1464

R1462

C700

C699

C698

C697

C696

TP99

R1472

R1475

R1474

R1473

R1466

R1467

R1468

R1469

R1470

C695

C694

R1463

R1461

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U118

21

X4

C692

C693

R1460

MTG2MTG1

7654321

J94

R1482

R1480

R1478

R1483

R1481

R1479

R1477

R1476

R1465

7 32 41 44 45 46 47 48 50 51 52

22

22

25

25

45

45

45

MAIN_RSTN

DNP

0

LSATA8_CLKN

LSATA8_CLKP

YEL

LSMA8_CLKP

LSMA8_CLKN0.1UF

0.1UF

0.1UF

0.1UF

0402

LP8_CLKP

LP8_CLKN

LS8_CLKP

LS8_CLKN

33.2

49.9

49.9

49.9

33.2

33.2

49.9

49.9

33.2

33.2

33.2

33.2

33.2

49.9

49.9

49.9

P8_ICS_FSEL0

P8_ICS_MR

P8_ICS_SSM

0402

33.2

10K

475

CONNSMA

+3V3

400MA

1.0UF

0.1UF

120OHM

0805

10UF

0.1UF

PORT 8 CLOCK GENERATOR

CONNSMA

221789-0

221789-0

5%

10

0603

0.1UF

0.1UF

0.1UF

16V

0.1UF

10UF

1%

1%

0402

DNP

DNP

1%

DNP

1%

22PF

22PF

DNP

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

OUTOUTOUTOUT

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

12

IN

IN

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

NC

NC

NC

NC

Thu Jul 01 15:01:07 2010 SHEET 50 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R775

TP

66

C113C117C120C121

5 4

32

1

J98

5 4

32

1

J99

C713

C712

MTG2MTG1

7654321

J97

R1506

R1504

R1505

R1507

R1503

R1502

FB13

R1495

C711

C710

TP100

C709

C708

C707

R1490

R1488

C706

C705

R1487

R1496

R1497

R1499

R1498

R1491

R1492

R1493

R1494

R1500

R1501

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U119

R1489

R1486

R1485

21

X5

C703

C704

R1484

7 32 41 44 45 46 47 48 49 51 52

24

25

25

24

45

45

45

+3V3

MAIN_RSTN

DNP

0

LSATA12_CLKN

LSATA12_CLKP

LSMA12_CLKN

0.1UF

LSMA12_CLKP

33.2

0.1UF

0.1UF

0.1UF

0402

LP12_CLKP

LS12_CLKN

LS12_CLKP

LP12_CLKN

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

33.2

33.2

33.2

33.2

33.2

33.2

33.2

P12_ICS_MR

P12_ICS_FSEL0

1.0UF

0.1UF

400MA

120OHM

0805

5%

10UF

0.1UF

YEL

0.1UF

0.1UF

0.1UF

DNP

0402

1%

0.1UF

10UF

16V

1%

DNP

0402

1%

475

22PF

22PF

10

0603

221789-0

CONNSMA

221789-0

CONNSMA

PORT 12 CLOCK GENERATOR

DNP

DNP

P12_ICS_SSM

1%

10K

33.2

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

12

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

OUTOUT

OUTOUT

IN

IN

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

IN

NCNCNCNC

Thu Jul 01 15:01:07 2010 SHEET 51 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R768

TP

67

C124C125

C123C122

5 4

32

1

J101

5 4

32

1

J102

C724

C723

FB14

TP101

MTG2MTG1

7654321

J100

R1530

R1531

R1528

R1526

R1529

R1527

R1525

R1524

C722

R1519

C721

C720

C719

C718

C717

C716

R1512

R1510

R1521

R1520

R1514

R1517

R1516

R1515

R1523

R1522R1518

R1511

R1509

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U120

R1508

R1513

C714

21

X6

C715

7 32 41 44 45 46 47 48 49 50 52

23

25

23

25

45

45

45

MAIN_RSTN

DNP

0

LSATA16_CLKN

LSATA16_CLKP

LP16_CLKP

LS16_CLKP

YEL

LP16_CLKN

0.1UF

0402

LSMA16_CLKP

LSMA16_CLKN

+3V3

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

LS16_CLKN

0.1UF

0.1UF

0.1UF

33.2

33.2

33.2

33.2

33.2

33.2

33.2

33.2

P16_ICS_MR

33.2

CONNSMA

10K

DNP

P16_ICS_FSEL0

PORT 16 CLOCK GENERATOR

221789-0

CONNSMA

221789-0

22PF

22PF

P16_ICS_SSM

475

1%

DNP

1%

1%

DNP

0402

DNP

0402

1%

10UF

16V

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

5%

10

0603

10UF

400MA

120OHM

0805

0.1UF

1.0UF

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

12

IN

OUTOUT

OUTOUT

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

IN

IN

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

NCNCNCNC

Thu Jul 01 15:01:07 2010 SHEET 52 OF 52

2.018-691-001

Derek Huang

2010

Tony Tran

SCH-PESEB-001

EB-LOGAN-23

B

R776

TP

68

C129C128C127C126

5 4

32

1

J104

5 4

32

1

J105

FB15

C728

C727

MTG2MTG1

7654321

J103

R1554

R1552

R1550

R1555

R1551

R1553

R1549

R1548

R1543

R1536

R1534

C513

C522

C518

TP102

C510

C514

C507

R1538

R1545

R1544

R1546

R1547

R1539

R1540

R1541

R1542C

726

R1535

R1533

9

8765

4

3332

31

30

3

29

28

27

2625

24

2322

21

20

2

19

18171615

14

13121110

1

U121

21

X7

C725

C501

R1532

R1537

7 32 41 44 45 46 47 48 49 50 51

25

24

25

24

45

45

45

MAIN_RSTN

0

LSATA20_CLKN

LSATA20_CLKP

LS20_CLKP

49.9

0.1UF

LSMA20_CLKN0.1UF

+3V3

DNP

LSMA20_CLKP

49.9

LP20_CLKP33.2

LS20_CLKN

LP20_CLKN

CONNSMA

49.9

49.9

49.9

49.9

49.9

49.9

0.1UF

YEL

0.1UF

0.1UF

33.2

33.2

33.2

33.2

33.2

33.2

33.2

PORT 20 CLOCK GENERATOR

33.2

10K

DNP

P20_ICS_FSEL0

P20_ICS_MR

1%

P20_ICS_SSM

221789-0

CONNSMA

221789-0

22PF

22PF

10UF

0.1UF

0.1UF

10UF

DNP

475

1%

DNP

0402

16V

0.1UF

0.1UF

0402

DNP

1%

1%

0402

0603

10

5%

0.1UF

1.0UF

0805

120OHM

400MA

IDT

TITLE

DRAWING NO.

AUTHOR CHECKED BY

COPYRIGHT (C)

3

SIZE REV.FAB P/N

1

1

A A

B B

C C

DD

2

2

4

45

6

67

7

8

38 5

6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

IN

IN

OUTOUT

OUTOUT

IN

678005005

MTG2

MTG1

7

6

5

4

3

2

1

IN

ICS841484

REF_IN

XTAL_OUT

XTAL_IN

REF_SEL

FSEL0

FSEL1

OE_REFOUT

MR_nOE

IREF

SSM

GND

PGND

GND

GND

VDD

VDD

VDD

VDD

REF_OUT

NC

VDDA

Q2

nQ0

BYPASS

NC

NC

NC

nQ3

Q3

nQ2

nQ1

Q1

Q0

12

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