A Micropower Differential Charge-BalancingSwitched-Capacitor Front-End for Capacitive

Microaccelerometers

Mika Kämäräinen ∗ Mikko Saukoski ∗ Kari Halonen ∗

Abstract — In this paper, a micropower differential switched-capacitor front-end for capacitive microaccelerometers is pre-sented. The front-end preserves charge balance in the sensorbeing read, thus avoiding distortion caused by nonlinear electro-static forces. All signal paths except the one connected to the mid-dle electrode of the sensor are differential, making integration onthe same substrate with digital signal processing easier. Trans-fer function, -3 dB corner frequency and stability conditions areanalysed. The effect of finite DC gain of the operational ampli-fiers is presented. The front-end achieves a 58dB maximum sim-ulated SNR with 1.8V operating voltage, when sampling fourchannels in a time-multiplexed fashion with 10kHz samplingfrequency for each channel. The worst case current consumptionis 45µA. A prototype chip was designed and will be fabricatedin a 0.13µm CMOS process.

1 INTRODUCTION

Microaccelerometers are micromachined accelerationsensors with dimensions ranging from 1 to 100 microm-eters. The devices can be for example piezoelectrical,piezoresistive or capacitive. Capacitive accelerometershave advantages such as zero static biasing current andexcellent thermal stability. Further, by using bulk mi-cromachined devices with a large seismic mass, veryhigh sensitivity can be reached.

With a proper configuration, a single capacitive ac-celerometer can measure accelerations along all threeaxes simultaneously [1, 2]. These devices are built suchthat the seismic mass forms four differential capacitorpairs. By measuring these capacitances and taking theirproper linear combinations, all three vector componentsof linear acceleration (x-, y- and z-directional) can beevaluated. With four masses, these devices also offer re-dundancy so that fault conditions can be detected. Thesensor element presented in [1] is shown in Figure 1.

A cheap yet reliable and highly-sensitive three-axisaccelerometer with low power consumption would havea wide range of applications, from hand-held mobileterminals and toys to industrial applications and auto-motive chassis control systems. In order to realise thiskind of a sensor, the read-out electronics has to be inte-grated together with the sensor element, forming a mi-croelectromechanical system (MEMS). The accelerom-eter should ideally have a fully digital output.

∗Electronic Circuit Design Laboratory, HelsinkiUniversity of Technology, Finland, e-mail:mika.kamarainen@ecdl.hut.fi, tel.: +358 9 451 2275,fax: +358 9 451 2269.

Figure 1: Left: Three-axis accelerometer presented in[1]; Right: Top view of the structural wafer of the ac-celerometer. (Images courtesy of VTI Technologies Oy,Vantaa, Finland.)

In this paper, we present the design of a differen-tial switched-capacitor (SC) front-end for capacitive ac-celerometers. The front-end is designed to read a capac-itive three-axis accelerometer by time-multiplexing thepresented circuit between four channels. The maximumsignal frequency in each channel is 1 kHz, the samplingfrequency for a single channel is 10 kHz, and the totalsampling frequency is 40 kHz. The -3 dB point of eachchannel is set to one quarter of the sampling frequencyfs. The design together with simulations are done witha 0.13µm CMOS process that offers high-quality ana-log capacitors. The circuit is being manufactured to ver-ify the design with measurements.

First, the basic theory behind the circuit is presentedand specific design issues are discussed. Next, the nec-essary equations for design and analysis are given. Fi-nally, simulation results are shown.

2 DESIGNED CIRCUIT

2.1 Background

A capacitive accelerometer can be modeled by a three-terminal component that consists of two capacitors,CDP and CDN, with a common middle electrode (seeFigure 2). If the capacitors are considered to be simpleplate capacitors, their capacitances under accelerationcan be written as

CDP =Aεrε0d− ∆d

= C0

(

d

d− ∆d

)

,

CDN =Aεrε0d+ ∆d

= C0

(

d

d+ ∆d

)

. (1)

Here, A is the plate area, εr the relative permittivity ofthe insulator, ε0 the permittivity of vacuum, d the initialdistance between the capacitor plates, ∆d the changein plate distance induced by acceleration, and C0 thecapacitance with ∆d = 0.

In order to be able to convert the capacitance to volt-age, the sensor structure needs to be biased. This bias-ing is usually done with either constant voltage or con-stant charge.

When a voltage V is connected over a capacitor withcapacitance C, charge Q = C · V flows into it. Theelectrostatic force between the capacitor plates can thenbe written as F = Q2/ (2εrε0A). By substituting (1)into this, we get

FCDP =Aεrε0V

2

2

(

1

d− ∆d

)2

,

FCDN =Aεrε0V

2

2

(

1

d+ ∆d

)2

. (2)

These equations show that the forces with a constantvoltage bias are nonlinear functions of the displacement∆d. When ∆d differs from 0 the forces are unequal,incurring nonlinear error to ∆d and causing harmonicdistortion.

One way to eliminate this distortion is the self-balancing bridge (SBB) originally presented in [3]. Inthis SC circuit, feedback changes the biasing voltagesover CDP and CDN by adjusting the middle elec-trode voltage, so that the amount of charge in and thusthe electrostatic forces over both capacitors are equal.When CDP and CDN follow Equation (1), this amountof charge stays constant.

When moving to three-axis accelerometers with dig-ital outputs, lots of digital signal processing needs to beintegrated on the same substrate with the sensor front-end. This increases the requirements for substrate andpower supply noise rejection in analog circuits. Noiseimmunity can be significantly improved by using fullydifferential circuits with balanced signal paths.

2.2 Structure

To solve the aforementioned problems, we have de-signed a new fully differential implementation of [3].The basic topology of the front-end is shown in Figure2.

This SBB maintains a charge balance in the capac-itors that are being read. The only signal path that is

φ 2

φ 2

φ 2

φ 2

φ 1

φ 1

φ 2

φ 2

-+

+-

φ 2

φ 2

φ 1

φ 1

φ P1 φ P1

φ P1 φ P1

φ P4 φ P4

φ P4φ P4

φ P1

φ P1

(1)

φ P4

φ P4

(4)

(1)(4)

(4)

CDPCDP

CDN CDN

(4)

(1)

(1)C3P

C3N

C3N

C3P

C1N

-VREF

+VREF

VMN

VMP+-

+-

+-

C4P

C4N

C2P

C2N

C1P

Figure 2: The circuit topology of the proposed SBB.

not balanced is the one connected to the middle elec-trode of the sensor. Otherwise, the main signal andfeedback paths together with operational amplifiers arefully differential, yielding good power supply and sub-strate noise rejection.

The amplifier used in the first integrator is a fullydifferential difference amplifier (FDDA) [4], which isutilised to convert the single-ended signal from the sen-sor into differential form.

Because the front-end is an SC implementation, it canbe time-multiplexed between multiple channels simplyby adding an individual integrator capacitor (C3P andC3N) together with selection switches for each channel,as shown in Figure 2.

2.3 Transfer function

To be able to analyse the functionality and behavior ofthis SBB and to implement it for a specific application,the transfer function for the circuit has to be derived.The transfer function can be shown to be

H(z) =VM

V REF=

2x

a+ (y − a) z−1, (3)

where

VM = VMP − VMN ,

x = CDP(n) − CDN(n) ,

y = CDP(n) + CDN(n) ,

a =C3

C2(2 · C1 + y + CPAD) ,

C1 = C1P = C1N ,

C2 = C2P = C2N ,

C3 = C3P(n) = C3N(n)

for each n ∈ {1 . . . 4}. Here, all symbols exceptCPAD are given in Figure 2. CPAD is the parasiticcapacitance from the sensor middle electrode to ground.

At DC, the transfer function simplifies to

H(1) =2x

y= 2

CDP(n) − CDN(n)

CDP(n) + CDN(n)

. (4)

It can be seen from (4) that not only good power supplyand substrate noise rejection are achieved by this dif-ferential structure, the output signal amplitude is alsotwice as large as in the single-ended case, thus improv-ing signal-to-noise ratio.

From (3), the -3 dB corner frequency fc of the circuitcan be solved as

cos

(

2πfc

fs

)

=−a2 + ay + 1

2y2

−a2 + ay. (5)

Here, fs is the sampling frequency. With (5), the -3dB point can be arbitrarily set anywhere between 0 andfs/2. Equation (5) could be approximated to a simplerform if the -3 dB point were much below fs/2. How-ever, if we are reaching towards low power consump-tion, fs needs to be as low as possible. Therefore, the-3 dB point will be relatively high compared to fs/2 andthe exact formula is required.

By substituting cos (2πfc/fs) = 0 into (5), the -3 dBpoint can be set to fs/4. Now C2 can be solved as

C2 =2 · C3 · (2 · C1 + y + CPAD)

(

1 +√

3)

y. (6)

Finally, the stability condition of the circuit is givenas

∣

∣

∣

∣

a− y

a

∣

∣

∣

∣

< 1 . (7)

When the -3 dB point is set at fs/4, the circuit is un-conditionally stable. This can be shown by substituting(6) into (7).

2.4 Effect of finite DC gain

As CMOS prosesses evolve towards deep submicronlinewidths, it gets harder to achieve high DC gain fromoperational amplifiers. Multi-stage amplifiers could beutilised, but every stage that is added reduces the currentefficiency of the operational amplifier.

Taking the finite DC gain of the amplifiers in Figure2 into account, a transfer function similar to (3) can bederived. With this function, the relative error caused bythe finite DC gain can be evaluated. The error dependsonly on y, C1, Ao1 and Ao2. In a typical case wheny = 5 pF and C1 = 2 pF , the absolute value of thiserror at DC is shown in Figure 3. In this plot, CPADhas not been taken into account for simplicity. Ao1 isthe DC gain of the FDDA, and Ao2 is the DC gain ofthe operational amplifier in the output integrator.

In Figure 4, contours from Figure 3 for different reso-lutions are presented. The indicated accuracy is reachedin the area up and right of each contour. From Figures3 and 4 it can be seen that to achieve a 12-bit accuracy,the open-loop gains of both amplifiers should be at least70 dB. An interesting phenomenon is that when gains

0

20

40

60

80

100

020

4060

80100

0

0.2

0.4

0.6

0.8

1

Ao1

[dB]

Ao2

[dB]

Rel

ativ

e er

ror

Figure 3: Relative error with finite open-loop gain.

are low, Ao1 and Ao2 balance each other. Theoretically,it could be possible to achieve 12-bit resolution withlower than 40 dB open loop DC gain.

40 50 60 70 80 90 10040

50

60

70

80

90

100

Ao1

[dB]

Ao2

[dB

]

12 B

ITS

11 B

ITS

10 B

ITS

12 BITS

11 BITS

10 BITS

Figure 4: Open-loop DC gain requirement for differentresolutions.

3 SIMULATION RESULTS

Thorough simulations were done for the presented SBBto verify its functionality and low power consumption.The operating voltage in all the simulations was 1.8V .In the worst case, the current consumptions of the op-erational amplifiers were simulated to be 33µA forthe FDDA and 10.5µA for the amplifier at the outputintegrator. The DC gains were simulated to be over80 dB for the FDDA and over 90 dB for the other am-plifier. Gain-bandwidth products were designed to be400 kHz, ten times higher than the sampling rate, andphase margins to be 60 degrees.

The capacitances of both the sensor element and in-ternal capacitors in the circuit may vary a lot, affect-ing the output loads of the amplifiers. Therefore, theamplifiers were designed to be as flexible as possible,including bias current control and programmable com-pensation.

A typical output spectrum is presented in Figure 5.Here, the differential signal amplitude at the SBB out-put is 456mV . The effect of the -3 dB corner frequencyat 2.5 kHz slightly attenuates the signal from the unat-tenuated value of 500mV . It can be calculated that thetotal harmonic distortion (THD) is 62 dB below the sig-nal.

0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency [Hz]

Pow

er [d

Bc]

Figure 5: Typical output spectrum.

An output spectrum with noise, obtained with tran-sient noise analysis, is presented in Figure 6. From thisfigure, it can be calculated that SNR is 58 dB in the1 kHz signal band.

0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency [Hz]

Pow

er [d

Bc]

Figure 6: Typical output spectrum obtained with tran-sient noise analysis.

SNDR is 56 dB and it is mostly limited by SNR. Asummary of the simulation results is given in Table 1.

Table 1: A summary of the simulation results.

Operating voltage 1.8VCurrent consumption ≤ 45µASNR 58 dBSNDR 56 dBTHD 62 dB

4 CONCLUSION

We have presented a new differential switched-capacitor front-end for capacitive microaccelerometers.The presented front-end maintains charge balance in thesensor element being read, avoiding distortion causedby nonlinear electrostatic forces. Transfer function, -3dB corner frequency and stability conditions were anal-ysed, together with the effect of the finite DC gain of theoperational amplifiers. The front-end achieves a maxi-mum simulated SNR of 58 dB. The worst case currentconsumption of the front-end was simulated to be 45µA from 1.8V supply.

Acknowledgments

The authors wish to thank Nokia Research Center, VTITechnologies Oy and National Technology Agency ofFinland (TEKES) for financial support.

Design tools were provided by Mentor Graphics.

References

[1] T. Lehtonen, J. Thurau, “Monolithic Accelerome-ter for 3D Measurements”, in “Advanced Microsys-tems for Automotive Applications 2004”, J. Vall-dorf, W. Gessner (eds), pp. 11–22, Springer 2004.

[2] T. Mineta, S. Kobayashi, Y. Watanabe, S. Kanauchi,I. Nakagawa, E. Suganurna, M. Esashi, “Three-axis Capacitive Accelerometer With Uniform AxialSensitivities”, Proc. Solid-State Sensors and Actua-tors Conference and Eurosensors, 1995, vol. 2, pp.554–557.

[3] H. Leuthold, F. Rudolf, “An ASIC for High-Resolution Capacitive Microaccelerometers”, Sen-sors and Actuators A, vol. 21, pp. 278–281, Febru-ary 1990.

[4] H. Alzaher, M. Ismail, “A CMOS Fully BalancedDifferential Difference Amplifier and Its Applica-tions”, IEEE Trans. Circ. Syst. II, vol. 48, pp. 614–620, June 2001.