A 37 ppm/oC Temperature Compensated CMOS ASIC with ±16 V Supply Protection

for Capacitive Microaccelerometers

Hyoungho Ko1, Ahra Lee2, Taedong Ahn2, Seung-Joon Paik1, Byoungdoo Choi1 and Dong-il “Dan” Cho1

1School of Electrical Engineering and Computer Science, Seoul National University, Korea 2SML Electronics, Inc., Seoul, Korea

Abstract- A high reliability CMOS-MEMS hybrid microaccelerometer system is presented. To enhance the temperature response and to minimize die-to-die variations, a low-noise continuous time front-end architecture with temperature compensation and parasitic cancellation is proposed. The temperature coefficients of the output bias and the scale factor are measured to be 37 ppm/oC and 27 ppm/oC, respectively. The bias instability level of the system is measured to be 42 μg. The integrated ±16 V power supply protection block gives the enhanced system reliability and reduced form-factor.

I. INTRODUCTION

With the continuously maturing Microelectromechanical Systems (MEMS) technologies, microaccelerometer has been successfully commercialized. In high-end applications such as automotive application, the performance requirements for dynamic range, temperature stability, and environmental reliability are very stringent. The capacitive micro-accelerometer is known to have several advantages when compared to the piezoresistive or piezoelectric micro-accelerometers with their good DC response, low noise performance, low drift and low temperature sensitivity [1]. Fig. 1 shows the wafer level hermetic packaged (WLHP) capacitive microaccelerometer fabricated using the Sacrificial Bulk Micromachining (SBM) process [2]. Sub-milli-gravity bias stability using this device was reported in [3]. The WLHP SBM device also accomplishes high sensitivity and environmental immunity [3].

This paper presents a CMOS-MEMS hybrid microsystem and circuit topologies for highly reliable microaccelerometer. The WLHP SBM device, temperature compensated circuit blocks, digital trimming and integrated power protection

Sensing direction

Sense electrode

Modulation electrodes

Glass wafer

Silicon wafer

Via-hole

Metal interconnection

Proof mass

Fig. 1. WLHP SBM microaccelerometer

circuit improve the system performances and the reliability while maintaining the low noise, the wide dynamic range and the small form-factor.

II. CMOS-MEMS HYBRID SYSTEM ARCHITECTURE Fig. 2 shows the schematic of the implemented accelerometer system. The inertial force exerted by applied acceleration compels the proof mass to move, and this motion produces the capacitance change between movable electrodes and fixed electrodes. The chopper-stabilized continuous-time charge amplifier amplifies this capacitance change. The high chopping frequency of 1 MHz reduces the unwanted low frequency component including 1/f noise and dc offset. The high pass filter removes the low frequency again, and this enhances the bias stability effectively. The continuous-time architecture is chosen to achieve both low noise and low power, compared to the switched capacitor (SC) method [4]. The acceleration output is obtained by the sample-and-hold and the low pass filter. The bandgap reference, the current bias, and the oscillator are designed to minimize the temperature deviations. To cancel the parasitic effects and to improve the temperature response, a capacitive front-end architecture with digital trimming and temperature compensation is proposed. The integrated power protection block provides the regulated internal supply, and protects the internal circuits from reverse battery. The integration of the protection blocks gives many benefits of the improved reliability, the reduced cost and small footprint. The protection against the over-voltage and reverse-battery connection is a major required function, i.e. for

Cap

. arr

ayC

ap. a

rray

Fig. 2. System block diagram of CMOS-MEMS hybrid microaccelerometer system

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IEEE 2007 Custom Intergrated Circuits Conference (CICC)

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automotive applications [5], and this is the first accelerometer system integrated with power supply protection.

III. CIRCUIT BLOCKS A. Digitally trimmable temperature compensated front-end The separated two chip solution of MEMS device and CMOS electronics provides many advantages, because it allows the specialized MEMS process such as bulk micromachining or WLHP. However, in the two chip solution, the parasitic capacitances are increased, and these can severely limit the dynamic range of the capacitive sensors [6].

Fig. 3 shows the proposed schematic of the front-end capacitive interface. The transfer function of the front-end is expressed as (1). The DC path of the capacitive input terminal, which avoids the charge accumulation, is implemented by M1. The long channel length (W/L=0.8 μm/300 μm) and the gate biasing of 2.5 V enable M1 to have the equivalent resistance of larger than 100 MOhm [7]. The offset and gain variations of the front-end due to the parasitic effects and fabrication imperfections is minimized by adopting the digital trimming architecture. CU, CD and CF are digitally trimmable 10 bit capacitor array. The output offset due to the parasitic capacitances, CP1 and CP2, is canceled by trimming the CU and CD. The front-end gain is also adjusted by trimming the capacitor array of CF.

Fig. 3. Schematic of front-end capacitive interface

( )

1 2

( ) ( )1

where, ,

FOUT REF TOTP TOTN AC

F F

TOTP P U P TOTN N D P

sRV s V C C V ssR C

C C C C C C C C

= − −+

= + + = + + (1)

As expressed in Fig. 3 and (1), the reference voltage, the

reference current and the oscillation frequency are the key factors that determine the front-end output. Moreover, the output frequency of the oscillator is a function of the reference current and the reference voltage. Thus, the temperature response of the front-end is determined by the temperature characteristics of these circuit blocks. The full operating temperature range of this system is from -45 oC to 125 oC. The reference voltage is generated by using a bandgap reference,

which has an over-temperature deviation of 5 mV. The reference current block, which supplies the bias currents of 4 μA to other sub-circuits, has an over-temperature deviation of 0.2 μA. The 1 MHz oscillator has an over-temperature deviation of 4 %. An excellent temperature response of the front-end is achieved by minimizing the temperature characteristics of these circuit blocks. B. Over-voltage and reverse-battery protection

The schematic of the over-voltage and reverse-battery protection block is shown in Fig. 4. The 16 V high voltage transistors are used in this block. The operation of the over-voltage protection is similar to the conventional low drop-out (LDO) regulator [8]. M1 roles the pass transistor of the LDO, and the regulated supply is determined by the feedback loop, which controls the gate voltage of M1. When the over-voltage is applied, the VGS3 becomes higher than VGS2, and this makes the IDS4 larger. Thus, the IDS5 also becomes larger, and the gate voltage of M1 becomes higher. Therefore, the internal supply voltage is regulated to the desired value.

The operation of the reverse-battery protection is as follows. R1 and R2 are the current-limiting resistors, and the D1 and D2 are the Schottky diodes. These devices make the bulk voltage of M1 to be high, when both the normal and reverse supply. When the reverse supply is applied, the bulk and gate voltages of M1 become high. Thus the M1 becomes turned off, and the internal circuits are protected.

M1 (Pass Tr.)

M2 M3

D1 D2R1 R2External supply (VDD)

GND

Internal supply

M4

M5 positive referencenegative

reference

always VDD(normal & reverse battery)

Fig. 4. Schematic of over-voltage and reverse-battery protection C. Bandgap voltage reference Fig. 5 shows the schematic of the bandgap voltage reference. The proportial-to-absolute-temperature (PTAT) current (IDS12) and VBE2, which has a negative temperature coefficient, generate a temperature-insensitive reference voltage. The temperature characteristics of the bandgap voltage reference are plotted in Fig. 6. The temperature deviation over temperature is simulated to be 5 mV in typical case. D. Temperature compensated current bias The schematic of the temperature compensated current bias, which supplies the reference currents to other blocks, is shown in Fig. 7. The negative feedback loop of M1 and M2 enhances

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the temperature characteristics. For example, if VGS2 is increased due to the temperature change, IDS1 is decreased, and this results the decreased VGS2. The temperature characteristics of the reference current bias are shown in Fig. 8. The temperature deviation over temperature is simulated to be 0.2 μA in typical case.

Fig. 5. Schematic of bandgap voltage reference

Typical case

BJT slow corners

BJT fast corners

Temperature deviation: 5 mV

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

-50 -25 0 25 50 75 100 125-50 -25 0 25 50 75 100 125Temperature (oC)

Out

put v

olta

ge (V

)

Fig. 6. Temperature vs. bandgap reference output

Fig. 7. Schematic of temperature compensated current bias

-50 -25 0 25 50 75 100 125

Temperature (oC)

-3.25

-3.50

-3.75

-4.00

-4.25

-4.50

-4.75

Bias

cur

rent

(μA

)

Typical case

PMOS fast corners

NMOS fast corners

Temperature deviation: 0.2 μA

Fig. 8. Temperature vs. reference current bias

E. Temperature compensated oscillator The schematic of the temperature compensated oscillator is shown in Fig. 9. The oscillation frequency is expressed as (2). The charging and discharging current, i, are generated by the temperature compensated current bias. The voltage references, which determine the upper and lower amplitudes of the triangular wave, are generated by the bandgap reference. C1 is a poly-to-poly (PIP) capacitor, and the PIP capacitor is known to have very low temperature coefficient. Thus, the very low temperature coefficient of the output frequency, fosc, can be achieved. The temperature deviation over temperature is simulated to be 4 % in typical case.

12oscREF

ifC V

=⋅ ⋅

(2)

+

-

REF3 V2REF

1 V2

i

C1

i

INV

OSCcharging path

discharging path

Triangular wave

Squarewave

Fig. 9. Schematic of temperature compensated oscillator

IV. FABRICATION RESULTS AND PERFORMANCE

EVALUATIONS

The fabricated capacitive interface ASIC and the CMOS-MEMS hybrid accelerometer system are shown in Fig.10 and Fig. 11, respectively. The scale factor, input range and nonlinearity is measured to be 2 V/g, ±1 g and 0.7 %FSO, respectively, as shown in Fig. 12(a) and Fig. 10(b). The bias instability on room temperature is measured to be 42 μg on root Allan variance plot, as shown in Fig. 12(c). The temperature characteristics are shown in figure 12(d). The maximum output deviation over temperature is less than 25 mg, thus the temperature coefficient of the output bias over temperature is 37 ppm/oC. The temperature coefficient of the scale factor stability is 27 ppm/oC by subtracting the -1 g output from 1 g output.

Capacitivefront-end

Analogblock

Low pass filter& output driver

±16V supply protection

Charge pum

p

EEPROM

Dig

ital b

lock

2 mm

2.2

mm

Fig. 10. Fabricated capacitive interface ASIC

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MEMS accelerometer

CMOS ASIC

Fig. 11. Hybrid accelerometer system (decapped)

0.0 0.1 0.2 0.3 0.4 0.5-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Out

put (

V)

Time (s)

B&K 4805 reference Fabricated accelerometer

(a) Time-domain output @ 40 Hz, 0.5 g

0.0 0.2 0.4 0.6 0.8 1.00.0

0.5

1.0

1.5

2.0

Out

put (

V)

Input acceleration (g) (b) Input-ouput characteristics

100 101 102 103 10410-5

10-4

10-3

sampling time (s)

alla

n va

rianc

e (g

)

Bias instability ~ 42 μg

Cluster time τ = n* τ0 (sec)

Roo

t Alla

n Va

rianc

e σ

(τ) (

g)

(c) Root Allan variance measurement

-40 -20 0 20 40 60 80 100 120-50

-40

-30

-20

-10

0

10

20

30

40

50

Out

put d

evia

tion

(mg)

Temperature (oC)

A: Temp. deviation with -1 g bias B: Temp. deviation with 0 g bias C: Temp. deviation with 1 g bias D: C-A

(d) Temperature characteristics Fig. 12. Measured performance results

V. CONCLUSIONS

A high reliability CMOS-MEMS hybrid microaccelerometer system is presented. A very low bias instability level of 42 μg is achieved by adopting the chopper-stabilized continuous-time architecture. The capacitive front-end architecture with digital trimming and temperature compensation is implemented to minimize the die-to-die variations due to the parasitic capacitances and to improve the temperature response. The temperature coefficients of the output bias and the scale factor are measured to be 37 ppm/oC and 27 ppm/oC, respectively. The integrated ±16 V power supply protection block enhances the system reliability.

ACKNOWLEDGMENTS

This work was supported in part by MIC & IITA through IT Leading R&D Support Project.

REFERENCES

[1] N. Yazdi, F. Ayazi, K. Najafi, "Micromachined inertial sensors,” Proc.

IEEE, vol. 86, pp. 1640-1659, August 1998 [2] H. Ko, et al., "Wafer-level Hermetic Packaged, Two-chip

Microaccelerometer Suitable for Tactical and Inertial Applications," Proc. TRANSDUCERS '05, vol. 1, pp. 507-510, June 2005

[3] H. Ko et al., "Wafer-level hermetic packaged microaccelerometer with fully differential BiCMOS interface circuit," Sens. Actuators A: Phys., in press, 2007

[4] Jiangfeng Wu, G.K. Fedder, L.R. Carley, "A low-noise low-offset capacitive sensing amplifier for a 50ug/rtHz monolithic CMOS MEMS accelerometer," IEEE J. Solid. State. Circ., vol. 39, pp. 722-730, May 2004

[5] K. Sakamoto, et al., "An intelligent power IC with reverse battery protection for fast-switching high-side solenoid drive," IEEE Trans. Electron Dev., vol. 46, August 1999

[6] A. Sharma, M.F. Zaman, F. Ayazi, "A 104dB SNDR Transimpedance-based CMOS ASIC for Tuning Fork Microgyroscopes," Proc. CICC 2006, pp. 655-658, September 2006

[7] Hao Luo, et al., "A post-CMOS micromachined lateral accelerometer," IEEE/ASME J. Microelectromech. Syst., vol. 11, pp. 188-195, June 2002

[8] G.A. Rincon-Mora and P.E. Allen, "A low-voltage, low quiescent current, low drop-out regulator," IEEE J. Solid. State. Circ., vol. 33, pp.36-44, January 1998

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