IEEE 2007 report Part II G.Villani

05/12/2007 G.Villani 1

IEEE 2007 report

Part II

G.Villani

05/12/2007 G.Villani 2

• NSS section• Trend on detectors• Noise studies on sub-micron

devices

CC

D

DR

IFT

CM

OS

OT

HE

RS

3D

2006 2007

CC

D

DR

IFT

CM

OS

OT

HE

RS

3D

• >1500 participants

• Nuclear Science & Medical Imaging

• Detectors and RO Electronics development

05/12/2007 G.Villani 3

Giuliana Rizzo

INFN and University, Pisa

on behalf of SLIM5 Collaboration

Recent developments on deep N-well CMOS MAPS

with sparsification capability

2007 IEEE Nuclear Science Symposium2007 IEEE Nuclear Science Symposium

Honolulu, October 27-November 3 2007Honolulu, October 27-November 3 2007

http://www.unipi.it/princ.html

05/12/2007 G.Villani 4

Recent developments on deep N-well CMOS MAPS with sparsification capability

Original concept proposed by RAL ~ 4 years ago

Enrico Giulio Villania, P.P. Allportb, A. Evansb, G. Casseb, M. Tyndela, R. Turchettaa, J.J. Velthuisb

PRE SHAPER DISC LATCHPrinciple of operation The undepleted epitaxial layer acts

as a potential well for electrons Signal (~1000 e-) collected through

diffusion by the n-well contact Charge-to-voltage conversion

provided by the sensor capacitance small collecting electrode

Simple in-pixel readout (additionals nwells for PMOS not allowed in standard MAPS design!)

sequential readout

• Full in-pixel signal processing realized exploiting triple well CMOS process

• Deep nwell (DNW) as collecting electrode

Gain independent of the sensor capacitance collecting electrode can be extended

• Area of the “competitive” nwells inside the pixel kept to a minimum:, they steel signal to the main DNW electrode.

• Fill factor = DNW/total n-well area ~90% in the prototype test structures

• Pixel structure compatible with data sparsification architecture to improve readout speed.

Design and characterization of a novel, radiation- resistant active pixel sensor in a standard 0.25 m CMOS technology

05/12/2007 G.Villani 5

Submitted DNW MAPS Chips 130 nm ST

APSEL1Sub. 12/2004 Sub. 8/2005

Sub. 8/2006 APSEL2_90Sub. 9/2006

Sub. 11/2006

APSEL2D

Sub. 7/2007

APSEL3D APSEL3_T1, T2

TEST_STRUCT

ST 130 Process characterization

APSEL0

Preamplifier characteriz.

Improved F-E8x8 Matrix

APSEL2M

Cure thr disp. and induction

APSEL2T

Accessible pixel Study pix resp.

ST 90nm characterization

Test digital ROarchitecture

8x32 matrix. Shielded pixelData Driven sparsified readout

Test chips to optimize pixel and FE layout

APSEL2_CT

Test chips forshield, xtalk

Sub. 5/2007 Sub. 7/2007

05/12/2007 G.Villani 6

90Sr electrons

Landau

mV

S/N=14

Cluster signal (mV)

• Noise ENC = 50 e-

• Indications of small cluster size (1-2 pixels)

• Cluster Signal for MIP (Landau MPV) 700 e-

S/N = 14

Cluster Multiplicity

3x3 matrix, full analog output

APSEL2 3x3 matrix: analog output

Noise events properly normalized

12

Cluster seed

Hit pixels in 3x3 matrix

50m pixel pitch

05/12/2007 G.Villani 7

8x8 matrix digital outputSequential readout

Threshold dispersion ~ 100 e-

APSEL2 8x8 matrix: digital output

Average Noise ENC = 50 e-

Noise scan: hit rate vs discriminator threshold

Vthr

Noise

90Sr electrons: single pixel spectrum

Spectrum from analog output

Differential spectrum from digital output

Vth (mV)

Noise (mV)

05/12/2007 G.Villani 8

Fast Readout Architecture for MAPS

• Data-driven readout architecture with sparsification and timestamp information under development.

• In the active sensor area we need to minimize:– the logical blocks with PMOS to minimize the competitive nwell area and preserve the

collection efficiency of the DNW sensor.– digital lines for point to point connections to allow scalability of the architecture with matrix

dimensions and to reduce cross talk with the sensor underneath.

Matrix subdivided in MacroPixel (MP=4x4)with point to point connection to theperiphery readout logic:– Register hit MP & store timestamp– Enable MP readout – Receive, sparsify, format data to output

bus

APSEL2D chip received in July, tests started- Pixel response and noise as expected- Readout seems to work as expected, but

crosstalk is present and interfering with operations

Data lines in common

2 MP private lines

MP 4x4 pixels

Periphery readout logic

Column enable lines in common

Data out bus

See Poster N24-260

05/12/2007 G.Villani 9

From APSEL2 to APSEL3

• Cross talk between digital lines and substrate– Requires aF level parasitic extraction to be modeled

• Relatively small S/N ratio (about 15)– Especially important if pixel eff. not 100%

• Power dissipation 60 W/pixel– Creates significant system issues M1

M2

M3

M5M6

M4

Analog routing (local)

Digital routing (local/global)

Shield (VDD/GND)

APSEL3 Redesigned front-end/sensor

APSEL3D Digital lines shieldingAPSEL2 issues

APSEL3 expected performance

FE Version Geom.

ENC (PLS)

(@5

S/N

APSEL2 data A 50 e- 88.7% 14

APSEL3

Transc.

A

B

41 e-

41 e-

93.6%

99.4%

16

18

APSEL3Curr. Mirror

A

B

31 e-

31 e-

98.6%

99.9%

22

24

Optimize FE Noise/Power: • Reduce sensor capacitance (from 500 fF to ~300

fF) keeping the same collecting electrode area– reduce DNW sensor/analog FE area (DNW

large C)– Add standard NWELL area (lower C) to

collecting electrode.• New design of the analog part Optimize sensor geometry for charge collection efficiency using fast simulation developed:

– Locate low efficiency region inside pixel cell– Add ad hoc “satellite” collecting electrodes

APSEL3 Power=30 W/pixel: Perfomance

05/12/2007 G.Villani 10

An example of sensor optimization

DNW collecting electrode

Competitive Nwells

3x3 MATRIX old sensor geom

Satellite nwells connected to central DNW elect

3x3 MATRIX sensor optimized

• With old sensor geometry (left) Efficiency ~ 93.5% from simulation (pixel threshold @ 250 e- = 5xNoise)

• Inefficient regions shown with dots (pixel signal < 250 e-)• Cell optimized with satellite nwells (right) Efficiency ~ 99.5%

05/12/2007 G.Villani 11

Conclusions & Perspectives

• DNW MAPS design (130 nm, triple well STM CMOS technology) looks very promising for application in future thin trackers with fast readout requirements. – Latest DNW MAPS (APSEL2) structures, with optimized noise and

threshold dispersion, showed good sensitivity to ionizing radiation (soft X and beta).

– New improvements in noise, power, charge collection efficiency implemented in the APSEL3 series (just received).

– Digital crosstalk can be kept under control using metal shield between sensor and digital lines.

– Data driven readout architecture with sparsification and timestamp under development: 8x32 matrix produced, 32x128 matrix in production by end Nov. 2007.

• Test beam foreseen in summer 2008 to measure DNW MAPS rate capability, efficiency, resolution.

• DNW MAPS sensors, developed within the SLIM5 Collaboration, now considered by the SuperB and ILC communities for application in their silicon vertex trackers.

• Contacts: [email protected]

05/12/2007 G.Villani 12

A Photogate Monolithic ActivePixel Sensor with Lateral Electric

Field to Improve Its ChargeTransfer-Efficiency

05/12/2007 G.Villani 13

motivation for photogate:

• why classical MAPS are notthe optimum solution?• SNR at the limit, almost no margin forincrease of noise; possible sources are numerous: Ileak, power supply, etc.,• large charge diffusion for single small charge collecting diode;• attenuation of signal due to Cconv increase for bigger or more diodes per pixel.

A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field

Photogate:• large coverage of active area;• large conversion factor;

05/12/2007 G.Villani 14

Standard photogate:• Electrons collected distribute evenly under the gate;• Surface states trap electrons, decreasing efficiency


05/12/2007 G.Villani 15


Enhanced photogate:• potential difference allows electrons drift under the gate; • less trapping, increased efficiency

05/12/2007 G.Villani 16


Simulations photogate:• 3D model used for simulation• E-field cut @ 5nm below SiO2 interface• Charge collected vs. bias

05/12/2007 G.Villani 17


Test structure TSMC 0.25umTests started October 2007Laser source and Fe55

Test structure no laser

Test structure with laser Test structure with Fe55

05/12/2007 G.Villani 18


Conclusions• Applying potential difference between opposite ends of the photogate proved to prompt charge transfer (surface transport) either to:• one end of the photogate (where it waits for closing transfer gate) or• directly to the sensitive node (where it can be probed via i.e. source follower).• Both photogate options, viz. with and withouttransfer gate allow CDS, although:

• It can be done within one access for pixel withtransfer gate (INT, RO, TXon, RO, RST, TXoff... ),• It is required to store two full frames in memoryand to do CDS after the readout of the second frameis accomplished (RST, RO, INT, RO,... ), .• The improved photogate may be consideredfor applications, where « big pixels » are required,i.e. central tracker @ ILC instead of TPC (Si pixeltracker proposed by Chris Damerell ALCPG 2007)

Contacts: [email protected]

05/12/2007 G.Villani 19

Development of 3D Detectors for Very High Luminosity Colliders

Celeste Fleta

University of Glasgow

October 30, 2007

On behalf of the CERN-RD50 Collaboration

05/12/2007 G.Villani 20

This talk shows a review of the work of RD50 on the use of 3D detectors as trackers in high radiation environments

1. The CERN-RD50 collaboration

2. Silicon 3D detectors

4. Different approaches• Single sided 3D• Double sided 3D• Full 3D

X

Y

0 20 40 60

0

10

20

30

40

50

3. Simulation work

05/12/2007 G.Villani 21

3D detectors

• Proposed by S. Parker et al. NIMA395 (1997). • 3-d array of p and n electrodes that penetrate into the

detector bulk• Lateral depletion

– Maximum drift and depletion distance set by electrode spacing

– Thicker detectors possible– Reduced charge sharing – Reduced collection time and depletion voltage

• Technologically complex

e-

h+

Particle

-ve

+ve

p-electrode

n-electrode

~300um e-

h+

Particle

-ve

+ve

p-electrode

n-electrode

~300um

e- h+

Particle

+ve -ve

p-columnn-column

~50um

e- h+

Particle

+ve -ve

p-columnn-column

~50um

planar 3D

Rad hard

05/12/2007 G.Villani 22

Simulation study of 3D sensors

• University of Glasgow• Modified Perugia 3-level trap model

– Trap parameters modified to match experimental trapping times

• Model accuracy assessed by comparing with results from planar devices

P-type FZ trap model

Depletion voltages and radiation damage

0

20

40

60

80

100

120

140

160

0 2E+15 4E+15 6E+15 8E+15 1E+16 1.2E+16

Fluence (Neq/cm^2)

De

ple

tio

n v

olt

ag

e (

V)

Full 3D, ptype, Medipix (55um)

Full 3D, ptype, 3-column ATLAS

P-type trap models: Depletion voltages

300

350

400

450

500

550

600

0 1E+14 2E+14 3E+14 4E+14 5E+14 6E+14 7E+14

Fluence (Neq/cm2)

De

ple

tio

n v

olt

age

(V

)

Default p-type sim

Modified p-type sim

Experimental

(Data from M. Lozano et al., IEEE Trans. Nucl. Sci., vol. 52 (2005))

[D. Pennicard et al., 10th RD50 Workshop, June 2007]

05/12/2007 G.Villani 23

Single type column detectors (ITC-irst)

• Variation of the STC-3D developed at BNL– Ohmic contact is implemented on the same side of the column etching: true one-

sided detector (backside not processed)

• Fabricated by ITC-irst/CNM– Strip, pad detectors– 300 or 500 µm p-type substrate – Hole depth 130-150 µm, diameter ~10 µm– Columns not filled, just passivated

• 2-stage depletion

1. Lateral depletion

2. Planar-like depletion towards the back contact

(Confirmed with C-V and CCE measurements, see Scaringella et al., NIMA 579 (2007))

Electrons swept away by transversal field and drift to nearest column (~40 µm)

Holes drift in central region and diffuse/drift to p+ contact (~300-500 µm)

p+

n+p--

p+

n+p--

hole

Hol

e d

epth

~ 1

20μ

m

hole metal strip

hole

Hol

e d

epth

~ 1

20μ

m

hole metal strip

05/12/2007 G.Villani 24

Position resolved CCE in STC-3D strip detectors

• Laser tests with ATLAS SCT readout• University of Freiburg• 40MHz ATLAS SCT EndCap electronics

– Binary readout– Shaping time 20ns

• Laser spot 4-5µm, penetration 100µm• STC-3D AC coupled strip detector

Vbias = 80V

Vbias = 20V

~25% signal drop

• Lateral depletion ~20V• Non-homogenous response: low

field region in interstrip area • Results after irradiation and with β

source in S. Kuehn’s talk (N44-2)

05/12/2007 G.Villani 25

CCE in STC-3D irradiated strip detectors

[G.Kramberger et al., 10th RD50 Workshop, June 2007]

CCE after neutron irradiation

25ns transient current integration

•As expected, STC-3D are not radiation hard:•E-field determined by doping (higher doping large E). •When the volume between columns is fully depleted, the electric field cannot be increased further •Essential to counteract trapping

•Very non-homogenous response due to variations in the electric field (saddle in mid-region)

• Position sensitive TCT measurements in Ljubljana (see poster N24-150 )– IR laser, FWHM ~7µm – STC-3D DC coupled detector, 64 x 10 columns– 80µm pitch, 80µm between holes

~40%

~60%

100%

~40%

~60%

100%

3 43 4

05/12/2007 G.Villani 26

Double sided 3D detectors

• Proposed by IMB-CNM (Spain)• Electrodes etched from opposite sides of the wafer • Double side processing• No sacrificial wafer is required

2.9m

TEOS

PolyJunction

2.9m

TEOS

PolyJunction

n-Si

(p+)

IMB-CNM currently processing a first run of n-type wafers with Medipix2, Pilatus2 and strip detectors

Double-sided technology also being investigated by ITC-irst see talk N18-3

27.5m

05/12/2007 G.Villani 27

50000

40000

3000

0

15000

2500

7500

D (m)

Z(

m)

0 25 50

230

240

250

260

270

280

290

300

19000017000015000013000011000090000700005000030000200001000050000

Double-sided 3D, p-type,0neq/cm2, back surface

n+

p+

ElectricField (V/cm)

Double sided 3D detectors

• Short charge collection times because both carrier types mainly drift horizontally

• High drift velocity as the electric field can be increased even after full depletion.

• Disadvantages: low field region below columns

700

00

25000

2500

0

10000

2500

D (m)

Z(

m)

0 25 50

230

240

250

260

270

280

290

300

19000017000015000013000011000090000700005000030000200001000050000

Double-sided 3D, p-type,1e+16neq/cm2, back surface

n+

p+

ElectricField (V/cm)

Undepleted

No damage 1016 neq/cm2

100V bias

• 250µm columns both devices• DS-3D has slightly higher

collection at low damage (greater device thickness!)

• But at high fluence, results match standard 3D

Simulated CCE, 55m pitch

0

5

10

15

20

25

0 2E+15 4E+15 6E+15 8E+15 1E+16 1.2E+16

Fluence (neq/cm2)

Ch

arg

e co

llect

ed (

ke-)

Double sided 3D, 250umcolumns, 300um thick

Full 3D, 250um thick

Performance comparable to standard 3D

05/12/2007 G.Villani 28

Full 3D detectors

• Project Glasgow/Diamond Light Source Synchrotron to develop 3D detectors for X-ray diffraction experiments

– Fabrication by IceMOS Technology Ltd. (Northern Ireland)• Full 3D detectors on n-type Si • Prototype 3D detectors will be integrated and tested with

existing r/o electronics:– Medipix2, Pilatus2, Beetle readout chips– Readout in p-electrodes hole collection– All contacts on the top need to route metal lines

connecting all n-electrodes (biasing)• Fabrication: start with a thick (~500 μm) wafer, create

electrodes from the top (~250 μm), then grind/polish to expose electrodes.

Poly-P+

P+P+N+ N+ N+

Si-N

SiO2

Poly-P+

P+P+N+ N+ N+

Si-N

SiO2

P+P+N+ N+ N+

Si-N

Metal contacts

P+P+N+ N+ N+

Si-N

Metal contacts

05/12/2007 G.Villani 29

Conclusions• Ongoing work of RD50 in 3D detectors

• Promising candidates as vertex sensors for extreme radiation environments

• Low depletion voltage, good charge collection even for s-LHC irradiation levels

• STC-3D detectors fabricated and tested succesfully+ Simple fabrication process, useful to tune in the technology and

gain experience with testing methods- Long charge collection times, can be used in experiments that do

not need a fast response

• Double sided and full 3D available soon

• More information: http://rd50.web.cern.ch/RD50/

05/12/2007 G.Villani 30

Minimum Noise Design of Charge Amplifiers with CMOS Processes in

the 100 nm Feature Size Range

L. Rattia,c, M. Manghisonib,c, V. Reb,c, V. Spezialia,c, G. Traversib,c

aUniversità degli Studi di Pavia

bUniversità degli Studi di Bergamo

cINFN Pavia

IEEE Nuclear Science Symposium and IEEE Nuclear Science Symposium and Medical Imaging ConferenceMedical Imaging Conference

November 2 2007 – Honolulu, Hawaii, USANovember 2 2007 – Honolulu, Hawaii, USA

05/12/2007 G.Villani 31

Motivation

Device scaling has enabled the use of CMOS processes in the fabrication of high performance front-end circuits for radiation detectors

Constant technology monitoring is necessary to

keep design criteria and methodologies up to date

oppose process obsolescence

study scaling effects on the main design parameters

Continuous miniaturization meets the demand for increased spatial resolution, denser functional packing and higher ionizing radiation hardness set by the experiments at the next generation colliders (LHC upgrade, ILC, Super B-Factory)

CMOS processes in the 100 nm feature size range now being considered for the design of analog front-end circuits

05/12/2007 G.Villani 32

HCMOS9 - 130 nm CMOS090 - 90 nm

Noise performance analysis in analog front-end channels based on experimental characterization of devices from a 130 nm and a 90 nm CMOS technologies

VDD=1.2 V

tOX=2 nm

COX=15 fF/m2

VDD=1 V

tOX=1.6 nm

COX=18 fF/m2

All the interesting design parameters – input device bias condition, dimensions and polarity, peaking time, detector capacitance – taken into account

Emphasis on second order effects and scaling related phenomena

Focused on front-end design for pixel and microstrip detectors under low power dissipation constraints

Analysis of total ionizing dose (TID) effects in view of applications to harsh environments

Content

05/12/2007 G.Villani 33

reset network

1

CinCD

T(stp)

CF

Q

en

in

detector

charge preamplifier

shaper

CD=detector capacitance+strays

CF=feedback capacitanceCin=input capacitance

tp=peaking time

T(stp)=shaper transfer function

In a charge sensitive amplifier (CSA), noise performance are mostly dependent on the input device noise features

Noise in the detector leakage current and in the reset network not considered

Model of charge measuring system

05/12/2007 G.Villani 34

reset network

1

CinCD

T(stp)

CF

Q

en

in

detector

charge preamplifier

shaper

en

• kB Boltzmann’s constant• T absolute temperature• αw excess noise coefficient • γ channel thermal noise coefficient• n proportional to the subthreshold ID-VGS slope

• gm transconductance

Model of the charge measuring system

fαf

w

2n

fA

Sdfed

series white noise

• channel thermal noise

n

g

T4kS

W

m

Bw ,

WLC

KA

OX

ff

• Kf 1/f noise parameter• αf slope-related parameter

series 1/f noise

• technology dependent contribution

• both kf and αf depend on the polarity of the DUT (f,s=0.85 for NMOS, 1.05÷1.2 for PMOS)

Gf,f

AS

dfid f,G

w,G

2n

jjGw, I2qS

• Kf,G 1/f noise parameter

• f,G slope-related parameter (~0.9)

• L gate-source/drain overlap

parallel white noise

• full shot noise in the gate current

parallel 1/f noise

• 1/f noise in the gate current

S D

G

IGCIGDIGS

• q elementary charge• Ij contributions to the gate current (IGC, IGS and IGD)

ΔL WII

ΔL-LWI

KA2GD

2GS

2GC

Gf,Gf,

05/12/2007 G.Villani 35

en

in

The ENC equation includes:

a parallel (white and 1/f) noise related contribution

•A3 and A4(f,G) are shaping coefficients

•Sw,G and Af,G depend on input device bias condition, dimensions and polarity

The results presented here have been obtained in the case of an RC2-CR shaping stage following the CSA

1

pf,Gf,G4pw,G31

pff2p

w12

inFD2 Gf,Gf,ff tA A2tSAtA A2

tSA

CCCENC

Equivalent noise charge

a series (white and 1/f) noise related contribution•A1 and A2(f) are shaping coefficients

•Cin and Sw depend on input device bias condition, dimensions and polarity

•Af depends only on gate dimensions in NMOS devices; it depends also on bias conditions in PMOS devices

•1/f noise contribution to the ENC is peaking time dependent

05/12/2007 G.Villani 36

10

100

1000

10-9 10-8 10-7 10-6 10-5

Peaking time [s]

EN

C [

e rm

s]

NMOS - 90 nm process

W/L=41/0.20, CD=500 fF,

ID=10 A, V

D=0.5 V

1/f series

1/fparallel

whiteseries

whiteparallel

Gate current no longer negligible in processes with sub-3 nm gate oxide thickness due to direct tunneling

Sizeable parallel noise contribution found in 90 nm devices

In CSAs, parallel white noise may provide a significant ENC contribution already at tp=100 ns

Contribution from parallel 1/f noise mostly negligible

Noise in 90nm CMOS process

05/12/2007 G.Villani 37

Optimum ENC achieves its minimum value at a peaking time of a few hundreds of ns and rises again due to white parallel noise contribution

100

1000

1

10

100

10-9 10-8 10-7 10-6 10-5

Op

tim

um

EN

C [

e rm

s]

Op

timu

m w

idth

[

m]

Peaking time [s]

CD=500 fF

ID=10 A

VD=0.5 V

L=0.13 mL=0.20 mL=0.35 m


Optimum width peaks at tp100 ns, then decreases due to gate current, and parallel noise, dependence on W

Optimum ENC and Width in 90nm CMOS

05/12/2007 G.Villani 38

20

40

60

80100

300

500

700

0 0.2 0.4 0.6 0.8 1

EN

C [

e rm

s]

Drain voltage [V]


W/L=410/0.20, CD=5 pF,

ID=100 A


W/L=410/0.20C

D=5 pF

ID=100 A

tp=1 s

tp=100 ns

total ENC

white parallelcontribution

Changes in the ENC at tp>100 ns due to drain voltage related variations in the gate current

Minimum is achieved at VDG=0, when IGD=0.

VD

IGDTR

IOD

E

VD related effects in 90nm CMOS FE

05/12/2007 G.Villani 39

Significant ENC variations (about 20% at tp=100 ns) only in the peaking time range where series 1/f noise is predominant

Virtually no changes in the extreme regions of the explored range no significant TID effects on white series and parallel noise

Assuming a 100 m thick detector

•S/N from 11 tp 10 @ tp=10 ns

•S/N form 28 to 23 @ tp=100 ns

90 nm appears to be harder than 130 nm process

TID effects in 90 nm NMOS input front-end

100

1000

10-9 10-8 10-7 10-6 10-5

Peaking time [s]

EN

C [

e rm

s]


W/L=480/0.20, CD=5 pF,

ID=100 A

1/f series

whiteseries

total ENC

beforeirradiation

10 Mrad (60Co)

V. Re et al., “Impact of lateral isolation oxides on radiation-induced noise degradation in CMOS technologies in the 100 nm regime”, 2007 NSREC Conference, to be published in IEEE TNS

05/12/2007 G.Villani 40

Results from front-end design optimization in 130 nm and 90 nm CMOS technologies for application to pixel and microstrip detector readout have been presented

Optimization procedure takes into account second order effects and scaling related phenomena

Kf dependence on overdrive voltage in PMOS devices

parallel contribution due to the noise in the input device gate current

dependence of the parallel noise contribution on the drain voltage in the input device

Data from TID characterization were used to predict preamplifier performances in harsh environment

The proposed model provides a comprehensive tool which can be easily extended to other ultra deep submicron technologiesUse of high K gate insulators may modify radiation hardness and noise properties in next CMOS nodes

Contacts: [email protected].

Conclusion

05/12/2007 G.Villani 41

V P C on IEEE 2007

• Overall always interesting (the most comprehensive and attended conference on electronic aspects of NSS);

• However not many novel or new solutions in terms of detections or readout;• RAL established presence with novel solutions presented every year ( serial

powering system, novel CMOS detectors, improved CCD… just from PPD);• Low power solutions becoming increasingly important.

Documents

IEEE 2007 report Part II G.Villani