An Adaptive Neural Spike Detector with Threshold-Lock Loop

Abstract—We present the design of an adaptive neural spike detector that dynamically adjusts the spike detection threshold based on the signal to noise ratio of the neural data sets. We propose a self-learning architecture, with a threshold-lock loop that feeds back a spike sorting performance index to the FSM inside the adaptive spike detector. The FSM references this performance index and dynamically determines an optimum threshold level for the incoming neural data sets. The architecture enables an autonomous operation without any manual adjustment from users. The simulation results demonstrate that the adaptive spike detector successfully locks to a threshold level, which is optimum from a spike-sorting standpoint.

I. INTRODUCTION Implantable electronic devices have emerged as a key

enabling technology for brain-machine interfaces (BMI) and neural prosthetics. In these multi-electrode systems wireless data transmission upward of 100 channels is required, imposing stringent data bandwidth and power dissipation constraints. To minimize potential tissue damage from heat generated by the implantable device, it is important to decrease the power dissipation. In order to reduce the data size, on-chip preprocessing before telemetry circuits becomes a necessary and critical step [1].

Spike detection is an effective technique to reduce the data rate per channel for BMI applications. Spike detection helps in data rate reduction by transmitting only those action potential waveforms that spike above a defined threshold level. These detected waveforms are transmitted to the online spike sorter, which can further decrease the data rate by transmitting only the spike metadata instead of the actual waveform.

A widely used spike detection technique is amplitude threshold crossing [2]. It is simple and has low hardware complexity. A common threshold setting is based on the mean value added to several times (typically 5) the standard deviation. However, the above mentioned fixed-threshold scheme is very sensitive to noise. There are numerous factors that can change the required threshold levels during a neural recording session. Any unpredictable noise sources such as distant neural activity or electrode noise can cause a change in

threshold levels that are needed to correctly detect the spikes. DC offsets, that can commonly arise across different recording electrodes due to electrochemical effects at the electrode-tissue interface, are also an issue. Typical spike detectors often require continuous user input to set the appropriate threshold value. Therefore, there is a need for adaptive adjustment of the threshold to accommodate for the ever-changing background noise levels. The straightforward adaptive approach is to continuously calculate the threshold under the assumption that the noise is stationary and Gaussian [3].

There is a need for a low-cost adaptive approach to adjust the threshold in nonstationary and non-Gaussian background noise. The goal of this work is to dynamically set an optimal threshold level that is high enough to reject the background noise peaks, while still detecting the true spikes from most of the known clusters. The real-time online spike-sorting algorithm serves as a great reference for developing an adaptive threshold spike detection architecture. Online spike sorting enables real-time data analysis and closed-loop parameter setting of the implantable neural system. In contrast, offline spike sorting requires all the spikes to be stored and transmitted before the sorting can take place. This makes immediate feedback difficult.

The purpose of our work is to propose an architecture that is able to perform an adaptive and autonomous spike detection that doesn’t require Gaussian noise assumption. The paper is organized as follows. Section II describes the proposed threshold-lock loop; Section III discusses the closed-loop

Chung-Ching Peng, Pawan Sabharwal, Rizwan Bashirullah Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611

{peng6808, pawansab, rizwan}@tec.ufl.edu

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ThresholdCalculator

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Fig. 1. System block diagram

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simulation and the impact of different parameter settings. Finally, Section IV summarizes the functionality and hardware complexity of the VLSI implementation of the proposed architecture.

II. THRESHOLD-LOCK LOOP The threshold-lock loop (TLL) is an example of a control

system using feedback. The TLL adjusts the detection threshold level by referencing the feedback from the spike sorter. The general scenario for the threshold adjustment is to increase or decrease the threshold value by a unit step based on the feedback signal. This is followed by an idle time where we wait for the effect of the threshold change to take place, and then make further adjustments based on the system response.

A. Initialization The loop begins with the calculation of the initial base

threshold by computing the mean value of the neural signal over a certain time period. Since the spikes occur less frequently than background noise, they don’t change the mean value by too much. The calculated mean value is then added to a small value to set the initial threshold. The detector uses this initial threshold to start detecting spike waveforms and transmitting them onto the spike sorter.

B. Spike Sorting The spike sorter takes the incoming spike waveforms,

performs spike-sorting tasks depending on the underlying architecture. We have previously developed an online spike sorting architecture called “Neural Cache”[4]. In our architecture, the detected spikes from the same neuron form a cluster in the cache, while the noise peaks or overlapped spikes get flushed out of cache frequently. Once the clusters are formed properly, the newly detected spikes can be sorted quickly if they belong to one of the valid clusters.

An alternative approach for adaptive threshold setting can be achieved by feeding back the minimum peak amplitude of spikes from all the active clusters. This requires an extra column of data in the cache memory to keep track of the minimum peak amplitude of each cluster at all time, and thus increases the static power dissipation. In order to minimize the hardware overhead, we simplify the feedback to a 1-bit digital value. Whenever there is a spike detected, the result of the spike sorting (1 for true spike, 0 otherwise) is immediately fed back to the detector.

C. Loop Performance Measurement The loop performance is measured by the percentage of true

spike occurrences in all detected spikes within a windowed time period. Whenever there is a detected spike, the result from the spike sorter is pushed into a first-in-first-out (FIFO) register bank. The threshold in computed once the FIFO is completely filled up. The number of true spike occurrences reflects the

ability of spike detector to reject the noise peaks. Fewer detected noise peaks result in better spike sorting accuracy [4]. D. Threshold Adjustment Algorithm

The proposed algorithm is a self-learning and adaptive approach. A Finite State Machine (FSM) oversees the execution of the algorithm. The FSM continuously keeps track of the performance changes and adjusts the threshold levels accordingly. It increments or decrements the threshold value by a unit step size depending on i) the impact on performance that the previous threshold adjustment had, and ii) the direction (up or down) in which threshold was adjusted. The detailed algorithm is listed in Table 1.

Besides the fundamental algorithms, there are several rules dedicated to the special events, such as sudden performance drop and some corner cases. If the performance drop is larger than a predefined value, or a valid neuron cluster in the Neural Cache gets deleted, the FSM initializes the TLL and triggers the base threshold re-calculation. This allows the incoming spikes that have peak amplitude lower than the threshold to form clusters. If the performance is 100% (all true spikes) or it stays unchanged, the threshold will decrease one unit step as a precaution against unrealistic high threshold.

E. Steady State The threshold adjustment stops when the improvement in the

noise spike reduction is trivial. This can be interpreted as the current threshold having reached an optimal balance point that is sufficient to filter out most of the undesired noise spikes.

III. CLOSED-LOOP ANALYSIS

A. Synthesized Noisy Spike Train Noisy spike train data representative of two simultaneously

firing neurons having different spike shapes is generated by the program [5]. For each value of SNR (0.5, 1, 2 and 4), 10 such data sets are generated. Therefore a total of 40 noisy spike train data sets are generated for the simulation. Each data set is sampled at 25kHz for 100 seconds. All the ground truths (known spike times) are stored for later performance evaluation. B. Simulation Setup

The Matlab simulation setup is illustrated in the Fig 2. To better evaluate the closed-loop performance , we developed an

Performance Change (Present v.s Previous)

Previous Adjustment

New Adjustment

Improve + 1 step + 1 step Improve - 1 step - 1 step Degrade + 1 step - 1 step Degrade - 1 step + 1 step

Table. 1. Threshold Adjustment Algorithm

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ideal spike-sorting model, such that the detected spike is immediately sorted based on the known ground truth. To begin with, the noisy spike train is supplied to the spike detector. Subsequently the detected spike waveforms are sent to spike sorter. The spike sorter sorts the spikes immediately by referencing the ground truths, feeding the results back to the spike detector. The loop performance (percentage of true spikes occurrence) is evaluated at the spike detector by recording the performance and changes in the threshold values every history-window length (32 detected spike occurrences). The unit step size for threshold adjustment is 1/256, assuming the 8-bits binary fixed-point representation.

C. Simulation Results Fig.3 illustrates the relationship between performance and

threshold step response during the start-up period. The results show that for both cases (SNR 0.5 and 2), the performance improves as the threshold value gradually increases. Note that in Fig. 3(a), the lower SNR (0.5) results in larger noise amplitudes; hence it requires higher threshold and longer settling time for the threshold to reach the steady state. In Fig. 3(b), the steady state is reached when the performance variation is significantly smaller. Table 2 summarizes the average response time and steady-state threshold for all the 40 data sets.

Fig. 4 demonstrates the impact on performance and threshold for sudden changes in SNR. The sample neural data set is synthesized by concatenating 3 different neural data sets with SNR of 4, 0.5, and 4 respectively. The SNR drop causes a sharp performance degradation, triggering the threshold re-calculation to compensate for the change in noise level. D. Parameter Settings

The performance of the Threshold lock loop depends on many parameters. The three most important parameters are unit step size, history window size and the performance drop value that triggers base threshold recalculation. We have extensively tested different parameter settings for these three parameters. The tradeoffs between the choices of values for these three parameters are as follows:

1)Unit step size: A smaller unit step size results in better threshold resolution, at the expense of longer settling time.

2)History window size: A larger window size reduces the FSM activity but at the expense of more hardware overhead. A smaller window size causes more fluctuation of performance changes, thus triggering more threshold adjustments.

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Fig 3. Performance/threshold changes using neural data sets with different SNR (a) SNR=0.5 (b) SNR=2.

Neural data set SNR

# of 32 spike window to reach steady state

Steady state threshold

0.5 93.8 0.0740 1 49.1 0.0655 2 17.2 0.0577 4 9.6 0.0450

Table. 2. Response time and steady-state threshold

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Fig 4. Performance/threshold changes with sudden SNR drop.

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3)Base threshold re-calculation: A smaller value for the performance drop that triggers the base threshold recalculation results in more dynamic power consumption by the arithmetic hardware. However, the recalculation of base threshold is necessary as it helps decrease the learning time during the periods when the SNR changes suddenly.

IV. VLSI IMPLEMENTATION

A. Hardware Architecture The adaptive spike detector architecture is shown in Fig. 5.

The functions of each block are described below, 1) Spike FIFO: The spike detection is performed by

comparing the amplitude of the 38th sample in FIFO with the threshold. If the amplitude crosses the threshold, a 64-cycle wide pulse will be generated by the pulse generator. During this pulse period the whole spike waveform will be received by the spike sorter. At other times the spike sorter simply ignores the incoming samples.

2) Finite State Machine: The total number of 1’s in the history FIFO is treated as a indicator of the ability of spike detector to reject noise. The FSM counts the number of ‘1’s in history FIFO and executes the adaptive algorithm (described earlier) which generates a new threshold value. When the threshold recalculation is triggered, the FSM generates a 6-cycle wide pulse to enable the adder tree to complete the addition of 64 samples from spike FIFO in parallel.

3) Power-Gated Adder Tree: The adder tree takes the 64 samples in FIFO and performs the addition operation. The result is then right-shifted by 6 bits to perform the divide by 64 operation. The adder tree is turned off during the stationary period, when there is no need to recalculate the threshold. The on/off power gating is controlled by the FSM with previously generated 6 cycle wide enable pulse.

4) History FIFO: The History FIFO stores 32 1-bit feedback samples. It is enabled whenever a newly sorted result is fed back from the spike sorter. B. VLSI Implementation

The RTL code for the spike detector has been developed and

simulated in Cadence NCSim. The functionality was verified using actual neural data sets as the input to the spike detector.

The VLSI implementation is a mix of synthesized and fully custom digital blocks. The FSM is synthesized using Synopsys Design Compiler with UMC 0.13um CMOS low-power standard cell library, which is characterized using a supply voltage of 0.4V. The two FIFOs and adder tree are custom designed and simulated using Cadence tools. The power is measured at a clock frequency of 20kHz. The area is estimated to a reasonable degree of accuracy by using actual gate layouts from the standard cell library. The details are reported in Table. 3. Most of the area is occupied by the spike FIFO, which is also needed by the online spike sorter. The power overhead of adaptive threshold computational engine depends primarily on the power consumption of the adder tree. The adder tree is mostly power gated and is powered only when threshold recomputation is required. Since threshold recomputation is not a frequent occuring event, the power overhead of the adaptive scheme is negligible.

V. CONCLUSION A technique using threshold locking has been described to

enable adaptive and autonomous threshold calculation without manual intervention. It has non-Gaussian noise rejection capability and requires only minimal hardware overhead. This technique enables dynamic evaluation of the optimal threshold value, which results in better spike sorting accuracy.

REFERENCES [1] M. S. Lewicki, “A review of methods for spike sorting: the detection and

classification of neural action potentials.” Network: Comp. Neural Syst.9(4)53-78, 1998.

[2] I. Obeid, P. D. Wolf. “Evaluation of spike-detection algorithms for a brain-machine interface application,” in IEEE Transactions on Biomedical Engineering, Vol. 51, No. 6, June 2004.

[3] R. R. Harrison, “A low-power intergrated circuit for adaptive detection of action potentials in noisy signals,” in Proc. 25th Ann. Int. Conf. IEEE EMBS, pp. 3325-3328, September, 2003.

[4] C.-C. Peng, P. Sabharwal, and R. Bashirullah, “Neural Cache: A low-power online digital spike-sorting architecture,” in Proc. 30th Ann. Int. Conf. IEEE EMBS, Aug. 2008.

[5] L. S. Smith, “Testing spike detection and sorting algorithms using synthesized noisy spike trains”, Neuro-IT workshop on Interoperability of Simulators, Edinburgh, United Kingdom, 2006.

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Fig 5. Adaptive spike detector block diagram

Functional Blocks Power (uW) Area (mm^2)

Spike FIFO 0.440 0.1900 History FIFO 0.026 0.0012

FSM (w/ pulse generator) 0.087 0.0083 Adder Tree 0.838 0.1769

Total 1.391 0.3764 Table. 3. Summary of power and area.

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