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Technique to Improve Visibility for Cycle
Time Improvement in Semiconductor
Manufacturing
Syahril Ridzuan Ab Rahim, Ibrahim Ahmad & *Mohd Azizi Chik Department of Electronics & Communication,
Universiti Tenaga Nasional (UNITEN),
43000 Kajang, Selangor, Malaysia.
*Silterra Malaysia Sdn. Bhd
Lot 8, Phase 2, Kulim Hi-Tech Park,
0900 Kulim, Kedah, Malaysia.
Email: [email protected], [email protected].
Abstract – Cycle time for a product is one of the key
performance indicators in semiconductor manufacturing.
Reduction of cycle time will shorten product time to market,
increase throughput, reduce operational cost and develop
customer trust. Semiconductor manufacturing that process 40,000
to 50,000 work-in-progresses (WIP), usually takes 50 to 70 days,
300 to 400 equipments and 300 to 900 steps to complete. Thus, any
task related to manual data collection to make indices reports or
analysis usually needs high resources requirements to spend for
manual work and risk for mistake. In the modern facility of
semiconductor fabrication, a system like Manufacturing
Execution Systems (MES) was implemented to ease the process
and operation traceability. The information is well kept in the
appropriate databases. Many applications then are integrated
with MES database to perform indices reports. In this paper, the
improve method for data collection related to cycle time
improvement is introduced. In this approach, the automated
systems was developed using existing Advance Productivity
Family (APF) programming platform to collecting the data. The
system is integrated between MES and APF to have the real time
data collection and analysis. In the systems, manual data
collection is replaced with respective automated data transfer
from real situation in the manufacturing environment. This
program then able to shows real root caused with proper
relational charting to display real problem for engineering to
prioritize and resolve respectively. As a result, 39% reduction of
cycle time gained by implementing this technique. The system has
successfully implemented and supports the cycle time reduction.
Index Terms—Advance Productivity Family (APF), Work In
progress (WIP), Manufacturing Execution Systems (MES).
I. INTRODUCTION
Today demand to produce product with competitive cycle
time is one for the key factors for business decision [1]. Many
approaches for cycle time improvement have been published.
Most of the papers are discussed cycle time improvement
through improving throughput of the equipments [1]. In order
to improve cycle time in semiconductor manufacturing, more
detail data to plot trend and relational between issues are
needed [2]. Key factors that influence cycle time are WIP
quantity and its mixed, bottlenecks equipment availability and
throughput, rework rates, others key equipments availability,
setups and dispatching rules[1]-[3]. Normally high cycle time
(CT) is contributed due to unnecessary waiting time,
unscheduled downtime, not effective dispatching rule, rework
and hold due to related engineering requirements [7]. In this
analysis, more focus will be addressed to improve waiting time
and hold time. Waiting time is when the WIP is idle. Hold time
is when the product is not allow to process next step, mainly
reserve for engineering activities to data validation, wait for
recipe setup, wait for merge with other wafer and customer
input. Most cases when product release from hold, it will
require go to inspection step. Further in this paper will discuss
technique and works that have done to reveal issue, causes and
potential solution to improve cycle time visible to the
operational team.
II. SYSTEMS ARCHITECTURE
SilTerra have existing MES systems that currently tracked the
information for products. Its MES systems have been designed
for easy integration with respective application for detail data
collection. This research takes the advantages and utilizing its
existing systems architecture to establish new computer
program for cycle time improvement exploration. In this
approach, few databases have been setup, and coding to collect
related cycle time caused is established.
Fig.1 shows system architecture and explanation of how
technique to improve visibility for cycle time improvement is
implemented.
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IEEE-ICSE2012 Proc., 2012, Kuala Lumpur, Malaysia
978-1-4673-2396-3/12/$31.00 ©2012 IEEE
Fig. 1. System Architecture
A. Queue Time Database
This database stores all information regarding product
information starting from first process steps until completed
process step. All of the information was extracted from the
MES database. Below is the list of information grabbed from
this database;
TABLE I.
EXAMPLE QUEUE TIME DATABASE INFORMATION
Information Description Information Description LotID LotID Identical name for every lot’s (Code
group of products)
StepName Name of the processing step’s
TrackIn Time Date and time of product going to the process step’s.
TrackOut Time Date and time of product completed process
step’s.
Last TrackOut
Time
Previous completed step’s TrackOut
Time
Equipment ID Equipment Identification
B. SRS Database
SRS database contains many information regards WIP.
However, in this approach only selected data regards caused of
high cycle time is needed to extract from SilTerra Reporting
Systems (SRS) database. This techniques help to provide fast
data transfer for automated data compilation.
TABLE II.
EXAMPLE SRS DATABASE INFORMATION
Information Description Information Description
Memo Reason of high Cycle Time
Resources Name a group of equipment
Date Date of Activity
Uptime Percent of Equipment avaibility
Utilization Percent of utilizing the equipment
C. Advance Productivity Family (APF)
APF is needed as platform to code a program to calculate
cycle time and consolidate various database sources to
understand cause of high cycle time [5]. This is where
automated data compilation replaced manual data collection in
MES installed Semiconductor Manufacturing. Please refer to
Fig. 1 for details. The code can be schedule automatically using
one of the APF function to collect and to perform data snapshot
at the respective time. The code is written to perform
automated data integration and filtration for proper caused of
high cycle time and search for responsible person that holding
the responsibility of current issue. The information generated
in this coding then integrated with Historical Compiled
database.
D. Historical Compiled Data Database
Previous results from APF coding are stored in this database.
An additional coding in APF then used this database to make
an automated follow up with respective person that responsible
for the action required. The automated follow up will end
automatically when the issue resolved.
E. Alert and Notification
The alert and notification application is coded from APF
platform. This is where an automated notification and
escalation is made to respective responsible person and to its
supervisor. The notification is done through automated reports
update and email.
III. DATA ANALYSIS
In this paper, the scope for data analysis is started with
capturing WIP waiting time at the respective limit. The
information is gathered automatically from MES systems.
Furthermore, coding that developed in APF will filter and
capture respecting waiting time WIP. In the process, more data
association and indexing with information like equipment,
person that responsible for high waiting time, processing steps,
module or area, and time stamp for the activities. Further
explain in the fig 2. Finally the results from this analysis then
publish to the respective personal for further action taken.
Fig. 2. Analyzing Method Process Flow Diagram
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IEEE-ICSE2012 Proc., 2012, Kuala Lumpur, Malaysia
The definition of criticality of the equipment or steps related to
cycle time is define to formula of waiting time x quantity that
actually impacted. The formula is call impact factors and it’s
summarized in the equation 1 [4].
The highest impact is important and will sorted first. As an
example the highest waiting time from the chart below is at
Etch (ETH) area and followed by cleaning (CLN) area.
Resources are defined as a group of equipments that capable to
process several types of steps. Front End (FE) resources are
defined as resources that process to make transistors, capacitor
and insulator. The processes begin with step “Oxidation
Cleaning” until “Inter Layer Dielectric Planarization
Annealing”. While back end (BE) resources are define as
resources that process to make metal connector. The processes
continue with step “Lithography Contact Inspection” until
“Outgoing Quality Assurance Packaging Inspection”. Analysis
is only choosed either front end or back end resources of the
respective area based on the highest impact factor. As an
example, fig. 4 below shows that the highest waiting time by
resources for backend etching area is at Damascene Trench
Etching and followed by Damascene Via-Etching.
Fig. 4. To Date Waiting Time by Resources FE or BE
Every resource is process identical steps. At the same time,
every product has a recorded actual processing time at
particular steps. From the top two highest waiting times by
resources from the previous analysis, drilldown analysis is
performed to know the problem steps and grabbed the date of
bad situation. As an example, highest waiting time by steps for
resources Damascene Trench Etching is at step Re-distribution
Etching Layer and Damascene with Bi-layer Resist as in fig. 5
below .
Fig. 5. Monthly Waiting time By Steps
Every day manufacturing engineers recorded their line
problems in the SRS database through “SRS application”. The
problems date can be match with SRS data to find out the root
cause of the problems based on the date and resources. For an
example, the highest impact factor waiting time by resources is
at Damascene Via-Etching is occur on day “2X” due to lack of
avaibility at that resources.
Fig. 6. Damascene Trench Etching Daily WIP,
ActualProcessQty, Utilization and Avaibility
Finally, the result from the analysis is summarized and
compile in the one PDF format as documentation. The
sequence of the result arrangement is as in fig. 7 below. Result
from the analysis arranged in sequence for solid explanation of
the root cause that contribute to high waiting time at certain
resource and date.
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IEEE-ICSE2012 Proc., 2012, Kuala Lumpur, Malaysia
Fig. 7. Sequence of Result Documentation
Analysis result sent out to the respective personal for further
action taken immediately. As an example, auto mail is sending
the result of the analysis directly to manufacturing, engineering
and management team for action taken to solve the problem
that occur at Copper-Dual Damascene Trench Etching
resources.
IV. RESULT AND EMPIRICAL IMPLEMENTATION
This system was integrating with the production line and shows
some improvement in the cycle time as presented in the fig. 7
below. There is an improvement about 39 % since year 2011.
Fig. 8. Percentage of Cycle Time Improvement
V. CONCLUSION
As a conclusion, manual analysis and data collection
difficulties was eliminated by using this automated technique.
This technique will help to improve the visibility for cycle time
improvement in semiconductor manufacturing by identifying
the causes of this problem. Manufacturing, Engineering and
Management personal easily gets the information of the
production problem by reading the real time report from this
system.
REFERENCES
[1] Kader Ibrahim, Mohd Azizi Chik and Uda Hashim, “Variability Due to
Tool Configurations That Impacts Overall Capacity in Wafer
Fabrication Facility,” 11th Asia Pacific Industrial Engineering & Management Systems Conference, 2010.
[2] Yair Meidan, Boaz Lerner, Gad Rabinowitz, and Michael Hassoun,
“Cycle-Time Key Factor Identification and Prediction in Semiconductor Manufacturing Using Machine Learning and Data Mining” , IEEE
Trans. Semicond. Manuf., vol. 24, no. 2, May 2011.
[3] Ingy A. El-Khouly, Khaled S. El-Kilany, and Aziz E.- Sayed, “Effective
Scheduling of Semiconductor Manufacturing”, World Academy of
Science, Engineering and Technology, vol. 79, 2011.
[4] Chung-Jen Kuo, Chen-Fu Chien, Jan-Daw Chen, and Member, “Manufacturing Intelligence to Exploit the Value of Production and
Tool Data to Reduce Cycle Time”, IEEE Trans. Actions On
Automations Science And Eng., vol. 8, no. 1, January 2011. [5] Mohd Azizi Chik, Yeo Eng Teck, Mahalil Amin Abd Malek, and Mohd
Hafidz Saidi, “Comprehensive Sequencing Dispatching Method for
Identified Bottleneck Tool – Photolithography Process”, NSM, Perlis, Malaysia, pp.19-21. 2003.
[6] Kader Ibrahim, Mohd Azizi Chik, Wan Shamsir Nizam, Nyioh Li Fern,
and Nor Farahidah Za’bah, “Efficient lot Batching Systems for Furnace Operation”, ASMC 14th Conference, Munich, Germany, pp. 322-324,
2003. [7] Mohd Azizi Chik, Mohd Hazmuni bin Saidin, and Uda bin Hashim,
“Industrial Engineering Roles in Semiconductor Fabrication”, APIEM
11th Conference, December 2010.
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