Evaluation of an FPGA-based Reconfigurable SoCfor All-Digital Flexible RF Transmitters

Nelson V. Silva, Manuel Ventura, Arnaldo S. R. Oliveira and Nuno Borges Carvalho

Departamento de Electronica, Telecomunicacoes e Informatica, Instituto de Telecomunicacoes,

Universidade de Aveiro, Aveiro 3810-193, Portugal

Abstract—In this paper an FPGA-based System-on-Chip (SoC)implementation of a flexible digital radio is presented andevaluated. The implemented transmitter is able to perform adirect up-conversion of a baseband signal to RF operatingin the gigahertz frequency range as well as it enables thesimultaneous transmission of two different carriers, each onehaving a different modulation, bandwidth, etc. The developedarchitecture is fully integrated into a single FPGA device andallows software programmability by including an embeddedmicroprocessor for control operations. The high flexibility ofthis architecture allows to easily change the frequency of thecarriers as also the spectral masks, making it interesting in thescope of white spaces exploration and for software radio-basedapplications.

Keywords-All-Digital Transmitters, Delta-Sigma Modulation,Field-Programmable Gate Array (FPGA).

I. INTRODUCTION

Over the last years there has been an exponential growth

of the communication needs with increasing mobility and

autonomy requirements. Moreover, recent changes in the spec-

trum management policies provide the exploration of white

spaces [1] in the RF spectrum (mainly on unused TV bands),

thus pushing an additional research effort towards the devel-

opment of new opportunistic and smart radios [2], capable to

adapt to different communication scenarios. In this sense, the

well-known Software-Defined Radio (SDR) concept [3] holds

the potential for implementing the supreme universal radio,

that is, a reconfigurable wireless radio that can change its

communication parameters in order to meet the user demands

as well as the channel and the network conditions.

However, one of the main challenges for achieving such a

new deployment involves the development of a very flexible

physical layer in order to support the transmission of multi-

band, multi-rate and multi-standard signals, which in practice

is very hard to implement using conventional approaches.

On the other hand, the last advances in this field include

the development of novel all-digital transmitters where its

datapath is digital from the baseband up to the RF stage. Such

concept has inherent high flexibility and poses an important

step towards the development of SDR transmitters. Moreover,

the architecture of this new transmitter can be implemented

using Field-Programmable Gate Array (FPGA) devices, which

provides additional flexibility as well as field upgradeability

and shorter time-to-market.

In fact, current FPGAs have an equivalent logic capacity of

millions of logic gates in addition to the large RAM blocks,

DSP modules and multigigabit I/O standards. If efficiently ex-

plored, these resources can be used to enable the development

of agile all-digital transmitters.

Conventional transmitters perform the RF up-conversion

stage by multiplying the desired signal by a sinusoidal carrier

(e.g. the homodyne transmitter). However, since the FPGA’s

internal logic typically operates at hundreds of megahertz (e.g.

up to 400 or even 500 MHz if good design practices were

used), performing the RF up-conversion inside the FPGA using

a conventional approach will only allow to generate low RF

frequencies (up to dozens or a few hundreds of megahertz),

and therefore resulting in a very limited RF transmitter.

On the other hand, all-digital transmitter architectures usu-

ally include a first stage where the input information is

typically converted into a 2-level representation using either

ΣΔ modulation or Pulse Width Modulation (PWM). This

data conversion to 1-bit eases the RF up-conversion stage

and if conveniently explored allow the use of a single FPGA-

embedded multigigabit (MGT) serializer to output the desired

RF signal. This way, given the very high speed of current

MGT serializers (e.g. up to 28 Gbps in Altera and Xilinx

high-end FPGAs), it becomes possible to have a digital RF

output signal centered in the GHz frequency range as well as

it allows integrating the entire design into a single FPGA.

In this paper we explore the potential allowed by current

FPGA technology by presenting and evaluating an FPGA-

based SoC all-digital transmitter architecture that is able to

simultaneously transmit two independent carriers (i.e. mul-

tichannel transmission) and where the RF output operating

in the gigahertz frequency range is generated inside a single

FPGA device.

The remainder of this paper is organized as follows. Sec-

tion II presents the related work. Section III introduces the

all-digital transmitter architectures. Section IV details the

architecture of the reconfigurable transmitter. The experimen-

tal results are reported in Section V and the conclusion is

presented in Section VI.

II. RELATED WORK

In [4] the authors present a digital transmitter where data

is shaped using Pulse Width Modulation (PWM) and up-

converted to RF using a digital mixer. In [5], [6] the authors

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present a new transmitter approach using Low-Pass (LP) ΣΔmodulators and digital multiplexers to design an all-digital

multimode RF transmitter. In this approach, ΣΔ modulation is

used to shape signals centered at baseband, which significantly

alleviates the processing speed requirements, and therefore

simplifies the design of ΣΔ-based transmitters for operation

in the gigahertz frequency range. In [7] the authors present a

low-pass ΣΔ-based transmitter front-end also using external

multiplexers for implementing the digital up-conversion to RF.

A SDR transceiver including IF up-conversion, a band-pass

ΣΔ modulator and RF up-conversion is presented in [8]. In [9]

it is presented an all-digital transmitter with multiple stop-

bands in the ΣΔ Noise Transfer Function (NTF) in order to

create a concurrent dual-band transmitter.

However, current state-of-the-art digital transmitter archi-

tectures are still restrictive for developing a truly SDR-based

system as well as for white spaces exploration. In fact, almost

all the above presented transmitters require very high-quality

filters to remove out-of-band noise, others only generate low

RF frequencies [4], [10], many require expensive external

multiplexers for implementing the RF up-conversion [5]–[7]

or have carriers with low Signal-to-Noise Ratio (SNR) [7].

In this paper we addresses some of these limitations and ex-

tend previous work [11], [12], by presenting and evaluating an

FPGA-based multichannel multistandard all-digital transmitter

architecture that reduces the need of using high quality filters

and where the RF output carriers operating in the gigahertz

frequency range are generated inside a single FPGA device.

Moreover, the high flexibility of this reconfigurable transmitter

makes possible to easily modify important parameters such

as the carriers’ frequencies, the usable bandwidth and the

dynamic range.

III. ALL-DIGITAL TRANSMITTERS BASICS

The underlying concepts of all-digital transmitters are pre-

sented in this section. As previously stated, the datapath

of these transmitters is entirely digital up to the RF stage,

which provides high flexibility, specially if implemented using

reconfigurable hardware, and poses an important step towards

the development of SDR transmitters.

2fc

��

fs

baseband RF

DSP(I/Q)

MUXvi

vq

ui

uq

PA

MUX��

fc

Modulation Up-conversion

MUX

n

n

1

1

1

0

0

1

1

0

Fig. 1. Architecture of an all-digital transmitter.

The ΣΔ-based transmitter illustrated in Fig. 1 receives

the baseband in-phase (ui) and quadrature (uq) components

Sf2Sf

2Sf�Sf� 0

Signal�� noise

f

Fig. 2. Frequency response of a low-pass ΣΔ modulator illustrating thesignal (solid line) and the ΣΔ noise shaping (dot-dashed).

vi

vq

fc

2fc

vq * fc

RFout

vi * fc

MUX

MUX

MUX

1

2

3

4

5

6

7

1

2

3

4

5

6

5

67

1

0

1

0

1

0

Fig. 3. Timing diagram illustrating the RF up-conversion process.

of the desired signal to be transmitted. These components

are then shaped using ΣΔ modulation in order to make

them suitable for the RF up-conversion process. In the ΣΔmodulation stage the signal information is preserved but out-

of-band noise is added as a consequence of converting a n-bit

signal representation into a 1-bit output signal, see Fig. 2.

After the ΣΔ modulation stage, a set of three digital

multiplexers are used to modulate the 1-bit baseband sig-

nals by a square wave carrier. Similarly to a conventional

homodyne transmitter, this approach shifts a baseband signal

directly to RF, that is, without passing through an Intermediate

Frequency (IF) stage. However, since a square wave is used,

odd harmonics of the carrier frequency will also be generated.

In this architecture, the leftmost multiplexers shown in

Fig. 1 center the signals at the carrier frequency while the third

multiplexer enables the transmission of both components by

time interleaving them with a 90 degree phase shift. The timing

diagram detailing the RF up-conversion process is illustrated

in Fig. 3 and the RF spectrum of the ΣΔ-based transmitter

after the digital up-conversion is shown in Fig. 4.

cf0 fcf� Sf2Sf2�

�� noise

Signal

Fig. 4. Signal (solid line) and noise shaping (dashed) of a low-pass ΣΔmodulator after RF up-conversion to fc.

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IV. FPGA-EMBEDDED RF TRANSMITTER ARCHITECTURE

In this section, we present an FPGA-based System-on-

Chip (SoC) architecture containing a multichannel all-digital

transmitter operating in the gigahertz frequency range.

This architecture enables the simultaneous transmission of

two different RF carriers, each one having a different stan-

dard, frequency, modulation and spectral mask in an FPGA-

integrated solution where the digital up-conversion to the

gigahertz frequency uses a single MGT transceiver.

A. ΣΔ Modulator Design

The second-order low-pass ΣΔ-modulator used in this paper

is a Cascade-of-Integrator with distributed FeedBack (CIFB)

type [13], as illustrated in Fig. 5 by its general representation in

the z-domain. The CIFB structure was chosen due to its good

stability when used in a low-pass configuration and because

its short critical path allows a higher sampling rate. This is of

critical importance since higher sampling rates allow to move

away the quantization noise from the desired signal which

permits in one hand having wider band signals and in another

hand reducing the quality factor of the reconstruction filter.

The ΣΔ coefficients were precomputed using the ΣΔ-

toolbox [14], for a sampling rate of fs = 250 MHz and with

a bandpass of 20 MHz, resulting in an effective oversampling

ratio (OSR) of 12.5. Moreover, in order to guarantee stability,

the Lee-criteria was set to ‖NTF(ω)‖∞ < 2.

These coefficients were then recomputed using a conver-

gence process where all coefficients are rounded to powers

of two or if not suitable to a two’s-complement binary rep-

resentation using up to eight bits. This way, the critical path

can be further reduced since powers of two coefficients can

be implemented using logical shifts.

The resulting type-2 Chebyshev highpass Noise-Transfer

Function (NTF) was then calculated to be:

-

11�Z 1

1�Z

v(n)

u(n)b1

c1 c2

g1

- -

a1 a2

Fig. 5. Structure of the implemented second-order CIFB ΣΔ modulator.

Fig. 6. Zero-pole z-plane and frequency response of the designed second-order CIFB ΣΔ modulator.

Fig. 7. Example spectrum of a ΣΔ modulator output for a 3.5 MHz basebandinput signal.

NTF(z) =z2 − 2z + 1.039

z2 − 0.875z + 0.315. (1)

The corresponding zero-pole z-plane and the frequency

response of the designed ΣΔ modulator are shown in Fig. 6.

As illustrated in Fig. 7, the simulated dynamic range is

≈ 40 dBc within the 20 MHz RF bandpass when used with

a 3.5 MHz bandlimited signal with 5.4 dB Peak-to-Average

Power Ratio (PAPR).

Concerning the ΣΔ datapath implementation, the chosen

topology and the optimized coefficients combined with specific

design goals and strategies made possible to implement the

ΣΔ-modulator at frequencies exceeding the 250 MHz in the

current FPGA logic fabric. The implemented ΣΔ modulator

illustrating the full datapath and the chosen coefficients is

detailed in Fig. 8.

B. Digital Up-Conversion

A block diagram of the implemented multichannel trans-

mitter architecture is shown in Fig. 9. In this architecture, the

main blocks for implementing the digital up-conversion stage

are the interconnection network and a MGT serializer. The

interconnection network block combines the outputs of the

ΣΔ modulators (vi and vq) with its inverted versions (vi and

vq), in order to generate the parallel output word (w).

The first step to generate w in a single channel scenario con-

sists of constructing a vector containing the four components

of the desired signal (vivqvivq), and then replicating it by the

digital up-conversion factor N , given by fc/fs. The serialization

of this vector at a bitrate of 4× fc will generate a digital RF

carrier centered at fc.

In a multichannel transmission scenario this procedure must

be done for each carrier. Nevertheless, since a distinct fcis desired for each channel, applying the above described

procedure will result in a different output bitrate for each

channel. Since the multichannel transmission followed in this

approach requires all channels operating at the same rate, the

Least Common Multiple (LCM) of all output bitstreams is

computed and each pre-constructed vector is extended so that

its waveform is maintained for the new bitrate given by the

LCM. At last, the multichannel transmission is carried out by

508885892

0.0125

v(n)

MUX0.28125

-0.28125

1�Z

MUX0.3203125

-0.3203125

1�Zu(n)

-

-

-

0.25 0.3125 4.00

11 11 12

13

12 11 5

8 6

10

Fig. 8. z-domain representation of the implemented CIFB second-order ΣΔ modulator.

time interleaving the vectors of each carrier. The allowable

output frequencies for each carrier are given by: fc1 = N1× fsand fc2 = N2 × fs where N1 and N2 ∈ N. Further details

regarding the interconnection network can be found in [11].

Finally, the FPGA-embedded serializer must produce an

output bitrate that is eight times the LCM of the desired carrier

frequencies in order to ensure the proper functioning. Since

the used serializer operates in both clock edges, it should be

clocked at a frequency fo that is half the output bitrate.

After the up-conversion stage, it is enough having an RF

front-end containing a switching-mode Power Amplifier (PA)

and a reconstruction filter for producing an RF signal that is

suitable to be transmitted by the antenna.

C. PHY Control Processor

The PHY control processor block includes a microcontroller

with a Reduced Instruction Set Computer (RISC) architecture

for software programmability with low hardware overhead,

interconnected to a dynamically Reconfigurable Digital Clock

Manager (RDCM) and to Input/Output interfaces for enabling

communication with external devices. This way, it is possible

through software to change the interconnection network in

order to select the desired input signals and up-conversion

factors, as well as to configure the RDCM in order to generate

the proper clock signals for obtaining the desired RF output.

Regarding the software programming model, the inter-

connection network and the RDCM have memory mapped

registers. This way, by modifying those registers it is possible

u1i

u1q

Serializer

fo

RF Front-End

Interconnection Netwokv1i

��

v1q��

u2i

u2q

v2i��

v2q��

I1

Q1

Ik

Qk

PA

v1i

v1q

v2i

v2q

FPGA SoC

w1w2

w64

RDCM

fs

I/O μController

PHY Control Processor

DSP

Fig. 9. Block diagram detailing the implemented FPGA SoC transmitter.

Fig. 10. Setup of the evaluated FPGA-based all-digital transmitter.

to alternate between different configurations of the intercon-

nection network as well as to tell the RDCM to synthesize new

frequencies for the ΣΔ-modulators and for the MGT serializer.

V. EXPERIMENTAL RESULTS

This section firstly presents the experimental results regard-

ing single channel data transmission and then the measured re-

sults regarding multichannel data transmission are also shown.

The FPGA-SoC depicted in Fig. 9 was prototyped in an

ML628 development board containing a Virtex-6 HX380T

FPGA. The measured results were obtained using a Vector

Spectrum Analyzer (VSA), model Rohde & Schwarz FSQ8,

directly connected to the development board, see Fig. 10.

All baseband signals used for evaluating this transmitter were

stored inside the FPGA’s internal memory.

A. Single Channel Data Transmission

In the first implementation experiment the RF transmitter

architecture was configured to transmit a 64-QAM signal

centered at 3.125 GHz, see Fig. 11. For this implementation

example, the up-conversion factor was set to N = 16. This

way the ΣΔ modulators were configured to operate at a clock

frequency of 195.3125 MHz. The pattern building block was

configured to generate the following 64-bit output word:

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w = [v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i

v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i

v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i

v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i v1q v1i

v1q],

where v1i and v1q are the in-phase and the quadrature compo-

nents of the 64-QAM baseband signal after the ΣΔ modulation

stage and v1i and v1q are its inverted versions.

The serializer was configured in order to produce an output

bitstream of 12.5 Gbps. This output signal was then connected

to a VSA for spectral and vector analysis. As can be seen in

Fig. 11, the high operating frequency of the ΣΔ modulators

allow a Signal-to-Noise and Distortion Ratio (SNDR) of

≈35 dB and a usable bandwidth of ≈15 MHz.

Next, the FPGA-SoC transmitter architecture was config-

ured in order to transmit the OFDM modulation of a WiMAX

baseband signal centered at the same 3.125 GHz. For this

new configuration, it is enough to change the interconnection

network for generating the following word:

w = [v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i

v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i

v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i

v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i v2q v2i

v2q].

The RF spectrum of the FPGA-based transmitter contain-

ing a WiMAX signal is illustrated in Fig. 12. The usable

Ref -1 dBm

Center 3.125 GHz Span 20 MHz2 MHz/

RBW 100 kHzVBW 1 kHz

-70

-60

-50

-40

-30

-20

Fig. 11. Output spectrum of the transmitter architecture when sending a64-QAM signal.

Ref -1 dBm

Center 3.125 GHz Span 20 MHz2 MHz/

RBW 100 kHzVBW 1 kHz

-70

-60

-50

-40

-30

Fig. 12. Output spectrum of the transmitter architecture when sending aWiMAX signal.

bandwidth of ≈15 MHz is equal to the first implementation

since the ΣΔ modulators are operating at the same frequency

and have the same coefficients. On the other hand, the used

samples containing the WiMAX baseband signal have lower

energy than the 64-QAM signal, which explains the lower

SNDR of ≈32 dB.

B. Multichannel Data Transmission

The architecture was now configured to implement the

simultaneous transmission of two different carriers, one cen-

tered at 1.5625 GHz containing a 64-QAM signal and the

second one centered at 781.25 MHz and containing a WiMAX

signal. All ΣΔ modulators were configured to operate at

195.3125 MHz. The interconnection network was configured

to generate the following 64-bit output word:

wo = [v1i v2i v1q v2i v1i v2q v1q v2q v1i v2i v1q v2i v1i v2q v1q

v2q v1i v2i v1q v2i v1i v2q v1q v2q v1i v2i v1q v2i v1i v2q v1q

v2q. v1i v2i v1q v2i v1i v2q v1q v2q v1i v2i v1q v2i v1i v2q v1q

v2q v1i v2i v1q v2i v1i v2q v1q v2q v1i v2i v1q v2i v1i v2q v1q

v2q].

Again, the MGT serializer was set to produce an out-

put bitstream of 12.5 Gbps. The obtained spectrum of the

multichannel architecture when simultaneously transmitting a

WiMAX signal centered at 781.25 MHz and a 64-QAM signal

centered at 1.5625 GHz is shown in Fig. 13. A closer view of

the 64-QAM signal can be found in Fig. 14.

Ref -1 dBm

Center 1.171875 GHz Span 1.18 GHz118 MHz/

RBW 500 kHzVBW 10 kHz

-70

-60

-50

-40

-30

-20

Fig. 13. Measured multichannel spectrum of the proposed transmitter.

Ref -1 dBm

Center 1.5625 GHz Span 20 MHz2 MHz/

RBW 100 kHzVBW 1 kHz

-70

-60

-50

-40

-30

Fig. 14. Measured spectrum of a 64-QAM signal when transmitting in amultichannel configuration.

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TABLE IMODULATION ACCURACY MEASUREMENTS OF A 64-QAM SIGNAL

CENTERED AT 1.5625 GHZ.

Result for a Result for a singlemultichannel data channel data Unittransmission transmission

EVM 1,8 1,4 %Magnitude Error 0,8 0,6 %Phase Error 1,0 0,7 degSNR (MER) 34,7 37,0 dB

Fig. 15. Constellation of a 64-QAM signal centered 1.5625 GHz.

As can be seen, the usable bandwidth of ≈15 MHz is kept

in this multichannel transmission scenario.

The modulation accuracy measurements for a 64-QAM sig-

nal centered at 1.5625 GHz when the architecture is configured

for a) multichannel data transmission and b) single channel

data transmission are shown in Table I. The obtained results

show a 2.3 dB loss in terms of Modulation Error Ratio (MER)

for the multichannel approach. This small degradation is due

to the higher in-band noise resulting from overlapping the

desired signal within a low noise region of the other channel.

Nevertheless, the Error Vector Module (EVM) is lower than

2% in both cases, which is more than sufficient for enabling

a well-defined constellation, as can be seen in Fig. 15.

The maximum operating frequency of this agile RF trans-

mitter is 233.0 MHz for the FPGA internal logic. This fre-

quency is limited by a critical path between the first to the

second delay in the ΣΔ modulator datapath shown in Fig. 8

Regarding the occupied resources, the entire datapath takes

only about 1% of the FPGA fabric, see Table II, providing a

large area available for other system functionalities, as well as

a vast grade of integration including, for instance, processing

of baseband protocols and higher protocol layers such as the

Medium Access Control (MAC).

TABLE IIMAIN OCCUPIED RESOURCES OF THE IMPLEMENTED FPGA-BASED

ALL-DIGITAL TRANSMITTER.

Without the With theLogic resources PHY control PHY control Available

processor processor

Flip-Flops 291 2516 478080LUTs 496 3136 239040RAM36E1 14 15 768GTHE1 QUADs 1 1 6

VI. CONCLUSION

In this paper, an FPGA SoC architecture containing a multi-

channel RF transmitter is presented and evaluated. The use of

a second-order ΣΔ modulator with a CIFB topology permits a

high operating frequency which consequently enables a higher

usable bandwidth and relaxes the quality factor requirements

of the RF output filter.

Moreover, the combined use of reconfigurable hardware

with a new radio architecture resulted in a very flexible

transmitter, capable of concurrent transmission of multi-band,

multi-rate and multi-standard signals, making it interesting in

the scope of white spaces exploration and for software radio-

based applications.

ACKNOWLEDGMENT

This work was supported in part by the Portuguese

Foundation for Science and Technology under PhD schol-

arship ref. SFRH/BD/76807/2011, under project TACCS

ref. PTDC/EEA-TEL/099646/2008 and by the Instituto de

Telecomunicacoes under project DiRecTRadio ref. LA-LVT-8.

REFERENCES

[1] J. van de Beek, J. Riihijarvi, A. Achtzehn, and P. Mahonen, “TV WhiteSpace in Europe,” IEEE Trans. Mobile Comput., vol. 11, no. 2, pp.178–188, 2012.

[2] J. Mitola and G. Q. Maguire, “Cognitive Radio: Making Software RadiosMore Personal,” IEEE Personal Communications, vol. 6, no. 4, pp. 13–18, Aug. 1999.

[3] J. Mitola, “The Software Radio Architecture,” IEEE CommunicationsMagazine, vol. 33, no. 5, pp. 26–38, May 1995.

[4] Z. Ye, J. Grosspietsch, and G. Memik, “An FPGA Based All-DigitalTransmitter with Radio Frequency Output for Software Defined Radio,”in Proc. Design, Automation & Test in Europe Conf. & Exhibition DATE’07, 2007, pp. 1–6.

[5] M. Helaoui, S. Hatami, R. Negra, and F. M. Ghannouchi, “A NovelArchitecture of Delta-Sigma Modulator Enabling All-Digital MultibandMultistandard RF Transmitters Design,” IEEE Transactions on Circuitsand Systems, vol. 55, no. 11, pp. 1129–1133, 2008.

[6] F. M. Ghannouchi, “Power Amplifier and Transmitter Architectures forSoftware Defined Radio Systems,” IEEE Circuits and Systems Magazine,vol. 10, no. 4, pp. 56–63, 2010.

[7] B. T. Thiel, A. Ozmert, J. Guan, and R. Negra, “Lowpass Delta-Sigma Modulator with Digital Upconversion for Switching-Mode PowerAmplifiers,” in Proc. IEEE MTT-S Int. Microwave Symp. Digest (MTT),2011, pp. 1–4.

[8] J. Sabater, J. M. Gomez, and M. Lopez, “Towards an IEEE 802.15.4SDR Transceiver,” in 17th IEEE International Conference on Electron-ics, Circuits, and Systems (ICECS), 2010, pp. 323–326.

[9] T. Kitayabu, Y. Amano, and H. Ishikawa, “Concurrent Dual-BandTransmitter Architecture for Spectrum Aggregation System,” in Proc.IEEE Radio and Wireless Symp. (RWS), 2010, pp. 689–692.

[10] M. A. Dahab, K. A. Shehata, S. Ramly, and K. A. Hamouda, “FPGAPrototyping of Digital RF Transmitter Employing Delta Sigma Modu-lation for SDR,” in Proc. National Radio Science Conf. NRSC 2009,2009, pp. 1–8.

[11] N. V. Silva, A. S. R. Oliveira, U. Gustavsson, and N. B. Carvalho, “ANovel All-Digital Multichannel Multimode RF Transmitter Using Delta-Sigma Modulation,” IEEE Microw. Wireless Compon. Lett., vol. 22,no. 3, pp. 156–158, 2012.

[12] ——, “A Dynamically Reconfigurable Architecture Enabling All-DigitalTransmission for Cognitive Radios.” in RWS. IEEE, 2012, pp. 1–4.

[13] S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters(Theory, Design, and Simulation), 1st ed. Wiley-IEEE Press, 1996, no.282-293.

[14] R. Schreier, “MATLAB Delta Sigma Toolbox,” Available athttp://www.mathworks.com/matlabcentral/fileexchange/19.

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