A 128-phase Delay-Locked Loop with Cyclic VCDL

Chien-Hung Kuo and Yu-Chieh Ma Dept. of Applied Electronics Technology,

National Taiwan Normal University, 162, He-ping East Road, Section 1, Taipei, Taiwan 10610, R.O.C

E-mail: chk@ntnu.edu.tw Abstract

A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.

Keywords Multi-phase DLL, Clock generator, Cyclic VCDL

1. Introduction Due to the stable first-order loop and no jitter

accumulation characteristics the multi-phase delay-locked loop (DLL) can be widely found in synchronous systems, such as clock generator, frequency synthesizer, and clock and data recovery circuit [1]-[3]. In modern high speed sample systems, multi-phase DLLs often requires a great amount of delay cells to generate high resolution output phases. Unfortunately, too many phases would result in uneven routing and much parasitics, and thus causing unacceptable timing error of output phases.

To reduce the number of delay cells, [4] proposes an array of DLLs to produce high resolution output phases. A dual-DLL approach [5] is also published to reduce the number of DLLs and the corresponding power by the addition of multiplexers, as shown in Fig. 1. However, the sub-DLL will start locking after the main-DLL is locked, and thus double the locking time will be required in the dual-DLL structure. Moreover, the dual-DLL cannot simultaneously provide all output phases, it will be hard to apply to real-time systems.

In this paper, a new cyclic voltage controlled delay line (VCDL) with impulse input for multi-phase DLL is proposed to reduce the number of delay cells and their corresponding power. A simple clock to impulse generator is devised to enter the sixteen delay cells of VCDL eight times to obtain 128 phases of outputs. A 3-bit counter is also inserted to complete the count of times the input impulse passing through the VCDL.

In section 2, the architecture of proposed multi-phase DLL will be introduced. In section 3, the detail circuit design of the presented DLL will be described. In section 4, the simulation results will be discussed. Finally, a conclusion will be given in section 5.

Figure 1: Dual-DLL for multi-phase output [5].

Figure 2: Proposed multi-phase DLL with cyclic VCDL.

2. Multi-phase DLL with Cyclic VCDL The block diagram of the proposed multi-phase DLL is

shown in Fig. 2. Since the control voltage, Vc, of the VCDL is close to VDD while the DLL is locked in this design, the supply voltage is used to charge it at the beginning. A clock to pulse generator is applied to the input to perform the cyclic operation of VCDL. Because the VCDL is operated at the lowest speed at the start, two pulse outputs, vin1 and vin2, with half input clock frequency are generated and respectively transferred to VCDL and phase and frequency detector (PFD) to avoid false locking, as the timing diagram shown in Fig. 3. A 3-bit counter is used to count the number of loop which the input pulse passes through. The 128th phase generated from the delay cell D16 will feed back to the PFD and charge pump (CP) for general locking process. When the DLL is locked, a lock detect (LD) signal will turn off the supply of PFD and CP to save their consumed power. The pulse vin2 from PG will also be switched off. Thus, the voltage Vc should be stabilized by additional controlled circuit.

978-1-4799-1314-5/13/$31.00 ©2013 IEEE 10 5th Asia Symposium on Quality Electronic Design

Figure 3: Timing diagram of the proposed multi-phase DLL.

3. Circuit Design 3.1 Input Pulse Width for Cyclic VCDL

In the presented VCDL, sixteen delay cells are designed for the cyclic pulse input, as shown in Fig. 4. Since the pulse will feed back to the input of VCDL after each cycle, the pulse widths must be confined to prevent the aliasing of two pulses occurred at the input node, N, of VCDL. That is, if the pulse width, wp, is equal to or greater than 16×tD, where tD is the delay time of a delay cell, then an uncertain state would be generated at the input of VCDL, as shown in Fig. 5. Therefore, the pulse width cannot be larger than 16×tD for the presented cyclic pulse transmission. On the other hand, if the input pulse width is too small, then the pulse might be diminished and faded due to the limited driving ability of delay elements. Thus, the pulse width must be deliberated to proper operation of VCDL, as shown in Fig. 5(c). In this design, the pulse width of 200 ps is designed in the pulse generator.

To ensure the pulse can be properly delivered in the VCDL loop, two switches are added at the input. The switch SW1 will be kept turning on until the input pulse is passed through it. The switch SW2 will be immediately turned on after the input pulse going low. Therefore, the pulse will keep delivering in the cyclic VCDL. Finally, the switch SW2 will be turned off while the pulse enters the delay cell D1 eight times. The clock will generate a new input pulse and activate SW1 for the succeeding locking process.

Figure 4: Cyclic VCDL.

(a) (b) (c)

Figure 5: Input pulse width, Wp, is (a) equal to 16×tD, (b) larger than 16×tD, and (c) smaller than 16×tD.

3.2 Delay Cell The delay cell used in the presented multi-phase DLL is

shown in Fig. 6. To adjusting the propagation time of the delay cell, a simple RC circuit is realized by two transistors, M1 and M2, at the input. The resulting impedance of M1 is regulated by the controlled voltage VC of VCDL. A simple pulse generator using half-transparent (HT) circuit is devised to shape the pulse after the RC circuit. The added switch S at the front of delay cell is always turned on to imitate the delay time caused by the switch SW2. For the matching consideration among all delay cells, there is no switch S existed in the first delay unit D1.

Figure 6: Internal circuit of the delay cell.

3.3 Lock Detector To save the power consumption of the whole circuit, the

lock detector is devised as shown in Fig. 7. The signal vin2 used for here is synchronized with the input vin1. When the final phase is emerged by the delay unit D16, a switch will send this phase to the input node B of lock detector. Two D-type flip-flops are used to provide a finite time difference, T, as the bound region for the phase comparison. While the signal vin2 is bounded between the 128th phase and its corresponding delay, a lock detector signal will be announced, as shown in Fig. 8. In this work, the time difference T is 55 ps.

Q

rstDFFD Q

rstDFFD

Tstart

D16(128)

vin2LD

CQ Q

AB

Figure 7: Internal circuit of lock detector.

(a) (b) (c)

Figure 8: The 128th phase and its delay (a) lead, (b) lag, and (c) surround vin2.

4. Simulation Results The proposed multi-phase DLL is implemented in TSMC

90nm 1P9M CMOS technology. The delay time of the presented cyclic VCDL versus the controlled voltage in typical and corner processes are shown in Fig. 9. The frequency of input clock is 92.16 MHz and the supply voltage of VCDL is 1.2 V. The locking process is shown in Fig. 10.

Figure 9: Delay time of the presented cyclic VCDL vs. controlled voltage.

Figure 10: Locking process.

0 20 40 60 80 100 120

-0.1

-0.05

0

0.05

0.1

0.15

Phase Number

LSB

DNL

(a) DNL

0 20 40 60 80 100 120

-0.1

-0.05

0

0.05

0.1

0.15

Phase Number

LSB

INL

(b) INL

Figure 11: Obtained (a) DNL, and (b) INL of the proposed multi-phase DLL.

The PFD and CP are activated every two clock cycles, and they will be turned off after DLL is locked to reduce the power consumption. A stable voltage close the final locked value will be apply to the controlled voltage of VCDL to suppress the jitter of output phases.

The linearity of the proposed multi-phase DLL are shown in Figs. 11 (a) and 11(b). The derived DNL is from -0.05 to +0.06 LSB, and the INL is from -0.06 to +0.07 LSB. The simulated peak-to-peak jitter of the buffer D1 is 3.97 ps with 3000 repeated cycles, as shown in Fig. 12. The performance of the presented DLL is summarized in Table I.

Figure 12: Jitter of the delay cell D1 under 3000 hits. Table I: Performance summary of the proposed Multi-phase

DLL with Cyclic VCDL. Parameters Value Technology 90 nm 1P9M CMOS

Supply Voltage 1.2 V Input Clock Frequency 92.16 MHz

Locked Time < 500 ns Number of Output Phases 128

DNL -0.05~0.06 LSB INL -0.06~0.07 LSB

Peak-Peak jitter 3.97 ps @ 92.16 MHz RMS jitter 611.22 fs @ 92.16 MHz

Power Consumption 9.2 mW @ 92.16 MHz

5. Conclusion The multi-phase DLL with cyclic VCDL is proposed to

simultaneously generate 128 output phases. Only sixteen delay cells are used to construct the VCDL. The number of delay units is successfully reduced. A pulse instead of a reference clock is used as the input of the DLL to perform the cyclic loop without occurring overlapped error on signals. The power consumption of the presented DLL is 9.2 mW at a 1.2 V supply voltage and 92.16 MHz input clock frequency.

6. Acknowledgment This research was supported in part by a grant of making

chips from National Chip Implementation Center (CIC). The authors would also like to thank National Science Council of Taiwan for the financial support of this work.

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[4] J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 952–957, Jul. 1996.

[5] S. C. Lin and T. C. Lee, “An 833-MHz 132-phase multiphase clock generator with self-calibration circuits,” in Proc. IEEE Asian Solid State Circuits Conf., 2008, pp. 437–440.

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