Parameters Optimization of Lateral ImpactIonization MOS (LIMOS)

Ankit Dixit, Sangeeta Singh, P. N. Kondekar, Pankaj Kumar, Bharti ModiDepartment of Electronics and Communication Engineering,

PDPM-IIITDM Jabalpur, MP, India.

Email: (ankit.dixit, sangeeta.singh, pnkondekar, pankajjha)@iiitdmj.ac.in, modi.bharti@gmail.com

Abstract—Impact Ionization MOSFET (IMOS), has emergedto combat one of the most critical and fundamental prob-lem of sub-threshold slope (SS) which cannot be lower than60mV/decade at room temperature for conventional MOSFET,as conventional MOSFET works on the principle of diffusion ofcharge carrier for the current flow in the device. Whereas, theIMOS devices work on the principle of avalanche breakdownto switch from the ‘OFF’ state to ‘ON’ state. In this paper,we have optimized the device performance of the Lateral impactionization MOSFET (LIMOS) by varying the device dimensionalparameters, such as gate length Lg , intrinsic length Lin, gate di-electric thickness tox and biasing voltages Vg and Vs. Simulationresults claims that the ratio of Lg/Lin has to be properly tunedfor the optimum device performance. If this ratio approachesto one LIMOS performance are optimized, whereas if it is veryhigher than one it behaves as Tunnel Field Effect Transistor(TFET) and if it is very less than one it effectively behaves asgated PIN diode. Simulation results show the sub-threshold slopeSS to be 1.373mV/dec for our optimized LIMOS. Considerableimprovement in other device performance parameters namelyIon, Ioff , Ion/Ioff ratio, threshold voltage Vth, breakdownvoltage Vbr , drain induced current enhancement DICE, and gateinduced barrier lowering GIBL has been reported.

Index Terms—Impact Ionization MOSFET (IMOS), draininduced current enhancement (DICE), gate induced barrierlowering (GIBL), gated PIN diode.

I. INTRODUCTION

MOSFETS have been the most popular devices the for

past five to six decades because of its excellent scalability.

Therefore, researchers accelerated its scaling as it showed

excellent performance and scaling properties. But in past

decade of semi-conductor industry faces many challenges

related to scaling, as per ITRS the scaling of CMOS device

and its process technology is expected to end at the 16-

nm node by the year 2019. These challenges are related to

several fundamental and practical limits related to transistor

operation and manufacturability, such as leakage currents,

mobility, reliability, sub-threshold swing (SS) and in turn

affects the device performance. The conventional MOSFET

has the physical limitation of the sub-threshold slope SS. It is

defined as

SS = dVgs/d(logId) (1)

where, Vgs is the gate to source voltage and Id is the drain

current. Theoretically the minimum value of SS for a conven-

tional MOSFET is given by its diffusion limit kT/q× (ln10)= 60mV/dec at 300 K. Therefore, many novel devices have

been proposed to replace or complement CMOS whose device

operation are not diffusion limited. Among them, this paper

focuses on the Impact Ionization MOSFET (IMOS) device [1],

[2] and [3]. The key feature of the IMOS device is that it has a

subthreshold swing less than 60 mV/dec at room temperature

which is the theoretical thermodynamic limit of the MOSFET.

IMOS is a gated p-i-n diode, unlike conventional MOSFET it

has the source and the drain with opposite kind of dopants and

there exists an i-region which is not completely overlapped

by the gate. The propose of i region is to induce avalanche

breakdown between the source and the channel and to suppress

unwanted band-to-band tunneling. Its operating principle is

totally different from that of the conventional MOSFET. MOS-

FETs control thermally-injected carriers by a channel potential

barrier governed by the gate voltage. Whereas, I-MOS devices

with no channel potential barrier use the potential difference

between the source and the channel to determine whether

breakdown occurs or not. Since the carriers of I-MOS devices

are injected by avalanche breakdown process instead of ther-

mal injection, the subthreshold swing can be reduced below 60

mV/dec at room temperature. In literature various aspects of

the IMOS operation, biasing [4], process flow [5] and circuit

level implementation and performance estimation and memory

implementations [6] along with the analytical and compact

mathematical modeling [7] are reported. The lateral structure

of IMOS is regarded as Lateral impact ionization MOSFET

(LIMOS). Apart from this structure vertical structure for

IMOS, Vertical Impact Ionization MOS (VIMOS) has also

being developed and analyzed [8], [9] and [10].

But still there is is an important literature gap in the op-

timization of parameters of Lateral Impact Ionization MOS

(LIMOS), i.e, device performance dependency on various

device dimensional parameters, such as gate length Lg , in-

trinsic length Lin, gate dielectric thickness tox and biasing

voltages are not investigated in detail. Hence, in this paper we

have optimized the device performance by varying the device

dimensional parameters, such as gate length Lg , intrinsic

length Lin, gate dielectric thickness tox and biasing voltages

Vg and Vs. This paper is structured as follows. In Section

II, the simulation method and the setting of the parameters

for studying the device characteristics and device operation

are introduced, Section III device performance is optimized.

Finally, Section IV concludes the optimization analysis of

LIMOS.

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II. DEVICE STRUCTURE AND SIMULATION

Fig. 1 shows the LIMOS architecture used for the simulation

modeling and optimization, it is an silicon-on-insulator (SOI)

implementation. Conceptually, the LIMOS transistor can be

regarded as a combination of a p-i-n diode and a MOS

transistor, hence the device is divided into two parts. The first

is composed of the MOS part of the IMOS, and second part

is composed of the intrinsic area. In this n-channel device, the

p+ is the source and the n+ is the drain because the p-i-n

diode is always reverse biased. As per concept level analysis,

the two sub parts of LIMOS elements are not discrete and

their operations are highly related. The vertical gate induced

field and the MOS surface carrier concentration affect the

breakdown voltage of the diode and the surface concentration

of carriers in the ‘ON’ state of the IMOS transistor depends on

the number of carriers injected by the avalanche breakdown

mechanism in the diode.

The various device performance parameters such as drain

current Id, on-current Ion, off-current Ioff , on-current to off

current ratio Ion/Ioff , DICE, GIBL, sub-threshold slope (SS),

and transconductance gm for the LIMOS are investigated

and optimized using Synopsys TCAD Sentaurus simulator

version vG-2012.06 [11] and [12]. To obtain accurate device

simulations for impact ionization device, simulations included

all models used to describe common device behavior including

both VanOverstraetendeMan impact-ionization and the band-

to-band tunneling model, along with the bandgap narrowing

model, and Shockley-Read-Hall and Auger recombination at

300K and it is assumed that the avalanche coefficients of

carriers near the surface are the same as the values in the bulk

of the material. For mobility, doping as well as transverse-

field models are considered. Table I. enlists the various device

parameters used during LIMOS device simulations and opti-

mization.

Fig. 1. Structure of stimulated and optimized LIMOS

III. SIMULATION RESULTS AND DISCUSSION

For better appreciation of various LIMOS device perfor-

mance parameters are evaluated and optimized. Fig. 2 shows

TABLE ITABLE I. PARAMETERS USED DURING THE DEVICE

SIMULATIONS

Parameters LIMOS structure

Channel length (Lch) 100nm

Gate length (Lg) 20, 50, 60, 70 & 80 nm

Intrinsic length (Lin) 80, 50, 40, 30 & 20 nm

Doping Nd 1019cm−3

Doping Na 1019cm−3

Gate thickness (tox) 3nm

Gate work-function 4.17eV

Gate bias 0V to 2V

the plot for drain current for n-channel LIMOS as a function

of the gate voltage with drain voltage Vd= 1V and Vs= -8V

at different Lg/Lin ratios. It is clearly inferred that when this

ratio approaches to one LIMOS drain current is enhanced,

whereas if this ratio is very higher than one then it reduces

similarly, when it is very less than one then also it degrades.

In similar way, Fig. 3 shows the plot for drain current for n-

channel LIMOS as a function of the source voltage with gate

voltage Vg= 1V at different Lg/Lin ratios, it is also showing

the similar behavior on varying the Lg/Lin ratio.

This variation in the device characteristics with respect to the

Lg/Lin ratio is because when the ratio is low LIMOS is

effectively a gated PIN diode structure with high breakdown

voltage and the gate controllability on the effective channel

length modulation is weak. As the gate controlled effective

channel length modulation is the key mechanism for the

LIMOS working, and it is low for less Lg/Lin ratio, and

device performance degrades. As Lg keeps on increasing the

ratio increases and the gate control on the channel enhances

and in turn device performance enhances. As a result of

enhanced channel length modulation by the gate, device gives

its optimum performance when the ratio is near one or Lg and

Lin are comparable. But, as Lg increases further as channel

length is constant, Lin decreases accordingly. As this ratio

gets higher and higher intrinsic region gets lower and lower.

The intrinsic region of LIMOS is the most active region of the

device, because impact ionization takes place in the intrinsic

region only and if this region gets on decreasing the number

of charge carriers generated after impact ionization keeps on

decreasing and hence, the device on current decreases and the

device performance degrades a lot for higher Lg/Lin ratio. For

higher Lg/Lin ratio LIMOS is effectively TFET with intrinsic

substrate and it gives less on-current and higher breakdown

voltage Vbr and threshold voltage Vth. As there is no drain

induced barrier lowering DIBL concept for the LIMOS sim-

ilar device parameter, i.e, drain induced current enhancement

DICE is used to study this behavior of the LIMOS. Hence,

DICE of LIMOS corresponds to DIBL concept of conventional

MOSFET. Table II. enlists the various device performance

parameters dependency on Lg/Lin ratio for tox=3nm, Vg=

1V and Vd= 1V.

In order to give in-depth analysis of the impact ionization

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Fig. 2. Id v/s Vg characteristics for LIMOS at different Lg/Lin ratios.

Fig. 3. Id v/s Vs characteristics for LIMOS at different Lg/Lin ratios.

mechanism going inside the LIMOS various parameters as,

impact ionization rate in different regions in the device, electric

field and band-gap narrowing are studied for optimized de-

vice dimensions, i.e, for Lg=60nm, Lin=40nm, tox=3nm and

Vg=1V. As the impact ionization rate depends on the electric

field in the drain side intrinsic zone. Rising the drain source

voltage increases the impact ionization rate exponentially. Fig

4. shows the electric field variation with respect to the x-

axis device dimensions. The maximum electric field occurs

at x = 0 and its value is 2.541 × 106V/cm. The potential

difference between drain and source give rise to the electric

field in the drain sided intrinsic region. As the drain-to-source

voltage increases, this electric field can be increased until

a significant impact ionization rate occurs in the drain side

intrinsic zone. At this point, the electrical behavior changes to

impact ionization mode and hence current is injected because

of impact ionization not because of drift and diffusion. Fig.

5 shows simulated impact ionization rates for the device and

it is maximum in the intrinsic region in accordance with the

established theory. Bandgap narrowing in the device for Lg=

60nm & Lin= 40nm is shown in Fig.6 and it is maximum in

source and the drain regions.

Fig. 4. Electric field variation with respect to the x-axis device dimensionsfor Lg= 60nm & Lin=40nm.

Fig. 5. Impact ionization rates in the device for Lg= 60nm & Lin=40nm.

Apart from the Lg/Lin ratio another important device

dimension parameter is the gate dielectric thickness tox. The

optimization of the device performance has been done for

tox variation as well. Fig. 7 shows the plot for the Id v/s

Vg characteristics for LIMOS at different tox= 2nm, 3nm,

4nm and 5nm at Vd= 1V. It shows the optimum performance

for tox = 3nm. Fig. 8 shows the plot for the Id v/s Vs

characteristics for LIMOS at different tox= 2nm, 3nm, 4nm

and 5nm at Vg= 1V. Table III. enlists the various device

performance parameters dependency on tox for Lg = 60nm& Lin = 40nm.

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Fig. 6. Bandgap narrowing in the device for Lg= 60nm & Lin=40nm.

Fig. 7. Id v/s Vg characteristics for LIMOS at different tox variations.

The impact of the gate voltage Vg at the breakdown voltage

Vbr is very much pronounced. Hence, in Fig.9 shows Id v/s

Vs characteristics for LIMOS at different Vg variations. It is

clearly shown that Vbr decrease as Vg increases. This effect

of the gate voltage Vg on the breakdown voltage Vbr variation

has been tabulated in Table IV.

Fig. 8. Id v/s Vs characteristics for LIMOS at different tox variations.

Fig. 9. Id v/s Vs characteristics for LIMOS at different Vg variations.

IV. CONCLUSION

In this paper, we have optimized the LIMOS device perfor-

mance by varying the device dimensional parameters, such as

gate length Lg , intrinsic length Lin, gate dielectric thickness

tox and biasing voltages Vg and Vs. Simulation results claimed

that the ratio of Lg/Lin has to be properly tuned for the

optimum device performance. If this ratio approaches to one

LIMOS performance are optimized, whereas if it is higher than

one it behaves as Tunnel Field Effect Transistor (TFET) and

if it is very less than one it effectively behaves as gated PIN

diode. Simulation results show the sub-threshold slope (SS)

to be 1.373mV/dec for our optimized LIMOS, i.e, Lg/Lin is

approximately one. Considerable improvement in other device

performance parameters namely Ion, Ioff , Ion/Ioff ratio,

threshold voltage Vth, breakdown voltage Vbr,drain induced

current enhancement DICE, and gate induced barrier lowering

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TABLE IIDEVICE PERFORMANCE PARAMETERS OF LIMOS FOR LENGTH OPTIMIZATION, I.E, Lg/Lin RATIO VARIATION.

Parameters Lg/Lin = 0.25 Lg/Lin = 1.0 Lg/Lin = 1.5 Lg/Lin = 2.33 Lg/Lin = 4

SS (mV/dec) 1.603 1.373 4.239 7.698 20.91

Vbr (V) -8.65 -7.75 -7.549 -7.181 -6.421

DICE (mV/V) 135.5 106 74.4 51.77 37.88

GIBL (mV/V) 750 900 974 1044 1059

Vth(V) 1.7031 0.7584 0.692 0.79512585 1.0176795

Ion(A/μm) 4.63× 10−5 3.15× 10−4 2.76× 10−4 2.91× 10−4 3.25× 10−4

Ioff (A/μm) 7.66× 10−11 1.2× 10−10 1.64× 10−10 9.07× 10−10 1.48× 10−8

Ion/Ioff 6.04× 105 2.63× 106 1.68× 106 3.21× 105 2.20× 104

gm(A/V) 2.91× 10−04 4.57× 10−04 4.99× 10−04 5.30× 10−04 5.53× 10−04

TABLE IIIDEVICE PERFORMANCE PARAMETERS DEPENDENCY ON tox FOR Lg = 60nm & Lin = 40nm OF LIMOS

Parameters tox= 2nm tox= 3nm tox= 4nm tox= 5nm

Vbr (V) -7.45 -7.75 -7.9 -8.2

Vth (V) 0.455 0.6926 0.9163 1.12788

SS (mV/dec) 6.01 4.239 1.947 1.651

Ion(A/μm) 1.68× 10−4 1.47× 10−4 1.31× 10−4 1.10× 10−4

Ioff (A/μm) 1.45× 10−9 1.625× 10−10 1.241× 10−10 1.01× 10−10

Ion/Ioff 1.16× 105 9.02× 105 1.06× 106 1.09× 106

gm (A/V) 5.8× 10−4 4.99× 10−4 4.34× 10−4 3.82× 10−4

TABLE IVBREAKDOWN VOLTAGE Vbr DEPENDENCY ON Vg FOR Lg = 60nm &

Lin = 40nm OF LIMOS

Gate Voltage (Vg) Vbr (V)

0 V -8.523

0.5 V -8.054

1.0 V -7.549

1.5 V -7.086

2.0 V -6.655

GIBL has been reported.

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