A hstract

Introduction

and

with C',,,. I hi, I,, atid I I scr\.ing as the pli!.sicrill!: based fitting constants. T!.picul C-V and I - V nicxuring instiunicnts use a ramping voltiigc h i x with ;I rclativcly slo\i. time cx)nst;int conipaixd with t l ic trap time constant. I t i s sliwvn hct-cin t ha t these s l o w \.ariatioils i n applied bias alluiv the traps to allkct the smal l signal KF and microwave pcrl'orniancc 01: the diode.

To o b t a i n hi as-de pe t i de ii t de \, i cc mea sit IT ti1 c i i t s re prcsc t i 1 ;i t i \'e o 1' I h c de \. i cc' s c ha rx.1 c r i s t i cs ;it I< F and niicrowavc. ti'cqucncics. elimination 01' tlic clli.c.ts 01. I > < ' bias 011 the K F characteristics associrttcd with traps is ncccssar!'. .4 protot!'pc. autoniatcd. pulsed I - V pulscd S-pai;imctcr (PI V PSI') integrated measurement systcni w;is developed ;it Tcsas Insti'uniciits t o liicilitatc the nicasurcnicnt conditions ncccs- sa ry (0 I- ;icc u ra t c b i a s-d c pen d c n t de v i cc c ha rac t c ri %a t io t i . I n t h c fo I Io w i n g scc t ion s . a b 1-1 c 1' s ti ti1 m ;i r!' o I' t h c cfi'cct of traps on the frequency dcpcndcncc ol' a diode's I-V and C-V characteristics is introduced. 4 discussion of PIV/PSP measurement systim and nicasurcniciit techniques is prcscntcd. Mcmtrcnicn~ rcsults Ihcn follow.

1 Rs

UF11615024

Figure I . Standard Nonlinear Diode \liidel

Frequenq Response of Tr:ips

To a lirst-order Iippi.osiiiiation. traps with energies :ihovc tlic Fcrmi-lc\~cl :ire cippt).: and. thus. arc positively charged. and traps hclo\v the Fcrmi-lc\.cl arc occupied h\- clcctr(itis and ;ire neutral. Tlic solid lines in Figure 213 depict the c.Iiargc distriliiitioii w i t h i n the tlcplction region. The step i n the distribution at s = y is the addition;il charge contribution c~;iiisccI l~!, traps.

Traps interact wi th the v;iIciicc and conduction hand through the l'oiir proccsscs pt'gcncration nnd rccotiibination: electron ciipturc. clcc.tron emission. hole captui'c. ;lnd hole Thc tinic constant. 7,. :issociared \vitIi cxI i type ol'c*niission anci capture process cIiarac*tcri/cs t11c a\.cragc time i t takes tbr a trap to cniit or capturc an electron. Thus. ;IS tlic \.oltagc applied IO the junction changes. the bandwidth o f the trap's frequency response to the signal dcpcnds on the \aluc o f 7 , . This time constant is described b!. the expression

whcrc I ' , ~ is the thcrmal \:cloc.it!, oI'c-lcc.trons. ma, is the capture cross section o f t l i c trap. .\'f is the densit!. ot' stirtiice states. is the energy 01' the li'ap. and 7 ' is the Ic'~11pcr;~tui-c ol'thc sciiiicondiictoi: I~cc:iusc ot'this trap tinic constant. changes i n the c.hargc clistribution clcpcnd on the li'cqucnc).:. us. ol'thc impressed signal across the diode. CJndcr the low-ti-equcnc).: condition. when us < 2~1;. the traps can respond to the variation o f the impressed signal b y emission and capturc proccsscs. Thc dashed lines in Figure 2 B sho:v this change during a low-frequency. incremental rcvcrsc bias. Note the charge contribution caused h:; traps tracks the change in bias. Under thc high-frcqucncy condition. when us > 2rt;. only the shallou. donors arc ablc lo rcspond. and the charge distribution caused by the traps is stationary. Figure 2C shous thc change in thc chargc distribution under thc high-fi-cqucncy condition.

37

c

i - N t N

d t

7 ,

T A Y C

t

I

7-1 I

N I

I & I

d - , c a w

Figure 2. Schottk:, Barrier .Junction Il 'ith Traps: (..I) Zero Bias. ( B ) Reverse Bias. and ( C ) Increasing Reverse Bias

I I

1

N + N d t

In addition. the relationship bctwccn trap occup;incy and the li-cqiicncy content of the applicd bias is also afTccrcd by ttic tcnipcr-ntiir-c ot'tlic junclion. Kcwriting Equation ( -3 ) .

\

t

I

I I

N I

I t.'

d - Y A W

I t can be seen that. as temperature iiictuscs. tlic separation bctwccn the conduction band and ihc Fermi- level increases. As a result. the point at which thc trap lcvcl intersects the Fcrnii-level (Figure 2.4) shifts to the right thercby increasing the amount ol'chatgc in the depletion region caused by ionized traps. Thus. heating of the diode by the impressed signal also alkcts the charge distribution of the depletion rcgio?. The wo,rk prcscntcd here docs not deal with tlic c k t s of Junction heating o n traps. Howcvcr. tlii:. method provides a means of stabilizing tlic junction tcmpcratiirc during bias-dcpcndent nicasurcnicnts.

Effects of Traps on C-\,' and I- \ ' Charactcristics

I 500kHz 0 I I I I I I

The charge w i t h i n the dcplction region dircctl! allkcts the junction capacitancc o1'tlic diode. Figure 3 graphicall!, illustrates h o w tixps impart a I'tulucnc!. dcpcndcncc to the \.aIuc of the junction capaci- tancc. Tlic plot is ot' liic'? as ;I I.iinction of rc\~crsc hias ;it dillkrcnl mcnsurcmcnt licqucnc.ics. Obser\~e that. as frequency is increased. the \.aluc ot'thc mcasurcd capacitance dccrcr~scs. From tlic previous discussion about frequency dcpcndencc of traps. lhc slow change 01' the DC hias also can alli.ct the charge cicnsity in ;lie dcplction region. thus allkcring the tiicxurccl capacitancc. This l lc ' interaction \vith the high- 1'requcticy AC' characteristic is not accounted 11)~ b!. the t!.pical (1-V iiic;isurcmcnt technique sho\vii in Figure 3 . Another c lkct associated wit11 !raps ( i n this c;isc. surface traps) i s (.-V str.ctch-out. C-V stretch- out is the sliili in the rcquircd gate \.olt;igc cscursion ncccssar!. IO achic\.c ;I spc\cilic capacitiincc \.ariation.

HIGH-FREOUENCY LIMIT

Sze4)

39

Measurement Technique

TEKTRONIX b DIGITIZING

OSCILLOSCOPE WAVETEK

Figure 3 shows the conligiiration of the PIV:PSP nicasurcnictit s!'stcm used in characterizing Ga.As Schottky barrier diodes. This system comprises a custoni pulsed I-V nicasut-cnicnt subsystem dc\,clopcd at Texas Instruments and a Wiltron Model-360 pitlsccl vector network analym-,

- HP11612A HP11612A - OPT 001 - OPT 0 0 1 BIAS TEE BIAS TEE

-

The PIV subsystem has three channels for cliar:icterimtion 01' up t o thrcc-port devices. Two ot' tlic channels can deliver prograniniablc quiescent voltages from - I O V to + I O V. as well as programniablc pulse voltages ranging from -20 V to 20 V. The third clianncl drivevscnscs larger currents and can deliver prograniniablc quiescent voltages from 0 V to 18 V. as well as programniablc pulse \,oltngcs ranging from 0 V to 32 V. cacti at up to 2 amps with a settling time to 0.01 pcrccnt in less than 700 t is.

-

In addition. thc voltage and curt'cnl sensing circuits each ha\^ a dynamic range in csccss ol'S0 dB. bandwidth more t h a n 20 MHz. and rcsolutjons less than I n i V and less than 20 p.4. rcspccti\.eI!.. .A stabilization circuit was incorporated into tlic circuits to niasiniizc the stability ot' the dcvicc undcl- test (DUT) wi th respect to its terminating impedances. The f'lV circuits were designed spccilically t'or this application and pcrlbrni optimally tior pulse repetition liuiucncics (PKFs) Icss than 5 kHz. [ lndcv. tlicsc low-duty-factor conditions. the DOT applied DC' quiescent bins and junction tcnipcratiti-c remain con- stant regardless ol'thc energ!: in the pulses. A single channel ofthis subsystem \v:is used for making the Schot t k y d i ode nicasu rc nic t i 1s.

Tlic pulsed S-parameter mcasiit~ctiicnts arc pcifornicd with a Wiltron Mocici-3hO pulsed vector network analyzer. The Wiltron un i t gcticratcs two waveforms on application of an cstcrnal trigger. The lirst waveform is the stimulus pulse. or KF pulse. the signal to be measured. The second pulse \\a\.clbrtii is the profiling pulse that enables tlic vector sampling heads within the instrunicnt. RF signal tiieasurc- nicnts arc obtained during the protiling pulse. The Wltron u n i t can pcrforni either ;I complete prolilc or a lixcd prolilc measurement of the stimulus pulse. The diode tiicasurctiictits were made \\it11 t l ic Wiltron

I

I WILT RON SYNTHESIZED

UF11615027 FREQUENCY SOURCE

Figure 4. Prototype Pulsed I-V/Pulsed S-Parameter Integrated Test Set Block Diagram

40

un i t in t l ic liscd prolilc mode in which the protile pulse is set to a constant delay from the rising edge of tlic RF pctlsc. This system 113s a soliwarc-resident line-rcllcct-load (LRL) calibration routine lor both pulsed and CW mcasurcmcnts. To synchronize the PIV and PSI' siibsystciii. the entire system is ti-iggcrcd by a single cstcrnal pulse generator. For these mcasurenicnts. a 47-kHz PRF was used to cnsurc the S-parameter dynamic range was i n csccss o f 50 dU.

Tlic test dcviccs measured wcrc 75-pni GaAs Scliortky barrier diodes. The nicasiirenictits were made on wafer using a Cascade probe station. T\c.o-port pulsed S-parameter tiicasitrcnicnts wcrc m u c k on a series diodc using the system conliguratioii shown in Figurc 4. The pulsed I-V nieasiircmctits were niadc with the diodc. clfcctivcly. in a shunt conliguration. This is accomplished by connecting a short to the DC port o f the bias tee illustrated on the right in Figurc 4. lhus pro\.iding a return path to the syswni ground. The diode iiicasurcnicnts weir pctformcd at seven distinct quiescent hias points ( -6 V. --I V. -2 V. 30 mV. 10 niA. 25 niA. atid 35 mA). ,At cacli quiescent bias point. 50 distinct piilsc voltages ranging from -8 V to I .5 V were synclironizcd wi th S-parameter mcasiirctiicnts li-om 2 1:) 2 0 CF!z. The entire nieasurcnicnt cycle. including data collection. wis automatcd.

Measurement Results .

The fot-ward pulsed I-V cI1;ir:ictcristics ol'o typical Sc.liott!i!, cliotlc arc illustrntcd i n Figure 5 . N o t c the ttircc curves correspond to three distinct quiescent hiascs and show t l ic c\spcc.tcd Jcpcncicnc~c. 0 1 ' t l ic diode rot-ward turn-on voltage to quiescent hias level.

h Vl a 5 v

c z w LL LL 3 0

- OUIESCENT BIAS = -6.26 V -- OUIESCENT BIAS = -5.64 mV ...... QUIESCENT BIAS = +1.02 V

0.05

0.04

0.03

0.02

0.01

0

0.01 I I I I I 0.25 0.50 0.75 1.00 1.25

PULSE VOLTAGE (vo l ts)

UF11615028

Figure 5. Pulse I-V Measurement of CaAs Diode at Three Distinct Quiescent Bias Values of qV = --6.26 V. -5.64 mV, and 1.02 1

The C-V characteristics of thc diodes were csttxtcd li-on1 cach set o f S-paramctcr data. corrcspond- ing to cach pulsed bias cscursion. using the linear model of Figure I . The C-V characteristics ofa typical Schottky diode arc illustrated in Figure 6. Note tlic thrcc ctirvcs corrcspond to three distinct quiescent biascs and show the cspcctcd C-V stretch-out predicted by Nicollian and

Summary

A working PIVi'PSP nicasurcnicnt systcm has hecn dcnionstratcd. Measurements of GaAs Schottk! diodes WCIT made at sc\"d quiescent and pulse bias points. Mcasurcnicnts demonstrate the c l k t 01' scniiconductor traps on Schottky junction bari.icr height. as well as C-V slrctch-out.

Acknowledgements

Thc authors thank Wiltron for lhcir loan 01' the Pulse Vcctor Network ,Analyzer and Tcktronis for the loan of the ground-signal probes tiscd i n tlic nic;istii'enients. I n par-ticulai: tlianks to Toni Kilbor-tic of Wiltron for his technical assistance wi th con1igiir;itioii of the pulsed vcctor nctwork analyzer.

0.5

- 0.4 LL a v

W 0 5 0.3 t a

0 0.2

0

a 'f

0.1

0 qv = - 0.006V t 0 qv = - 0.006V

v qv = + 1.02ov

I I I I I J -2.0 -1.5 -1.0 -0.5 0 0.5 1.0

PULSE VOLTAGE (VOLTS)

l l i I16 1 % 35

Figure 6. CapJcitunce Versus Pulsed Voltage hrJmelerized By Quiescent Voltage

42

References

I . Antognetti. P.. and C;. Massobrio. cd. Sc,iiricu,/ri/iic,ro/. />rric.ci .\/odcdi/?~ i i i r h S'l'IC'I:. N c w York: McGraw-Hill. 1988. pp. 1-36.

I . Crowc. T.W. "Modeling and Optimization of Gallium Arscnidc Schottky Barrier Mixer Diodes." P1i.D. dissertation. University of Virginia. 1986.

Hclszajn. J . 1'ir.s.sii.c~ L i d . . l c ~ i i i r . l / i c . r o i i n i . c , C'ircwiis. New York: John Wiley S: Sons. 1975.

Szc. S.M. l'/ij~.sic~.s ( ? / ' . S c ~ ~ i i i c . o r ~ i / i i c . l o / . / lc~i . icx~.s . Id cd. New Yosk: John Wiley s( Sons. 198 I .

Kimcrling. L.C. "Inllucncc of Deep Traps on the Measurement of Frcc-Carricr Distribution in Semiconductor by Junction Capacitance Techniques." JOI / I . I ILI / (?/' . lp/ ) / id P/rj..sics. Vol. 54. No. 4. April 1974.

Balbci-g. I . "Relation Dctwccn Distribution of States and the Spacc-Chargc-Region Capaci- tance in Scniiconductors.'. J o i / r / i u / (!/'. l/)p/icd /'/rj*.sicx Vol. 58. No. 7. October 1985.

7. Rhodcrick. E.H.. and R.H. Willianis. . l l c J ~ ~ i / . S c J i / r i c . o i r t / i / c , r ~ ) / , ( ' o / r f c / c . f . s . 2d cd. N e w Yo&: Oxford Univcrsily Press. 198s.

Schocklcy. W.. and W.T. Kcad. Jr. "Statistics 01 ' tlic Rcconihination oI' Holcs and Elcctrons." P / r j ~ . s i ~ w / K c ~ r i c ~ Vol. 87. N o . 5 . pp. 835-8.1 I . Scptcnibcr I 9 j l .

Nicollian. E.H.. and J . R . Uscws. .\/OS i.1 I c i l u / 0.vit/;8 . ~ c ~ / / i i ~ , ~ ) / i ~ / ~ ~ ~ , ~ ( ~ / . ~ I'/ij..sic:s ~ i / r i / 7 i ~ . h / r o / o , y \ : New York: John Wilcy 6: Sons. 1982.

3.

4.

5 .

6.

8.

9.

43