New Low-Resistance and Compact MOSFETs for Analog Switch ICs with V-groove Dielectric Isolation

Kenji Hara and Junichi Sakano Hitachi Research Laboratory

Hitachi Ltd. 7-1-1 Omika-cho Hitachi-shi Ibaraki-ken 319-1292, Japan

E-mail: kenji.hara.vf@hitachi.com

Hironobu Honda, Junichi Aizawa and Taiga Arai Power & Industrial Systems Division

Power Systems Company, Hitachi Ltd. Hitachi-shi, Ibaraki-ken, Japan

Abstract— A low-resistance and compact MOSFET for analog switch ICs with Dielectric Isolation (DI) process technology is proposed. To obtain a high current density, we have developed new MOSFET with internal prominence, which reduce the drift resistance of devices with a high breakdown voltage. New N-ch and P-ch compact MOSFETs for level shifters have also been developed that can control saturation current with a low electric field under the gate region by using a junction field effect transistor structure for higher hot carrier reliability. The areas of these MOSFETs can be shrunk about 40% in 220-V devices.

I. INTRODUCTION High-voltage analog switch ICs are widely used in medical

ultrasound imaging systems and printed circuit board tester applications [1-2]. Figure 1 shows a block diagram of a conventional high-voltage analog switch IC [3]. To reduce system size and cost, low on-resistance and high saturation current have become more important for main switch MOSFETs with thick gate oxide. Moreover, MOSFETs for level shifters that also have thick gate oxide should have to reduce the saturation current and electric field for hot carrier reliability with a small device area.

To satisfy these requirements, we propose a new concept of low-resistance and compact MOSFET for analog switch ICs with dielectric isolation. To obtain a high current density, we developed a MOSFET with internal prominences, which reduces the drift resistance of devices with a high breakdown voltage. These prominences are formed without any additional processes in a conventional V-groove DI process by using isotropic etching [4-5]. New N-ch and P-ch compact MOSFETs for level shifters have also been developed that can control saturation current with a low electric field under the gate region by using a junction field effect transistor (JFET) structure for higher hot carrier reliability.

II. CONCEPT OF COMPACT MOSFETS

A. MOSFET for Main Switches Figure 2 shows cross sections of the conventional and

proposed MOSFETs for the main switches. The conventional structure has channel regions that are arranged like a mesh. The proposed structure has channel regions that are arranged like stripes and has internal prominences, which are formed between the channel regions. These prominences reduce drift resistance in devices with a high breakdown voltage. Moreover, they improve the performance of parasitic diodes and reduce the impedance of the main switch circuit. They can be formed with narrow V-groove patterns.

Figure 3 shows the process for fabricating the V-grooves and internal prominences. The L1 indicates the resist material space for V-groove etching for the device isolation area. A prominence is formed in the device area by making L2 shorter than L1. Prominence height is controlled by adjusting L2.

The buried n+ layer is connected with the drain electrode of the MOSFET. In the conventional structure, the current flows in the horizontal and vertical directions at the edge of the device and in only the vertical direction at the center of the device. The thickness of the n- substrate depends on the edge structure of the device to maintain a high breakdown voltage. Therefore, the distance between the drain region and the

Main SwitchesLevel Shifters

VNNVPP

UltrasoundSignal

Transducer

Figure 1. Block diagram of high-voltage analog switch IC.

SW#1

SW#2

SW#n

LS#1

LS#2

LS#n

Latches

CLLEVDD VPP: Positive supplyVNN: Negative supplyVDD: Logic supply

DIN

CLK

DOUT

ShiftRegister

978-1-4244-8424-9/11/$26.00 ©2011 IEEE 32

Proceedings of the 23rd International Symposium on Power Semiconductor Devices & IC'sMay 23-26, 2011 San Diego, CA

source region is excessively long at the center of the device, which degrades drain current characteristics.

In the proposed structure, the distance between the drain region and the source region at the center of the device is shorter due to the formation of the internal prominences, and the current density is higher due to the reduction in the effective drift layer length and drift resistance. The breakdown voltage does not drop if the length between the drain and source regions at (A) in Fig. 2(b) is equal or longer than at (B). Figure 4 shows the potential distributions for the conventional and proposed MOSFETs for a main switch at the same current density. The drift resistance becomes lower for the proposed one.

B. N-ch MOSFET for Level Shifters Figure 5 shows cross sections of the conventional and

proposed N-ch MOSFETs for the level shifters. The conventional structure has a very long channel region to reduce the electric field under the gate region for higher hot carrier reliability. The proposed structure controls the saturation current by using a JFET structure instead of the conventional long channel region.

The source electrode in the proposed structure surrounds the gate electrode, and the channel region is formed along the edge of the gate electrode. The JFET resistance around the channel region increases with the voltage of the drain electrode. Therefore, the saturation current is suppressed, and the electric field under the gate region is reduced. The saturation current can be controlled by optimizing the space between adjacent channels (Lgate in Fig. 5(b)).

(a) V-grooveformation Si

(b) Buried layerformation &oxidation

SiO2

n+ buried layer

(c) Lapping I

(d) Lapping II

Si

SiPoly-Si

Figure 3. Process flow of DI wafer.

Turn over

L1 L2

(a)

(b)

(A)

Electric current

p

n-

n+

n+ n+p+n+ n+

SiO2

GateSource Drain

pp+

Gate Drain

p

n-

n+

n+ p+n+ n+

SiO2

pp+ n+

Tp(B)

Figure 2. Cross sections of MOSFETs for main switches:(a) conventional and (b) proposed.

A

A'

B'B

A A'GateSource Drain

GateSource DrainB B'

Source

Figure 4. Calculated potential distributions for (a) conventional and (b) proposed MOSFETs atsame current density. (0.2 V/line, J=0.06 mA/um)

(a)

(b)

Source

Drain

GateSource

Drain

Source

Gate Source

n-n+

n+

SiO2

GateSource Drain

pp

p+n+

ppn+p+

Source

JFET

p

n-n+

n+p+n+

n+

SiO2

Source Drain

p

Gate

Channel region

Lgate

Electric current

Figure 5. Cross sections of N-ch MOSFETs for level shifters: (a) conventional and (b) proposed.

(a)

(b)

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C. P-ch MOSFET for Level Shifters Figure 6 shows the proposed P-ch MOSFET device

structure for the level shifters. The conventional P-ch MOSFET for the level shifters also has a very long channel region for the same reason as for the N-ch one. The proposed structure also controls the saturation current by using a JFET structure instead of the conventional long channel region. The JFET region in the P-ch MOSFET is formed adjacent to the RESURF (REduced SURface Field) layer in the plane direction.

In the proposed P-ch MOSFET, additional n layers are formed on both sides of the RESURF p layer. These n layers are connected to the source electrode with large resistance and form the JFET region. The JFET resistance in the RESURF p layer increases with the voltage of the source electrode. Therefore, the saturation current is suppressed, and the electric field under the gate region can be reduced. The saturation current can be controlled by optimizing the space between the additional n layers (Lnn in Fig. 6(c)).

III. EXPERIMENTAL RESULTS To verify the effectiveness of the proposed MOSFETs, we

have fabricated sample devices using a 6-inch DI process.

A. MOSFET for Main Switch Figure 7 compares the characteristics of the proposed

MOSFET device for the main switches with those of the conventional one. The proposed device has 40% higher current density than the conventional one. Figure 8 shows the current density and breakdown voltage for various heights of the internal prominences (Tp, see Fig. 2(b)). The current density increases when Tp is increase. The breakdown voltage is constant up to Tp=1.0(au), and then started to deteriorate at

Tp=1.0(au). This is because the drift length between the drain and source at (A) (see Fig. 2(b)) is equal to that at (B) when Tp=1.0(au). Therefore, the prominences reduce the effective drift length without increasing the peak electric field below Tp= 1.0(au).

B. MOSFET for Level Shifters Figure 9 shows the drain current characteristics of the

proposed Nch-MOSFET for the level shifters at various gate-to-source voltages (Vgs). The saturation current is almost constant when Vgs is higher than the threshold voltage. This means that the saturation current is not only controlled by the gate voltage but also suppressed by the JFET resistance. The saturation current can be controlled by adjusting the width of the gate electrode (Lgate). Figure 10 shows the relationship between the drain current and Lgate. The drain current increase as Lgate is widened. Device size compared with that of the conventional type is also plotted in Fig. 10. With the proposed structure, the device size is less than 50% that of a conventional device.

Figure 11 shows the drain current characteristics of the proposed Pch-MOSFET for the level shifters at various Vgs. The saturation current is almost constant when Vgs is higher than the threshold voltage, as it is for the N-ch one. The saturation current can be controlled by adjusting the space between the additional n layers (Lnn). Figure 12 shows the relationship between the drain current and Lnn. The drain

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Drain to source voltage [V]Figure 7. Current density – drain voltagecharacteristics of main switch devices.

Conventional

This work

Vgs=100V, RT

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Bre

akdo

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volta

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Tp [au]Figure 8. Current density and breakdown voltagefor various heights of internal prominences.

Conventional (Current density)

n

n+

Source Drain

p+

Gate

pn

n

p+

A A'

B

B'

Figure 6. Proposed P-ch MOSFETs device structurefor level shifters: (a) top view, (b) cross section of A-A‘, and (c) cross section of B-B'.

(a)

n+

Drain

n-

SiO2

SiO2n+n-

n n

p

n

n+ p+

p+

Source GateA A'

Source electrode

JFET

(b)

(c)

Lnn

p RESURF

B B'

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current increase as Lnn is widened. Device size compared with that of the conventional type is also plotted in Fig. 12. With the proposed structure, the device size is less than 44% that of a conventional device.

IV. CONCLUSION To reduce the size and cost of high-voltage analog switch

ICs, we have developed a low-resistance and compact MOSFET for analog switch ICs with dielectric isolation that is fabricated using isotropic etching. To obtain high current density, we form internal prominences, which reduce the drift resistance of devices with a high breakdown voltage. The current distribution in the drift layer at the center of the device is made uniform by the internal prominence, which improves the drain current characteristics. The proposed structure has 40% higher current density than the conventional structure. N-ch and P-ch compact MOSFETs for level shifters have also been developed that can control saturation current with a low electric field under the gate region by using a JFET structure for higher hot carrier reliability. The areas of these MOSFETs can be shrunk about 40% in 220-V devices.

ACKNOWLEDGMENT The authors would like to thank Koichi Suda, Shinichi

Kurita and Takeya Ikeda for fruitful discussions and support on device fabrication.

REFERENCES [1] Bruno Haider, “Power Drive Circuits for Diagnostic Medical

Ultrasound,” Proceedings of ISPSD ’06, Plenary Session p. xxxiii, 2006.

[2] Richard K. Williams, Larry T. Sevilla, Eric Ruetz and James D. Plummer, “A DI/JI-Compatible Monolithic High-Voltage Multiplexer,” IEEE Trans. on Elec. Dev., vol. ED-33, pp. 1977 –1984, 1986.

[3] ECN3290 Datasheet, Hitachi Ltd. [4] Y. Sugawara, Y. Inoue, S. Ogawa and S. Kurita, “New Dielectric

Isolation for High Voltage Power ICs by Single Silicon Poly Silicon Direct Bonding (SPSDB) Technique,” Proceedings of ISPSD ’92, pp. 316-321, 1992.

[5] B. Murari, F. Bertotti and G. A. Vignola, “Smart Power ICs,” Springer-Verlag Berlin Heidelgerg, 2002, pp. 114–118.

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mA

/mm

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Gate-to-source voltage Vgs [au]

Figure 9. Drain current characteristics of proposed N-chMOSFET for level shifters: (a) Id-Vds and (b) Id-Vgs.

(a)

(b)

Vds=100 V

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Lgate [au]Figure 10. Drain current characteristics of proposed N-ch MOSFET for level shifters and device size compared with that of conventional one.

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m2]

Drain-to-source voltage |Vds| [V]

Figure 11. Drain current characteristics of proposed P-chMOSFET for level shifters: (a) Id-Vds and (b) Id-Vgs.

(a)

(b)

Vds=-100 V

Conventional

This work

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%]

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in c

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A/m

m2]

Lnn [au]

Figure 12. Drain current characteristics of proposed P-ch MOSFET for level shifters and device size compared with that of conventional one.

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