Abstract—This paper describes a low power clock and data re-covery (CDR) circuit with integrated ASK demodulator for wireless implantable neural recording microsystems. A modula-tion scheme based on amplitude shift-keying (ASK) and pulse position modulation (PPM) is employed to simplify the complex-ity of implant circuits and reduce power transmission require-ments. A charge-pump based CDR circuit is used to extract non-return to zero data from the demodulated waveforms. A prototype has been fabricated in 2-poly 3-Metal 0.6µm bulk CMOS technology in order to validate circuit functionality. The receiver front-end exhibits a sensitivity of 3.2mV p-p at 1MHz. The ASK demodulator and CDR operates over an input data range of 4kbs to 18kbs, measures 300µm by 600µm and dissi-pates 70µW from a 2.7V supply.

I. INTRODUCTION

Low power and short range wireless interfaces in long-term biocompatible neural recording implants are optimized to perform various tasks that include DC power extraction from a wireless low frequency carrier via an inductive link (~1-20MHz), reception of low data rate signals for overall system control (~1-10kb/s), and transmission of high data rate encoded neural signals to an external signal processing unit (~1-2Mbs) [1], [2]. While simultaneous operation of the implant receiver and power rectification circuits depend on the availability of a rechargeable battery, the neural recording device receiver often employs the same inductive link used for power transmission to recover data and clock for implant circuit operation. Previous integrated implementations of clock and data recovery (CDR) circuits have extracted the clock directly from the power carrier (or a sub harmonic) and the data from an amplitude shift-keyed (ASK) signal modu-lated onto the same carrier [3]. This implementation suffers from inaccurate synchronization of the clock and data sig-nals. Other approaches have employed pulse width modula-tion (PWM) signals with delay-locked loops (DLL) to re-cover and resynchronize clock and data at the expense of increased area and power overhead [4].

In this paper, we propose an integrated low power clock and data recovery circuit without DLLs. Synchronization of clock and data is achieved via a modulation scheme based on amplitude shift keying and pulse position modulation (ASK-PPM) that facilitates clock and data recovery using an ASK demodulator and a charge-pump with latched comparator [5]. The clock edge information is embedded into the modulated signal and is easily recovered using a toggle register. The

circuit is fabricated in standard 2-poly 3-Metal 0.6µm bulk CMOS technology and operates from a 2.7V battery supply, dissipates 70µW, measures 300µm by 600µm and exhibits a sensitivity of 3.2mVp-p. The circuit recovers 4kbs to 18kb/s clock/data from a 1MHz carrier.

This paper is organized as follows. In section II, we pre-sent a brief overview of the modulation scheme, followed by detail discussion of the circuit blocks. Measurement results and concluding remarks are provided in section III and IV, respectively.

II. RECEIVER DESCRIPTION

A Modulation Scheme

The signaling scheme employs ASK with modulation index of m and PPM with pulse duration TON, as shown in Fig. 1. A single bit of information is encoded into two pulses; the first pulse of the present and next bits represents the start and end of each bit from which the system clock can be easily extracted. The time between pulses encodes a “1” or a “0” – a

A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics

Hong Yu, Student Member, IEEE, Rizwan Bashirullah, Member, IEEE Department of Electrical and Computer Engineering,

University of Florida, Gainesville, FL 32611

Fig.1. Amplitude Shift-Keying (ASK) with Pulse Position Modu-lation (PPM). Comparison between ASK-PPM and standard ASK shows lower power dissipation over the range of modulation index (m) due to the low duty cycle inherent to the signaling scheme.

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1 is encoded by two pulses separated by 60% and 40% of the bit time (TB), whereas a 0 is encoded by 40% followed by 60%. This approach in comparison with a standard ASK modulator achieves lower power dissipation due to the short on-time of the pulses. Assuming equal probability of ones and zeroes (i.e. p1=0.5 and p0=0.5) and an un-modulated car-rier with average power of PAVG, the power for an ASK modulated signal can be approximated as

( )⎟⎟⎠

⎞⎜⎜⎝

⎛ −+⋅=

211 2mPP AVGASK

(1)

Similarly, the average power of an ASK-PPM signal is

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−+⋅=−

B

ON

B

ONAVGPPMASK T

TmTTPP 2112 2 (2)

From (2), decreasing TON with a modulation index m=1 can lead to nearly 50% reduction in power dissipation, as shown in Fig. 1. The drawback of this signaling scheme is the reduc-tion in maximum attainable data rate. Since four transitions are required to encode a single bit, the maximum data rate assuming 60%/40% PPM encoding is 1/5 that of a standard ASK modulator. This penalty in transmission data rate is acceptable in low frequency forward telemetry links com-monly used to update system functionality.

B ASK Demodulator

The ASK demodulator consists of an input amplifier stage with digital offset compensation, an envelope detector with full-wave rectifiers consisting of two unbalanced differential pairs [6] and an ASK detector circuit, as shown in Fig. 2. The input stage employs a source coupled amplifier with resistive feedback (RF) implemented using nMOS devices. Since the input stage is AC coupled to an external inductor antenna, this feedback serves to self-bias the input. The output load of the amplifier uses a composite load consisting of R1, C1 and a pMOS device to implement an active inductor [7]. Assuming

that the total capacitance at the output is lumped into CL, the composite half-circuit load ZL(s) can be expressed as,

( )

( )11

3

11

3112

11

311

3 1

11)(

CCRgm

CCRRRCC

ss

CCRgm

CsR

gmsZ

LL

oL

LL

+⎟⎟⎠

⎞⎜⎜⎝

⎛ +++

⋅+=

(3)

Thus, the circuit exhibits a zero at -1/R1C1 and the sum of two poles given by the second term in the denominator. Note that in order to minimize area and parasitic capacitance con-tribution, R1 is implemented using an nMOS transistor with its gate connected to the supply voltage. The dc load and gain can be approximated as 1/gm3 and ADC~-gm1/gm3 (assuming large RF). With proper choice of parameters, a low frequency zero is easily inserted to boost the gain at 1MHz and improve the overall frequency response. This frequency boosting or shunt-peaking effect helps decrease the power dissipation of the input stage. The input stage is biased at 9µA for a gain of 29dB at 1MHz. The circuit also exhibits a small dc gain to minimize the effect of transistor mismatch on DC offset. Ad-ditional binary weighted (D0-2) digital offset compensation nMOS transistors are used to trim the offsets of the input stage.

The amplified signal is directly coupled to a CMOS full-wave rectifier [6], as shown in Fig. 2. The unbalanced source coupled pairs with cross-coupled inputs (N3-N6) and parallel connected output stage (P8-P11), produces a rectified current (IREC) that is proportional to the square of the applied small signal input voltage. Assuming matched devices and transis-tor operation in saturation region, the first order terms can be canceled out. The rectified current is amplified by a factor of N using the P10-P11 current-mirror and applied to a low-pass filter (N1 and CREC) to remove the 2nd harmonic. The enve-lope voltage is level converted with one path low-pass fil-tered by RLPF and CLPF to compensate for slow varying DC offsets. The succeeding comparator stage senses the voltage difference and generates CMOS level ASK output (VASK).

Fig. 2. ASK demodulator circuit.

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An intentional offset of 10mV is introduced to set the output voltage to zero in the absence of ASK signals. The buffered CMOS level signal is applied to the following clock and data recovery block.

C Clock and Data Recovery (CDR)

The output of the ASK detector generates short pulses of duration TON that are separated by 40% or 60% of the data bit time (TB), as shown in Fig. 3a. Clock recovery is easily im-plemented using a pulse width modulation (PWM) detector based on a toggle register. Since the pulses occur at 40% or 60% of the bit-time duration, the full-rate (non-return to zero) clock edge information is readily available. The toggle FF consists of a DFF with Q and D connected by three inverters. The delay guarantees that the output toggles only to the first incoming edge to prevent any change in output state for the entire duration of the telemetry burst (i.e. TON).

An NRZ data stream is extracted from the clock signal by integrating the pulses with a charge pump and sampling the analog waveform with a latched comparator, as shown in Fig. 3b. Non-overlapping clocks are provided by the clock gen-erator module to minimize the effect of clock feedthrough in the charge pump. The charge pump provides a stable current IP that is integrated on a linear capacitor (CP) to generate VP. The voltage difference (VP-VTH) at the inputs of the latched comparator is sampled using a short pulse after the falling edge of the clock signal. The sampled state is stored in a Nand based RS-latch and resynchronized by a DFF on the following rising edge of the clock. The optimal threshold voltage is determined by VTH=0.5IPTB/CP, where 1/TB is the input data rate (fB). For any given fixed threshold voltage, the maximum theoretical variation in input data (∆fB) is less than 0.4fB (or ∆fB/fB < 0.4). That is, the input data range must be less than 40% of the nominal data rate. This provides suffi-cient margin to accommodate for process variations.

This clock recovery scheme does not provide 50% duty cycle – an acceptable constraint when used to update system control status in low power implant circuits. In addition, in the event of a single ASK pulse error, the recovered pulse-width modulated signal becomes inverted causing 100% bit errors. To resolve this, the data is encoded/decoded using a differential encoding scheme. With differential encoding, the information is encoded into the data transitions instead of the bit level, thus allowing correct data extraction even from an inverted recovered signal.

III. EXPERIMENTAL RESULTS

A prototype test chip has been fabricated in 2-poly 3-Metal 0.6µm bulk CMOS technology in order to validate circuit functionality. A custom package platform consisting of a standard printed circuit board with coil antenna and die at-tachment using chip-on-board (COB) technique was fabri-cated. All circuits are powered from a 2.7V supply and bi-ased from a single 420nA current source. Fig. 4a shows the measured voltage at the input of the ASK demodulator cir-cuit. The circuit exhibits a sensitivity of 3.2mVp-p at 1MHz and generates CMOS level pulse position modulated signals (VASK).

Fig. 4b shows the operation of the clock and data recovery circuit. An arbitrary waveform generator (Agilent 33120) provides a 1MHz carrier ASK waveform with modulation index of m=1 and pulse position modulation with data en-coded as 60%/40% for a logic “1” and 40%/60% for logic “0”. The recovered clock and non-return to zero data signals indicate correct detection of a “110” test pattern. The CDR is operational for an input data range of 4kb/s to 18kb/s – this is sufficient to support implant control and update functions from an external wireless device. The input data rate (fB) is related to the threshold voltage (VTH) and charge pump slew-rate via VTH=0.5(IP/CP)(1/fB). Since direct observation of the

(a) (b) Fig. 3. Clock and data recovery (a) waveforms and (b) circuit implementation.

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charge pump output voltage (VP) response indicates a slew-rate (IP/CP) of approximately 20.5mV/µs, the required threshold voltage range ∆VTH is ~ 0.57V to 2.56V – this is approximately the dynamic range of the sense amplifier latch when operated from a 2.7V supply.

A die micrograph is shown in Fig. 5. The envelope detec-tor and clock/data recovery circuits measure 300µm by 600µm. The measured circuit power dissipation is 70µW at 2.7V.

IV CONCLUSIONS An integrated low power clock and data recovery circuit

for implantable electronics is presented. The circuit employs a modulation scheme based on ASK and PPM with modula-tion index m=1 to facilitate clock recovery and reduce power dissipation. Instead of a DLL, the receiver employs a charge-pump based data extraction loop that yields small power and area implementation. A prototype has been fabricated in 2-poly 3-Metal 0.6µm bulk CMOS technology in order to vali-date circuit functionality. The measured sensitivity of the receiver front-end is 3.2mV p-p at 1MHz. The circuit oper-ates over an input data range of 4kbs to 18kbs, measures 300µm by 600µm and dissipates 70µW from a 2.7V supply.

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[2] K. D. Wise, D. J. Anderson, J. F. Hetke, D. R. Kipke, K. Najafi, “Wire-less Implantable Microsystems: High-Density Electronic Interfaces to the Nervous System,” IEEE Proceedings, vol. 92, no. 1, Jan. 2004.

[3] K. Najafi, H. Yu, "Low-Power Interface Circuits for Bio-Implantable Microsystems", IEEE Solid-State Circuits Conf., pp.194 - 487, vol.1, 2003.

[4] W. Liu, K. Vichienchom, S.C. DeMarco, C. Hughes, E. McGucken, M.S. Humayun, E. De Juan Jr., J.D. Weiland, and R. Greenberg, “A Neuro-Stimulus Chip with Telemetry Unit for Retinal Prosthetic De-vice," IEEE Journal of Solid State Circuits, vol. 35, no. 10, pp. 1487-1497, Oct. 2000.

[5] R. Bashirullah, W. Liu, Y. Ji, A. Kendir, M. Sivaprakasam, G. Wang, and B. Pundi, "A Smart Bi-directional Telemetry Unit for Retinal Pros-thetic Device", IEEE Proc. International Symposium Circuits and Systems, vol. 5, pp. 5-8, May 25-28, 2003.

[6] Katsuji Kimura, "A CMOS Logarithmic IF Amplifier with Unbalanced Source-Coupled Pairs", IEEE J.Solid-State Circuits vol. 28, No.1, pp. 78-83, Jan., 1993.

[7] B Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw Hill, 2001.

(a)

(b)

Fig. 4. Measured waveforms (a) ASK detector (b) clock and data recovery.

Fig. 5. Die micrograph.

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