Record power added efficiency of bipolar power transistors for low voltage wireless applications.

F. van Rijs', H.A. Visser2, P.H.C. MagnCe'

'Philips Research Laboratories Prof. Holstlaan 4, WAG12,5656 AA, Eindhoven, The Netherlands

2 . Discretes Philips Semiconductors Gerstweg 2,6534 AE, Nijmegen, The Netherlands

Abstract n+ poly

To increase the power added efficiency (PAE) of low voltage RF bipolar power transistors for cellular applications, we investigated the influence of transistor parasitics on PAE. We found that reducing the output capacitance increases the PAE due to better second harmonic tuning. By optimizing the transistor for a low output capacitance we achieved a record PAE of 71% at 0.5 Watt, 1.8 GHz and 3.5V supply voltage.

Introduction

For cellular phone applications, such as GSM, DCS1800 and CDMA, the talk-time is limited by the power amplifier, which has output powers in the range of 2W (DCS1800) up to 4W (GSM). In order to increase the talk-time it is of great importance to improve the power added efficiency of the power amplifier and in particular the efficiency of the output power transistor.

Previously we reported [ 11 a high power added efficiency of 60% at 0.5W of output power at 1.8 GHz and a low supply voltage of 3.5V with a bipolar transistor fabricated in a double poly-silicon bipolar process. However, comparable or even higher efficiencies were reported with other competing devices and technologies such as LDMOS transistors [2,3], AlGaAs HEMTs [4] and SiGe and AlGaAs HBT's 15-71. In this paper we present results, by simulation and experiment, which show an improvement in power added efficiency of more than 10% yielding a total power added efficiency of 71% at 1.8GHz at 3.5V operation. This obtained efficiency is a new record for bipolar transistors and compares favorable with other competing technologies.

Technology and measurement setup

Fig. 1 shows a schematic cross-section of the double poly- silicon bipolar technology used which has a cut-off frequency of 25 GHz, an f,, of 33 GHz and a collector-emitter breakdown voltage of 5.0 V. Standard double poly technology is used with nitride L-spacers, implanted poly- emitter and an effective emitter width of 0.4 um. Epi- thickness and collector implantation (SIC) were optimised to reach the required breakdown voltages and to reach the ruggedness voltage of 4.5 V. This voltage reflects the ability of the transistor to withstand high supply voltages under RF- power conditions during mismatch of the output. The

t n+ buried layer )

p- substrate

Fig. 1 : Cross-section of the 25 GHz double poly-silicon bipolar transistor technology.

standard power transistor with a power added efficiency of 60% has 24 emitter fingers each 26 um long (fig. 2) and delivers 0.5 W of output power at 3.5 V supply voltage and 1.8 GHz. Collector series resistance due to the buried layer is kept low by limiting the riumber of emitter fingers in one collector area by three. Fig. 3 shows the measured (markers) and simulated results (solid lines) as a function of output power. Measurements were done on a semi-automated loadpull setup with passive tuners from Maury. All devices are mounted on an A1203 co-planar substrate for large-signal characterization and are contacted by Cascade Microtech

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Fig. 2: Layout of the standard 0.5 Watt transistor with 60% power added efficiency at 1.8 GHz, 3.5V (die size: 500x500 um2).

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wafer probes. Harmonic balance simulations in MDS [8] using the MEXTRAM [9] model show good correspondence with measurements.

80

60

40

20

B

0.0 0.2 0.4 0.6 0.8 output power IWl

Fig. 3: Comparison between measured and simulated power gain and efficiency of the standard transistor. De transistor is tuned at 0.5 W (1.8 GHz,3.5V) for maximum power added efficiency.

High power added efficiency results

Using the MEXTRAM model the influence of several transistor parasitics on the power added efficiency were simulated. It was found that emitter and collector series resistances are low enough and do not degrade the efficiency.

n

8 U

L c---- simulated PAE, Rc=0.2 Ohm -

0 measured PAE 55

50rn I a I 3 a I I I I I 1 1 1 1 -

0 2 4 6 output capacitance [pF]

Fig. 5: Simulation of power added efficiency as a function of output capacitance without (solid line) and with small series losses. Markers represent the experimental results and compare good with simulations.

lossless, as it is in our case, otherwise additional loss- mechanisms come into play. Fig.5 clearly shows that to obtain higher efficiencies a low output capacitance is of vital importance. For very low output capacitance, the efficiency approaches almost the theoretical limit of 78.5% for class-AB operation.

To investigate experimentally the influence of the output

However, the output capacitance, as defined in fig. 4, is very important for high efficiency operation. Fig. 5 shows the simulated efficiency results as a function of

Rc

I

-

Fig. 4: Equivalent circuit of transistor with output capacitance (collector-substrate capacitance and emitter- collector interconnect capacitance) and contact resistance which are important for high efficiency operation.

output capacitance. The solid line is simulated without series losses and the dotted line includes the losses of a small contact resistance of 0.2 Ohm (fig. 4). A necessary condition for these results is that the output capacitance is almost

Fig. 6: Improved layout of the 0.5 Watt transistor where the interconnect capacitance is minimized and the collector- substrate capacitance is made lower by decreasing the buried layer area.(die size: 400x550 um').

capacitance several transistors were made with different collector-emitter capacitances (5.8pF, 3.6pF and 2.1pF) but with the same active transistor area. The output capacitance consists of collector-substrate capacitance and interconnect capacitance between emitter and collector metallization. A high capacitance has been made (5.8pF) using a high doped substrate (high collector-substrate capacitance) and a low

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capacitance (3.6 pF) using a low doped substrate. To further minimize the output capacitance a new layout was designed, see fig. 6, which has a much lower interconnect capacitance. With this layout an output capacitance of 2.lpF was reached.

Fig. 7 and 8 show the measured efficiency and power gain for the three devices with different output capacitances. All measurements were done at 1.8 GHz and 3.5V supply voltage on mounted devices and were tuned for highest efficiency. The power gain in fig.8 is highly dependent on the emitter inductance of the bondwires. With four bondwires used, the

0.0 0.2 0.4 0.6 0.8 output power [W]

Fig. 7: Measured powei added efficiency for three transistors with 2.1 pF, 3.6 pF and 5.8pF of output capacitance. Highest efficiency of 71% is reached for the device with 2.lpF of output capacitance, 66% for the 3.6 pF device and 60 % for the 5.8 pF transistor.

Cout

output power [W]

Fig. 9: Power adlded efficiency of the best device and tuned for highest efficiency at thre:e different output powers as indicated by the arrows (300rW, 400mW and 550mW)

inductance value is about 0.12 nH. The highest efficiency of 71% was obtained for the device with the lowest output capacitance. The other peak efficiencies are 66% and 60% for respectivelly the 3.6 pF and the 5.8 pF device. These peak efficiencies are ]plotted as markers in fig. 5 and compare very well with simulations when 0.2 Ohm losses are included. These losses can be attributeld to the A1203 substrate and the RF-probes. When measured on-wafer, the contact resistance of the RF-probes is lower and even higher efficiencies of 73% are measured for the 2.lpF device.

Figures 9 and 10 display efficiency and power gain

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5 1 . , . . 1 1 1 . . 1 . 1 . . 1 ' . ' ' J 0.0 0.2 0.4 0.6 0.8 output power [W] 0.0 0.2 0.4 0.6 0.8

output power [W] Figure 10: Power gain of the best device but tuned for highest efficiency at three different output powers (300mW, 400mW and 550mW)

Fig. 8: 2.lpF, 3.6pF and 5.8 pF of output capacitance.

Measured power gain for three transistors with

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measured on the optimum device for several tuning cases in which the load impedance was changed to shift the peak efficiency at various output powers. Up to 600mW the high efficiency can still be maintained with a small loss in gain at the peak efficiency output power as indicated by the arrows in fig. 10.

To further investigate the behaviour of the efficiency as a function of output capacitance, more simulations were performed. Since the output capacitance is considered ideal (with a high Q-factor at 1.8 GHz), this capacitance is tun d

frequency and does not change the performance. However, this capacitance can not be tuned out at the higher harmonic frequencies at the same time in the measurement setup. So the higher harmonic frequency components of the collector current are more short circuited with higher output capacitances. Especially the second harmonic component lowers the efficiency with increasing capacitance. The degradation of the efficiency can be circumvented when the capacitance at the second harmonic can be tuned out by second harmonic tuning. This can also be seen in fig. 11, where the efficiency is simulated against the phase of the second harmonic load reflection component. The magnitude

out by the output matching impedance at the fundame ,.e tal

of the load reflection component is one and thus considered ideal (no resistive part). In our measurement setup the phase is about 80 degrees but a phase of about 180 degrees would give for all output capacitances comparable high efficiencies. The higher the output capacitance, however, the smaller the range in which the second harmonic tuning is effective. For low capacitances, the efficiency is almost independent of the phase between 0 and 180 degrees and, as an advantage, does not require special matching circuitry for second harmonic tuning.

Conclusions

As a conclusion, optimizing the bipolar transistor for lower output capacitance significantly increases the PAE. An efficiency of 71% at 1.8 GHz was demonstrated.This high efficiency, in combination with low cost and straightforward impedance matching demonstrates that silicon bipolar is and will remain a viable technology for present and future cellular application.

References

(1) F. van Rijs, R. Dekker, P.H.C. Magnee, R. Vanoppen, E. v.d. Heijden, B.N. Balm and L.C. Colussi.,”High gain, high efficiency, low voltage medium power Si-bipolar transistor suitable for integration”, RFIC Symposium, Denver, pp. 15, 1997. I. Yoshida, M. Katsueda, Y. Maruyama and 1. Kohjiro, “A Highly Efficient 1.9-GHz Si High-Power MOS amplifier”, IEEE trans. ED, Vol45, No.4, pp. 953, 1998.

(3) E. Spears et al.,”Silicon RF GCMOS performance for portable communications applications”, IEEE-RFIC symposium, pp. 153, 1997.

(4) D-W Wu, R. Parkhurst, S-L Fu, J. Wei, C-Y Su, S-S Chang, D. Moy, W. Fields, P. Chye and R. Levitsky, ”A 2W, 65% PAE single-supply enhancement-mode power HEMT for 3V PCS applications”, MTT- Symposium, Denver, pp. 1319, 1997.

( 5 ) D.R. Greenberg et al.,”large-Signal performance of high-BVCEO graded epi-base SiGe HBTs at wireless frequencies”, IEDM-97, pp. 199,1997. A. Schuppen, S. Gerlach, H. Dietrich, D. Wandrei, U Seiler and U. Konig, ”1-W SiGe Power HBT’s for Mobile Communication”, IEEE

90 180 270 360 (7) Y. Matsuoka, S. Yamahata, M. Nakatsugawa, M. Maraguchi and T. Ishibashi., ”High-efficiency operation of AlGaAslGaAs power heterojunction bipolar transistors at low supply voltage”, Electronics letter, Vol. 29, pp. 982, 1993.

(2)

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(6)

5 0 - . . * 1 , * I MGWL, Vol. 6, No.9, pp. 341, 1996.

phase of second harmonic [degrees] 0

Fig. 1 1 : Simulated power added efficiency as a function of (8)

. . mblic domain since 1994. The MEXTRAM bipolar transistor model

MDS is a microwave and RF design system from Hewlett-Packard.

the phase of the second harmonic reflection component with (9) The MEXTRAM model, developed by Philips Electronics N.V. is

magnitude 1. ievel 503.2, unclassified report 006/94 CA min9-mxt @natlab.research.philips.com

be requested at

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