An Efficient Tree-Based Algorithm for Computing Path Delay Fault Coverage

Bhanu Kapoor Integrated Systems Laboratory Texas Instruments Incorporated

Dallas Texas 75243

Abstract

A new algorithm for the efficient computation of path d e l a y fault coverage fo r circuits with very large number of path delay faults has been presented. The di- rected acyclic graph representzng a combinational cir- cuit consists of a set of trees rooted at the fanout and output nodes. The algorithm uses a tree-based mark- ing process to compute the path delay fault coverage of a given delay-test set in linear time and memory. The root of a tree is marked as used only when it has been tested with respect to the rising and falling path delay faults passing through all the leaves of the tree. The al- gorithm takes advantage of large tree structures, found in most digital designs, to provide a reasonably accu- rate and very efficient method for the estimation of path delay fault coverage. Some results obtained using non-robust simulation of benchmark circuits suggest the viability and validity of our approach.

I. Introduction

At present, test generators create tests for stuck-at faults. These faults are not always the way in which a circuit fails. Circuits failures are caused by physical defect such as broken lead, bridging defects, statisti- cal variation in the manufacturing process, and more subtle failures such as gate oxide shorts. These defects sometimes manifest themselves as hard failures, which can be detected by stuck-at fault test, and sometimes as delay faults.

A delay fault is a fault that causes incorrect data to be latched into a memory element or appear a t an output. The maximum allowable path delay in a syn- chronous circuit is determined by its clock rate. If the delay on a path of a manufactured circuit exceeds the time period of the clock, erroneous values may be latched at the output. The objective of delay test- ing is ensure that the manufactured circuit operates correctly a t the functional clock rate.

0-7803-2020-4194 $4.00 0 IEEE 417

V. S. S. Nair Dept. of Computer Science & Engg.

Southern Methodist University Dallas Texas 75275

Two common delay fault models, called the gate delay fault model and the path delay fault model, have been investigated by several researchers for the tasks of test generation [5-81 and fault simulation [l-41. The path delay fault model is capable modeling distributed failures resulting due to statistical variation in the manufacturing process. As a result, it is of particu- lar importance for circuits designed using statistical timing analyzers.

One problem associated with path delay fault model is that there can be an exponential number of path delay faults in a circuit. This makes it practically impossible to enumerate all paths for the purpose of test generation and fault simulation.

The problem of path delay fault simulation has been investigated in [l-41. In order to compute the exact path delay fault coverage by a given test set, these methods have a worst case exponential complex- ity. In [l], complete set of paths is used. In [2], all delay tested paths are stored. An efficient method for path delay fault simulation of sequential circuits is presented in [4].

A non-enumerative method to compute the path delay fault coverage is presented in [3]. A polyno- mial complexity algorithm is presented where as the degree of the polynomial is increased, more accurate estimates are obtained. It has an exponential com- plexity for exact computation of path delay fault cov- erage. In this approach, the linear algorithm consists of marking an edge as used when it has been tested for a t least one rising and falling path delay fault go- ing through that edge. Once all the edges are marked used, the algorithm will not be able to account for any new path delay fault detected as a result of sim- ulation. It is easy to see that , in the worst case, all edges can be marked used after only detecting a num- ber of path delay faults which of the order of number of lines in the circuit. However, the circuit may have an exponentially large number of path delay faults.

In this paper, we present a new linear algorithm for the efficient computation of path delay fault cov- erage for circuits with a very large number of path delay faults. The directed acyclic graph (DAG) repre- senting a combinational circuit is divided into a set of trees. The algorithm uses a tree-based marking pro- cess to compute the path delay fault coverage of test set in linear time and memory. The root of a tree is marked as used only when it has been tested with respect to the rising and falling path delay faults pass- ing through all the leaves of the tree. The algorithm takes advantage of large tree structures, found in most digital designs, to provide a reasonably accurate and very efficient method for the estimation of path delay fault coverage. We describe the algorithm in Section 11. Some results obtained using non-robust simulation of benchmark circuits suggest the viability and valid- ity of our approach. This is discussed in Section 111. Section IV gives a brief summary of the paper.

11. Tree-Based Algorithm for Coverage Estimation

A combinational circuit is represented as a directed acyclic graph (DAG), where gates correspond to ver- tices and the wires correspond to edges in the graph. Fig. l(a) shows a combinational circuit which is mod- eled as a directed acyclic graph in Fig. l(b). There are two path delay faults associated with every path, one each for the rising and falling transitions. Each edge in the circuit graph is replaced by a pair of edges in the path fault graph. This is shown in Fig. l(c).

I2

Figure 1: Representation of path delay faults using a directed acyclic graph

For circuit with large number of paths, an explicit

fault representation is not practical. Efficient path manipulation algorithms are necessary for execution speed as well as to maintain manageable memory re- quirement. The DAG representing a given combina- tional circuit consists of a set of trees. A linear time path counting method involves topological sorting [9] of the trees in the DAG and then summing the number of paths going through each leaf node of a tree. The number of paths through each primary input is as- signed a value equal to 1. Topological sorting requires a depth first search traversal of the circuit, which is of linear complexity. An example of tree-representation and path counting, for the structure shown in Fig. l(b), is shown in Fig. 2. The DAG is broken up into a set of trees. The number shown along with each leaf and root node is the number of paths between that node and the set of primary input nodes.

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Figure 2: Tree-Based Representation and Tables for Marking Process

During the course of path delay fault simulation of the circuit, the algorithm needs to keep track of already tested path delay faults. For this purpose, we have used a marking process which marks the root of the tree as used only at least one of the path delay faults through each leaf of the tree has been tested with respect to both rising and falling transitions. The estimated path delay fault coverage will be pessimistic as a result.

We assign two bits, r and f > corresponding to the rising and falling path delay faults through these leaves. These bits are set to 1 only when the corre- sponding path fault through the leaf has been delay

41 8

tested. Some example tables for roots of the example tree are shown in Fig. 2.

12 12

Figure 3: Two sets of tested path delay faults

A newly tested path delay fault is added to the count of tested path delay faults if and only if it sets a t least one of the bits in one of the tables associated with the roots on the path. The computation of the number of newly tested path delay faults, as a result of an application of a delay test, is carried on in a fashion similar to the path counting mechanism, how- ever, it is restricted over the tested DAG, and uses the information of already marked bits in various tables.

An example illustrating various steps in the algo- rithm is described next. Let us assume that a pair of delay tests, when applied on the example circuit, are able to test the paths shown using bold lines in Fig. 3(a) and 3(b). Also assume that these tests propagate rising transitions. After the application of first test, the status of various tables is shown in Fig. 4.

When a new bit in one of the tables is set, this cor- responds to a newly tested sub-path. Every path delay fault, in the set of tested path delay faults, containing this sub-path is a newly tested path delay fault, and is included in the count. The counting of newly tested path delay faults is carried on over a portion of tested DAG such that each path in the sub-DAG contains a t least one newly tested sub-path. The derivation of this sub-DAG can be achieved in linear time. The trees are examined in the topologically sorted order for this purpose. If a newly tested sub-path is found then all the edges reachable from the leaf node on this sub-path are marked in a breadth-first manner. The marking process stops if an already marked edge is

:17

Figure 4: Data structures after processing the first set of tested path delay faults

encountered. This allows for a linear time sub-DAG derivation process.

For example, as a result of application of the second delay test, only a portion of tested DAG is marked as newly tested. This is shown using bold lines in Fig. 5. In this case, the number of newly tested path delay faults is 2.

This edge marking process, coupled with a linear path counting algorithm, allows for a linear algorithm for computing the path delay fault coverage of a delay test set. The algorithm is linear in both memory and time requirements. The algorithm takes advantage of large tree structures, found in most digital designs, t o provide a reasonably accurate method for the esti- mation of path delay fault coverage in a very efficient manner.

111. Experimental Results

The method described here has been implemented in Common LISP. Some comparisons of the faults counted using the algorithm presented here and the exact number of faults tested [ 101 are shown in Table 1. For each example, non-robust simulation using 10000 randomly generated test vector pairs were used. Col- umn 2 contains the number of path delay faults in each circuit. Column 3 contains the exact number of path delay faults detected by the test set. Column 4 is the number of path delay fault as determined by the algo- rithm presented in this paper. Column 5 gives CPU time in seconds for a SPARCStation 2 . As expected,

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Figure 5: Data structures after processing the second set of tested path delay faults

the coverage obtained using the algorithm presented here is pessimistic. However, the estimated coverage is reasonably accurate in most cases. This is despite the fact that the algorithm uses linear time and memory.

Table I: PATH DELAY FAULT SIMULA

Circuit sn54181 apex6 apex7 b9 des f51m rot z4ml c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

Path Faults 914

2998 1698 406

199690 348

15886 182

167852 18880 17284

8346432 1458114

13559768 57353342 2682610

1.9788320 1452988

Exact 802

1630 824 352

12574 340

1980 182

2704 3450 2198 6426 4972 2484

20172 6912

116298 7332

IV. Summary

3N RESUI

Estim. 776

1568 802 334

11056 306

1980 166

2704 3450 2178 6426 4972 2484

20172 6904

116284 7332

CPU 66

702 270 130

3600 128 650 53

183 248 408 706 588

1102 1677 2045 2679 2588

a reasonably accurate estimation of path delay fault coverage during the process of path delay fault simu- lation. Some results obtained using non-robust simu- lation of benchmark circuits suggest the viability and validity of this approach.

References

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[3] I. Pomeranz and S. M. Reddy, “ An efficient non- enumerative method to estimate path delay fault coverage ,” in Proc. ICCAD, pp. 560-56, 1992.

[4] S. Bose, P. Agrawal, and V. D. Agrawal, “Path Delay Fault Simulation of Sequential Circuits,” IEEE Trans. VLSI Systems, pp. 453-461, Dec. 1993.

[5] C. J . Lin and S. M. Reddy, “On delay fault testing in logic circuit,” IEEE Trans. Computer-Aided Design, pp. 694-703, Sept. 1987.

[6] P. C. McGeer, A. Saldhana, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Timing analysis and delay-fault test generation using path recursive fuctions,” Proc. ICCAD, , pp.

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[8] E. S. Park and M. R. Mercer, “Robust and non- robust tests for path delay faults in combinational circuits,” in Proc. Int. Test Conf., pp 1027-1034, 1987.

[9] S. Even, Graph Algorithms. Computer Science

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A linear algorithm for computing path delay fault cov- erage has been described. The algorithm exploits large tree-structures found in most digital designs to derive

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