IEEE S.F. Bay Area Council GRID Magazine · find a way to look anew at ourselves, our lives, ... • Assertion- Based Coverage-Driven Verification ... • Mixed-language and SystemVerilog

S e p t e m b e r 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1

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Upcoming Conferences

Sept 10-13: IEEE Custom Integrated Circuits Conference – DoubleTree Hotel – San Jose [more]

Sept 11-13: Measurement and Simulation of Computer and Telecommunication Systems (MASCOTS '06) – Hyatt Regency Monterey [more]

Sept 12-14: CDNLive! -- Cadence Designer Network – San Jose Convention Center/Marriott [more]

Sept 13-15: DISKCON USA 2006 – Hyatt Regency Hotel/Santa Clara Convention Center [more]

Sept 25-28: Embedded Systems Conference Boston – Hynes Convention Center/Boston [more]

Oct 1-5: Broadband Comm’ns, Networks, Systems (BroadNets) – Doubletree Hotel San Jose [more]

Oct 9-11: Fall Micoprocessor Forum: Advances in Power Efficiency - Doubletree Hotel San Jose [more]

Oct 22-27: IEEE International Test Conference (Test Week 2006) - Santa Clara Conv Center [more]

Oct 25-27: IEEE Int'l Symposium on Workload Characterization - Hilton Hotel, San Jose [more]

Nov 5-9: Int'l Conference on Computer-Aided Design (ICCAD) Double Tree Hotel, San Jose [more]

Nov 7-9: ISPCON FALL 2006 - The Internet Industry Event - Santa Clara Convention Center [more]

Nov 12-17: AVS 53rd International Exhibition and Symposium - Moscone West, S.F. [more]

September 2006CHAPTER MEETINGS

SCV-IMS - 8/30 | An Overview of the Texas Instruments MSP430 Architecture -for Test and Measurement applications ... [more]

SCV-LEOS - 9/5 | New Approaches to Projection Lighting - electrode-less lamp as a source for projection display systems ... [more]

SCV-CPMT - 9/13 | 25-Micron Flip Chip Bumping Technology: Processes and Applications - ultra-fine pitch on 50-micron centers, for applications in imaging and detection devices ... [more]

SCV-MTT - 9/14 | The Latest Update on Gb/s Wireless Communica-tions at 60GHz - recent CMOS demonstrations of capabilities for RF, microwave & millimeter wave circuits ... [more]

SCV-Mag - 9/19 | Spin Electronics - three-terminal spin transistor, spin-polarized currents, entirely new device concepts ... [more]

SCV-EMB - 9/20 | Micromachined Transducers for Medical Ultra-sound Imaging and Therapy - modes of operation, two technologies for making them, and integration of electronics ... [more]

OEB-IAS - 9/21 | Tour of USS-POSCO Industries - producing cold rolled sheet, galvanized sheet, and tin plate ... [more]

SCV-SSC - 9/21 | Application of Carbon Nanofibers for On-chip Interconnect Applications - electrical characteristics of vertically aligned carbon nanofiber (CNF) arrays ... [more]

SCV-CE - 9/26 | Advanced Digital Cable Architectures and Tech-nologies - for better services, more competitition ... [more]

SF-IAS - 9/26 | Conductors for Wiring - 600-volt insulating materials, products, selection parameter, and new products developments ... [more]

SCV-CPMT - 9/28 | 3-D and Multi-Technology Packaging: Current Capabilities - new assembly technologies for multi-component stacked-die IC packaging ... [more]

SCV-LEOS - 10/3 | The Solid State Heat Capacity Laser (SSHCL) Program - transition to an operational directed-energy weapon ... [more]

SCV-CPMT - 10/11 | Convergence Challenges of Photonics with Electronics - low cost requirements and CMOS compatibility ... [more]

SCV-MTT - 10/12 | Microwave High Power Amplifier Design and Testing - for radars, radios, base stations and cell phones ... [more]

SCV-Mag - 10/17 | Recollections of the Early History of Video Tape Recording - the Ampex team that developed the world’s first practical, economically successful video tape recorder ... [more]

SCV-Nano - 10/17 | Status of Nanotechnology Initiatives at the University, State, & Federal Levels - a myriad of initiatives experiencing various levels of success ... [more]

SF-PES - 10/17 | Fall Banquet - Michael Peevey, President, California Public Utilities Commission - issues facing the electric industry … [more]

SCV-CE - 10/24 | HANA: the High-definition AV Network Alliance - connectivity between AV devices via IEEE-1394 ... [more]

Chapter One-Day Tutorials and Seminars:

Broadband/RF Circuit Design in CMOS Technology September 9, at Cadence Design, San Jose [more]

Electronics Cooling - Theory and Applications Sept. 13, at Keypoint Credit Union, Santa Clara [more]

Seminar: The World with RFID October 14, at the Biltmore Hotel, Santa Clara [more]

Support our advertisers

MARKETPLACE – Services page 3 Volunteers Needed: for our schools (K-12) page 6

http://www.ewh.ieee.org/r6/scv/ce/


Your Networking Partner ®

September 2006 • Volume 53 • Number 9

IEEE-SFBAC ©2006

IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition

residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.

Editor: Paul Wesling IEEE GRID 12250 Saraglen Dr. Saratoga CA 95070 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net

From the editor . . .

Most of us are very focused on the things that matter to us – our jobs, our family, our community, etc. In this fast-paced world, we sometimes struggle to keep up with everything that’s needed for us to cont inue to be relevant in our careers. After a few years of this (or perhaps decades?) i t may be that al l we see is the Herculean efforts required.

But once in a whi le each of us f inds the opportunity to change our point of focus – to f ind a way to look anew at ourselves, our l ives, our careers. For me, there have been two types of events that al lowed me to re-focus: several sabbaticals, and my annual backpacking tr ip into the Sierras.

Tandem Computers, during the 17 years I was there, had a program where every four years each employee received 6 weeks off . We could add vacation to this, but we were not al lowed to take fewer than 6 consecutive weeks. I remember one tr ip to Europe and another to New England. And yes, when I came back to work, many things seemed fresher. I also noticed this with others who’d leave for two months, then return recharged.

Two weeks ago I led a backpack tr ip through Piute Pass (west of Bishop) into John Muir’s favori te high country, camping at Marion Lake for 5 days. My wife caught several golden trout in the Golden Trout Lakes, on a dayhike. Our group sat around the campfire in the evening singing songs (I brought my backpacker guitar). Watching the sun set over the lake at 11,000’ and sleeping under the stars is a great way to refresh the mind!

I t rust that you have a way to step back and regain focus, and that you take the t ime – every once in a whi le – to do i t .

Paul Wesl ing, Editor [email protected]

NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net

DIRECTORS

Santa Clara Valley Lee Colby

Fred Jones

Oakland East Bay Alan Meyer Bill DeHope

San Francisco Dan Sparks Julian Ajello

OFFICERS Chair: Fred Jones

Secretary: Alan Meyer Treasurer: Dan Sparks

IEEE-SFBAC PO Box 2110

Cupertino, CA 95015-2110

IEEE GRID


Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835

Bernie Siegal

650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures

Do you provide a service? Would you like more inquiries?

• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available

Visit our Marketplace (page 3)

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• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

[email protected] www.ozeninc.com

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MET Laboratories

EMC – Product Safety

US & Canada

• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

Facilities in Union City and Santa Clara

www.metlabs.com [email protected] 510-489-6300

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RF and Wireless Product Design & Development

- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

Redwood City (650) 369-0575

Digital Chip Design Services

ASIC Design • EDA Evaluation • Verilog HDL • Synthesis • Design for Visibility • Timing • Scan • Verification • Low Power techniques • Power Analysis • BIST • DFT • ATPG • Silicon Debug

Testable logic for high-volume production with low DPM

Contact Mahesh Siddappa ME (CS, India), MS (EE, SUNY at Stony Brook)

[email protected] 408-981-6612

VOICE COIL MOTORS Design - Control - Fabricate - Test

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San Jose, CA 95125

[email protected] (408) 269-7044 (408) 206-3049 cell

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http://www.ozeninc.com/


http://www.File-EE-Patents.com/

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CDNLive! 2006

September 12-14 in San Jose – Register Today CDNLive! is a technical conference that brings electronics designers and engineers using Cadence technologies and services together for face-to-face interactions. Cadence Designer Network, the worldwide organization of Cadence customers, and Cadence are sponsoring the three-day event in Silicon Valley.

Sessions: (Complete session details at cdnlive.com ) Functional verification Track: • Functional Verification Roadmap • Formal Analysis of Padring Mux-Logic Using IFV • Assertion- Based Coverage-Driven Verification • Verification Plan Reuse • Configuration- Based Verification Environment • Mixed-language and SystemVerilog Verification of ARM Processor-based Systems

Digital IC Design and Implementation Track: • Digital IC Roadmap • Synthesis Flow for Timing Closure in Place/Route • Handling Design Variability • Sequential Logic Synthesis with Retiming in Encounter RTL Compiler • True Hierarchical Floorplanning on the Encounter Platform • Facilitating Low Power Scan Test • Formal and Structural Analysis of Power Management Designs • Power Shut Off Design Verification with IUS Simulator

© 2006 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks and the CDNLive! logo is a trademark of Cadence Design Systems, Inc. CDN728 07/06

October 9-11, 2006 DoubleTree Hotel, San Jose

The Fall Microprocessor Forum provides concentrated insights about trends and architectures needed by designers and technical business people, accompanied by technical background and design considerations. Leading organizations present their PC processors, server processors, low-power embedded processors, consumer embedded, imaging DSPs, and on challenges of advanced semiconductor design. Presenters from multiple companies will compete for your attention via technical presentations – no marketing allowed.

Technical Sessions: • New Server Architectures (FJ SPARC64, IBM Power6, Sun Niagara2, more) • Processor Cores (RISC-free VoIP, PAC, FPGA-based) • Multicores for Embedded Applications (TeraOPS, gCORE16, Sensor-Processor, OCTEON CN48xx, SH-X3) • Multimedia at the HW-SW Interface (Embedded Audio, MSCB144 DSP, OpenGL Mobile GPU Core, Media Processor) - and more

Sponsors: IBM, Sun, VIA Exhibitors: ARM, CEVA, Green Hills, OCP, Obsidian, Tensilica, VaST, and others

Early Registration: September 8, 2006 SAVE $100

Custom IC Design/Simulation Track: • Custom ICRoadmap • An SOC Foundry Test Chip & Generic Design System Proof Point • A Top-Down Design Methodology for Mixed-Signal ICs • Substrate Noise Analysis

SPB Physical PCB Co-Design Track: • SPB Roadmap • An Advanced Fabrication Array Utility • Allegro DFA Tool Reduces Design Cycles • Design for Assembly Analysis in Allegro PCB Editor • Design Reuse for Performance • Large Complex BGAs

SPB Front-End Co-Design/SI Track: • Netlist Generation and Management • Rules-Driven PTF Generation and Management • Targeting Footprint Selection by Technology in the PCB Editor • Performing SSN Analysis in Early Design Stage

Plus a Special Topics Track, Keynote talks, a Networking lunch, Designer Expo, Cadence Technology Night, and 18 techtorials.

For additional details, visit: www.cadence.com/cdnlive

Questions? Email [email protected]

Monday full-day Seminar: “Maximum Performance, Minimum Power” with Max Baron, Senior Editor & Principal Analyst • Low power for mobile processors • Cooling techniques for very-high-performance engines • Presentation by Cadence on low power design tools • Presentation by Texas Instruments on low power technologies Keynote Addresses: “Energy Efficient Performance: The Next Frontier” Dr. Dileep Bhandarkar, Architect-at-Large, Digital Enterprise Group, Intel “Priorities in Energy: Optimized Processing” John Cornish, Vice President, Processors Division, ARM

Earlybird Discounts through September 8th -- save $500!

For full details, visit our website:

www.in-stat.com/FallMPF/

http://www.cadence.com/cdnlive/na/index.aspx


http://www.in-stat.com/FallMPF/


Developments in the field of vacuum technology have contributed significantly to the growth and success of the semiconductor industry in Silicon Valley. The 2006 Symposium addresses important issues in the research and development of thin films, electronic and photonic devices, biomaterials, magnetic materials and micro and nanostructures, as well as surface and interfacial issues, methods of processing, and manufacturing and vacuum technology. The conference covers a broad spectrum of cutting-edge topics that focus on physical and chemical phenomenon occurring at the interfacial regions of complex systems.

TECHNICAL SYMPOSIA: • Advanced Surface Engineering • Applied Surface Science • Biomaterial Interfaces • Electronic Materials and Processing • Magnetic Interfaces and Nanostructures • Manufacturing Science and Technology • Nanometer-Scale Science and Technology • Plasma Science and Technology • Surface Science • MEMS and NEMS • Thin Film • Vacuum Technology

TOPICAL CONFERENCES: • Energy Science & Technology • Nano-Manufacturing • Nucleic Acids at Surfaces • Ultra-Bright Light Sources

PUBLIC LECTURE: “The End of Oil: Dependence, Depletion, and Derail,” Paul Roberts, independent journalist – has written for Harper’s Magazine, The Los Angeles Times, The Washington Post, Slate, USA Today, Newsweek – author of book The End of Oil

PLENARY LECTURE: “Far-field Fluorescence Microscopy at the Macromolecular Scale”

SHORT COURSES: • Operation and Maintenance of Vacuum Pumping

Systems • Partial Pressure Analysis • Plasma Etching and RIE • Reactive Sputtering and Deposition • Sputter Deposition • UHV Design and Practices • X-ray Photoelectron Spectroscopy (XPS/ESCA)

EXHIBITION: FREE ADMISSION An extensive display of tools, equipment, services and consulting for film deposition, surface and interface measurements and analysis, materials, chemicals, and supplies, vacuum production and measurement, and related instrumentation for surface, interface and film measurements, as well as professional literature and publications.

SPECIAL SESSIONS & EVENTS: • AIP Industrial Physics Forum (IPF): Providing a “meeting

of the minds” in physics. The IPF is designed to foster the sharing of knowledge and collaboration, and is an opportunity to exchange ideas with other R&D leaders facing similar research and business challenges. The theme is ‘Nanotechnology in Society and Manufacturing’

• Biomaterials Plenary Session: Featuring three plenary lectures focusing on recent issues relating politics and science in the field of nanotoxicology (V. Colvin, Rice University), breakthrough nanofabrication innovations in novel microfluidic processing systems (H. Craighead, Cornell University), and nano-tag labeling methods for highly resolved detection, identification and analytical capabilities in complex biological systems (M. Natan, Nanoplex Technologies).

• Exhibitor Workshop: Emphasizing new techniques and/or applications in research, industrial, manufacturing or processing; technology transfer from R&D to manufacturing; Scale-up aspects and innovations in manufacturing practices; technology/economic aspects and market impact of new and innovative scientific and/or engineering technologies. The presentations will be held in a specially designated area of the Exhibit Hall.

• International Conference on Nanoimprint & Nanoimprint Technology (NNT): Offering an international platform for presentation of the latest developments related to the scientific and economic potential of NNT technology and applications. Leading groups from the United States, Asia, and Europe will discuss the ‘state of the art’ and focus on maintaining the close links between researchers, technologists and the emerging NNT industry. Further details on the program, and Abstract submission for NNT'06, are available at www.NNTconf.org

Registration Discount Deadline: October 23rd!

More Information: For more details, please access the AVS Website:

www2.avs.org/symposium/ sanfrancisco/

Short Courses – Technical Sessions – Exhibits

http://www2.avs.org/symposium/sanfrancisco/


ISPCON shines the spotlight on the "how" behind the best technologies and business opportunities of the Internet Industry. Whether you're interested in how to better optimize and secure a VoIP network, manage and grow your customer base with advanced web applications or select the proper wireless equipment, the path to any organization's profitable future goes through ISPCON.

The Fall ISPCON event centers on WHAT'S HOT in the Internet Industry and the success stories of those who are. The majority of selected sessions include case studies and real world operating knowledge and experiences.

Voice, including • Triple Play Solutions (Voice, Video, Data) • VoIP in Small, Med, Large Networks • Tech and Business Implementation Strategies • PSTN-to-IP, Megaco, MGCP, Gateways, Soft Switches, SIP, IP PBX, IP Centrex and Hosted • VoIP Solutions and Alternatives • Open Source and SOHO VoIP How-To’s

Web Hosting, including • Hosting tools and add-on features • Virtualization, Colocation, Automation and VPS • Hosting resource management • Datacenters • Authoring, CMS and End-User/Reseller Tools and Applications • Managed Services We need engineers/developers who can assist with programs from Kindergarten through 12th grade, in our local public schools. Give us a hand …. For Fall/Winter 2006

• Future City • Lego Robotics : Middle schools • Book Sorting

For Spring 2007 • Engineer's Week • Science Fair • Robotics: High schools • Career Fair: High schools

We’d appreciate your help. Contact : David Fong [email protected]

Visit our SCV K-12 Website, to see what we’re doing and how you can help:

www.ewh.ieee.org/r6/scv/k-12

ISPCON FALL 2006

November 7-9, 2006

Santa Clara Convention Center

Wireless, including • Equipment Issues, Interference, Efficiency • Community Networks, Government-funded WiFi, Pros, Cons and Strategy • Spectrum Issues, Mediation and Management • Security, Authentication & Management

Email, including • Anti Spam, Anti Virus, Anti Phishing Strategies • Encrypted Email, Securing MTAs, SARBOX • Authentication and Accountability • Capacity and Performance Management • Open Source Tools, Tips, Tricks and Resources

Emerging Trends/Opportunities, Including • Hosting IPv6 Services • Public-Private Partnerships for Municipal Broadband • Capacity and Performance Models

Earlybird rates through Sept 15th – save $100

Free Exhibits Pass through Sept 15th!

For full program and registration details, visit:

www.ispcon.com/GRDF6

Save an extra $100 with this Customer Code: GRDF6 Reduce your taxes by donating stocks or cash to support Santa Clara Valley K12 activities IEEE Foundation, Incorporated IEEE Development Office c/o Santa Clara Valley K-12 Education Fund 445 Hoes Lane PO Box 1331 Piscataway, NJ 08855-1331

Support Santa Clara Valley K12 funding activities by signing up for eScrip at www.escrip.com using our group id: (IEEE Santa Clara Valley Section K12, or Group ID# 500002476) …and register your credit cards (VISA, Macy's VISA) so that your purchases using your cards at places like Macy's, Cosentino's, Draeger's, PW Supermarkets, Whole Foods, Big 5, PepBoys, Big O Tires, OfficeMax, Carl's Jr, LeBoulanger,.will be credited towards our group.

Any questions, contact David Fong [email protected]

Opportunities for Volunteers: Engineers Needed for K-12 Programs

http://www.ispcon.com/GRDF6/



http://www.ewh.ieee.org/r6/scv/k-12/

http://www.escrip.com/


Getting More out of Test

The IEEE International Test Conference is the world's premier event dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

ITC offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including: formal paper sessions, tutorials, panel sessions, case studies, lecture and application series, commercial exhibits and presentations, and a host of ancillary professional meetings. Keynote/Invited Addresses “Managing Test, Yield, Quality, and Cost in Fabless Manufacturing Model,” Chris Malachowsky, Co-Founder, NVIDIA Fellow and Senior Vice President “The Impact of Globalization on Test and the Test Engineer,” Gregg Jordan, Sr. Director, Manufacturing Test Engineering, Cisco Systems, Inc. “On the Need for Convergence Between Design Validation and Test,” Siva Yerramilli, General Manager, Design and Technology Solutions (DTS), Intel Corporation “It's Not What You Can Make—It's What You Can Test,” W. Robert Daasch, Professor, Electrical and Computer Engineering, Portland State University

Test Week: October 22-27 Conference and Exhibition: October 24-26 Santa Clara Convention Center

Sponsors: IEEE Computer Society Test Technology TC

The Philadelphia IEEE Section

Seventeen Full-day Tutorials, including • Semiconductor Test and DFT Fundamentals • Advanced Memory Testing • GHz Interconnects—Electrical Aspects • Design for Testability for RF Circuits and Systems • Test Strategies for System-in-Package • Statistical Methods for VLSI Test, Quality and Reliability • Soft Errors: Trends, System Effects and Protection Techniques • Debugging Compression-based Tests: OPMISR, XDBIST, EDT, LBIST • Wafer Probe Test Technology • Timing Issues for Sub-100-nm Designs—Modeling to Production Three Multi-day Workshops • Design-for-Manufacturability and Yield • Current- and Defect-based Testing • Silicon Debug and Diagnosis Three days of 33 technical sessions Including Manager's Track, 7 panels, 4 lectures • Making Decisions Based on Economics • Improving Test Efficiency • RF Testing • Xtreme ATE: Solving Jitter Challenges • xJTAG X 3 • Advances in Test Data Compression • Microprocessor Test • Mixed-Signal Test Techniques (plus 25 others) World-Class Exhibits Free exhibits-only admission on Wednesday afternoon and all day Thursday (with lunch included on Thursday).

Download the full program – plan to attend Register by Sept. 25th for substantial savings!

Visit our website:

www.itctestweek.org

http://www.itctestweek.org/


MASCOTS holds its 14th annual international

meeting in the Bay Area, bringing together researchers worldwide to discuss both theoretical and practical results of significance that have not previously been published. A major focus is the experimental verification of past important modeling/simulation results and techniques. MASCOTS encourages mutual verification, not in the interest of fostering rivalry among scientists but in the interest of fostering the scientific process.

Keynote address: “Performance: Then, Now, and Upcoming” Alan Smith, University of California at Berkeley

45 papers in 15 Sessions on modeling, analysis and simulation: • Analytical Methods • Hardware Simulation • Storage Systems • Wireless Networking • Network Simulation • Network Management • Wireless and Optical Networking • Peer-to-Peer and Web Services Systems • Operating Systems IEEE SCV-CAS TUTORIAL

Broadband and RF Circuit Analysis and Design

in CMOS Technology

Saturday Sept 9, 2006 – 8:30 AM – 1:00 PM

at Cadence Design Systems – Bldg 5 2655 Seely Ave, San Jose

The purpose of th is three-hour tu tor ial is to

famil iar ize engineer ing professionals with both classic and innovat ive new broadbanding techniques for CMOS technology amplif iers appropr iate for s ta te-of- the-ar t communicat ion system appl icat ions. A unif ied circui t broadbanding s tra tegy is propounded, as is a pract ical methodology for the monoli th ic real izat ion of narrowband radio frequency (RF) amplif iers . All theoret ic and conceptual d isclosures are ver if ied through the resul ts of real is t ic SPICE simulat ions.

Examples of presentations at MASCOTS 2006: • Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior • A Fluid-Diffusive Approach for Modelling P2P Systems • Using Site-Level Modeling to Evaluate the Performance of Parallel System Schedulers • Disk Array Data Layout Tolerating Multiple Failures • A Statistical Traffic Model for On-Chip Interconnection Networks • Modeling a New Class of Non-Iterative Bounds for Closed Queueing Networks • Sluggish Calendar Queues for Network Simulation • A Longitudinal Study of P2P Traffic Classification • Quasi-Dynamic Network Model Partition Method for Accelerating Parallel Network Simulation • Analysis of Resource Sharing and Cache Management in Scalable Video-on-Demand • An Architecture for Distributed Real-Time Passive Network Measurement • Resilience in Overlay Multicast Protocols

Special rates for IEEE/ACM members and for Students

Visit our website: www.cs.ucsc.edu/mascots06/

Instructor: Dr. John Choma, Fellow, Scintera Networks, and Professor of EE & Systems Architecture Engineering, Univ of Southern California

Tutorial Outline: • Overview of MOS Transistor Modeling • Noise Sources In NMOS and PMOS Devices • Broadband Architectures • Magnitude Response • Lossless Filters • Linearity Considerations

A CD of all lecture material and related notes will be provided to all attendees.

Registration: 8:30 – 9:00 AM (includes breakfast) Sponsored lunch: 12:15 – 1:00 PM

Registration Fee: IEEE Member $40 Non-Member $50

Registration Deadline Sept 5 (postmarked by Sept 2) After Sept 5 – if Space Available, $5.00 Surcharge See fu l l Tutor ial Descr ip t ion for prerequisi tes and other detai ls :

www.e-grid.net/docs/0609-scv-cas.pdf

14th Annual IEEE/ACM International Symposium on

Modeling, Analysis, and Simulation of

Computer and Telecommunication Systems (MASCOTS)

September 11-13, 2006 Hyatt Regency Hotel in Monterey

http://www.cs.ucsc.edu/mascots06/

http://www.e-grid.net/docs/0609-scv-cas.pdf


IEEE/CPMT Chapter – Technical Course

Electronics Cooling - Theory and Applications

Wednesday Sept 13 – 10:15 AM - 5:30 PM

At Keypoint Credit Union Community Room 2805 Bowers Ave (near Walsh), Santa Clara Course Objectives: • To introduce electronics cool ing to the

part ic ipant and highl ight i ts sal ient points • To cover fundamental physical concepts for

solv ing electronics thermal problems • To establ ish a foundat ion from which

solut ions can be developed To provide the part ic ipants wi th solut ions to

speci f ic thermal problems in electronics cool ing

Who Should Attend: Packaging engineers , system engineers, thermal and mechanical engineers , design, process , fa i lure analysis , and rel iabi l i ty engineers .

October 25-27, 2006

Hilton Hotel San Jose

(Immediately following ASPLOS XII at same venue) IISWC is dedicated to the understanding and characterization of workloads which run on all types of computer systems. New applications and programming paradigms continue to emerge as the use of computers becomes more widespread and more sophisticated. Improving process and communication technology, innovations in microarchitecture, compilers, and virtual-machine technology are also changing the nature of problems that are being solved by computing systems. Whether they are PDAs at the low end or massively parallel systems at the high end, the design of tomorrow’s computing machines can be significantly improved through the knowledge and ability to simulate the workload expected to run on them. We invite you to attend IISWC this year to participate in these advancements.

First time in Silicon Valley! Instructor: Dr. Kaveh Azar is the president, CEO and founder of Advanced Thermal Solutions, Inc. (ATS), a leading engineering and manufacturing company focused on the thermal management of electronics. Prior to ATS, Dr. Azar was the founder and manager of Lucent Technologies' Thermal Management Center, responsible for developing next-generation cooling systems. He authored Lucent's thermal roadmap and served as the corporate thermal consultant. He is Editor-in-Chief of Electronics Cooling Magazine. Earlybird rates through Sept. 8th: IEEE Members: $125; Non-Members: $160 For detailed class outline and registration form, please

visit our website:

www.cpmt.org/scv/ Further Information: Contact Farhad Akhavan, [email protected] 408-750-3407 SESSIONS (preliminary) • Benchmark Construction and Evaluation • Characterization and Analysis of Bioinformatics Workload • Characterization of Multimedia and Games Workload • Energy and Power Behavior of Applications • Understanding Java Workload • Characterization of Scientific Workload • Novel Insights and Techniques • New Benchmarks

TUTORIALS AM: “Software Performance Tuning with the Apple CHUD

Tools,” Rick Altherr, Ryan Du Bois, Lance Hammond, and Eric Miller

PM: “Building Workload Characterization Tools with Valgrind,” Nicholas Nethercote, Robert Walsh

BENCHMARKS WORKSHOP Selected benchmarks, with authors presenting their programs and input data sets. Scheduled: • DFS: A Simple Yet Difficult Benchmark for Conventional Architectures • Clustering Application Benchmark • NU-MineBench

Advanced Registration Deadline: Wednesday, October 11

For further information, and to register:

www.iiswc.org

2006 IEEE International Symposiumon Workload Characterization

http://www.cpmt.org/scv/courses/cooling-theory.html

http://www.iiswc.org/


San Jose Doubletree Hotel

2050 Gateway Place (adjacent to the Airport) BROADNETS 2006 is an international conference focusing on broadband communications, networks and systems, and covers the entire gamut of next-generation networks, communications systems, applications and services. The conference consists of the following three symposia: Wireless Communications, Networks and Systems Symposium: covers mobility, routing for multihop, multimedia QoS and traffic management, cross-layer optimization, MAC and emerging physical layer technologies (UWB, MIMO) for high-speed wireless networking. Sessions: • MAC • Multi-hop Networks • Wireless Sensor Networks • Handoffs/Adaptive Association/QoS • Wireless TCP • Cross-Layer/PHY Optical Communications, Networks and Systems Symposium: covers WDM technologies, Ethernet and MPLS integration into the optical layer, Next-Generation SONET/SDH, as well as SAN extensions over DWDM/SONET/SDH, Optical and WDM communication systems and cross-layer design. Sessions: • Optical Network Survivability • Optical Burst Switching • Modeling of Optical Networks and Systems • Distributed Computing over Overlaid Optical Networks • Traffic Grooming and Processing • Optical Network Operation and Management • Optical Network Design General Symposium: covers theory and algorithms of networking such as routing, congestion control, traffic engineering, peer-to-peer/overlay and security; architectures and protocols such as VPLS, SIP and IMS; and applications and services such as L2/L3 VPNs, VoIP, IPTV, content services and location-based services. Sessions: • Multicast and Multihop • Routing and Traffic Engineering • Performance Evaluation and Measurement • Next-Generation Internet Architecture and Services • Congestion Control and Network Reliability

Sponsored by SUNDAY October 1st Broadband Advanced Sensor Networks Workshop Grid Networks Workshop MONDAY October 2nd Guaranteed Optical Service Provisioning Workshop Optical Burst Switching Workshop TUESDAY-THURSDAY, Oct 3rd-5th Main Conference

Organizing Committee Co-Chairs: Dr. Suresh Subramaniam, George Washington University, and Dr. Mario Freire,

University of Beira Interior, Portugal

Wireless Symposium Program Co-Chairs Dr. Aura Ganz, University of Massachusetts, and

Dr. Ragupathy Sivakumar, Georgia Tech

Optical Symposium Program Co-Chairs Dr. Byrav Ramamurthy, University of Nebraska –

Lincoln, and Dr. Ahmed Kamal, Iowa State University

General Symposium Program Co-Chairs Dr. Indra Widjaja, Bell Labs, and Dr. Hagen

Woesner, Create-Net, Italy

Registration is now Open

• Earlybird registration thru September 1st (save $100!) • Special rates for full-time students • Full-conference registrants save on one- or two-day

workshop registration Visit www.e-grid.net/conf/broadnets

for full details

http://www.e-grid.net/conf/broadnets/


ICCAD focuses on the pressing problems of

today's IC designs, such as power and variability, as well as the challenges of future technologies. The program addresses both physical design and system-level issues, and has special sessions for designers and for non-CMOS technologies. ICCAD 2006 offers an ideal place for all to meet and exchange ideas about the challenges and solutions for the future as we move into the era of nanoscale integrated circuits. Both professionals and researchers active in EDA as well as practicing designers will benefit from the knowledge provided in both regular paper sessions and selected embedded tutorials.

Keynote Talks: “An Industry in Transition: Opportunities and Challenges in Next-Generation Microprocessor Design,” Phil Hester, Chief Technology Officer, AMD “Innovation in Electronic Design Automation,” Leon Stok, Director of CAD, IBM Forty Technical Sessions: Particularly noteworthy this year is the technical track on system design issues, which runs the entire length of the conference and covers issues on power and performance optimization at the system-level; thermal and variability issues in architectures; and energy minimization in realtime embedded systems. Plus sessions on physical design, placement, routing and interconnect. The Designer’s Perspectives: an all-day event of three sessions focused on linking design technology and EDA research. We have invited over 15 IC designers to share their experiences in designing for reliability and robustness; to ensure logic, functional, and system verification; and in mixed-signal design. Nano Day: ICCAD has expanded its focus to include innovative research on design, modeling, simulation, analysis, synthesis and testing of nanoscale electronic devices, circuits and systems. Two regular sessions and two embedded tutorials are dedicated to nanotechnologies.

Sponsored by:

In cooperation with:

Sunday Workshop: “Design/Technology Convergence” Four experts from industry and academia cover the theme of convergence and interaction between traditionally disparate domains in IC design and technology. Six High-caliber, Half-day Tutorials: • Enabling Variability-Aware Analysis • DFM: Impact of Manufacturing Reality on Design • Power and Thermal Challenges for 65 nm and Below • Enhancing Yield at 45nm: DFM Solutions from Different Perspectives • Transistor, Cell, and Interconnect Modeling: Basics to Advanced • Advanced Routing Techniques for Nanometer IC Designs

Plus embedded tutorials: • Challenges in Designing and Mapping Algorithms to Multi-Core Systems • UML and SystemC for Industrial ESL Design • From Dual to Multi to Many Core: Opportunities and Challenges • Design and CAD Challenges in 45nm CMOS and Beyond • Automation in Mixed-Signal Design • Emerging Nanoelectronics • Integrating Nanoelectronics, Biotechnology and MEMS/NEMS

Technology Fair: Key CAD/EDA vendors will be displaying their products and be available to answer questions. on Tuesday November 7 from 10 AM-6 PM. The forum is beneficial to ICCAD attendees for stimulating new contacts, ranging from fruitful research collaborations to networking for the future. Check out current products and technologies, as well as those just around the corner. Display space still available: contact Amy Shaklee for details: 303-530-4562, [email protected]. Substantial savings for registration by October 18th

Can’t attend the full conference? Sign up separately for the Sunday Workshop and/or Thursday Tutorials.

See the website for more details:

www.iccad.com

http://www.iccad.com/



Visit www.embedded.com/esc/boston

The Embedded Systems Conference Boston brings together the East Coast's systems design community for eye to eye communication on real-world solutions. The event delivers real-time embedded advice from experienced industry experts in 82 classes and full-day tutorials, exhibitors across the embedded industry with the tools you need, and solution-swapping opportunities with your peers in discussion groups. Experience live "teardowns" of products and get involved in the technology debate with Get-to-the-Point Panels on the exhibits floor. Get free product training in the Sponsored Sessions and Seminars.

Keynote Talk: Improbable Research and the Ig Nobel Prizes Marc Abrahams

Industry Address: The Embedded Revolution Joe Jensen, Intel Corporation

Product Exhibition See the latest hardware, software, and development tool solutions from leading vendors in the electronics industry. Watch product demonstrations and hear about new product launches. Speak to product experts, compare products side-by-side and share experiences with your peers. Hear first-hand about tomorrow's technology today. Come to the Disruption Zone on the Exhibits Floor and see new products from innovative start-up companies who are changing the face of embedded design and disrupting the status quo. FREE MSP430 eZ430-F2013 USB Development tool!

by Texas Instruments The eZ430-F2013 is a complete MSP430 develop-ment tool including all the hardware and software to evaluate the MSP430F2013 and develop a complete project in a convenient USB stick form factor. It uses the IAR Embedded Workbench Integrated Development Environment to provide full emulation with the option of designing with a stand-alone system or detaching the removable target board to integrate into an existing design. The USB port provides enough power to operate it. The development tool can be picked up onsite and will not be shipped in advance. Limited to conference attendees, Exhibits Plus Pass attendees, and the first 1200 exhibits attendees onsite.

ESC Tracks. The Future Starts Now.

DSP Track: Signal processing gets more popular (and mandatory) every year but confusion still surrounds this segment of the developer's world. See and hear what DSP programming is all about. Eclipse Track: The Embedded Systems Design survey showed that development tools are the #1 concern for most programmers. Eclipse seems to be the IDE of choice but where is Eclipse heading and what are its alternatives? Hardware Track: There's no embedded system without processors and support logic. These classes cover hardware-related issues of RFI, PCB layout, and subjects that are "close to the metal." Java Track: After its initial flash in the pan, Java is settling down to a supporting role in many embedded systems. Where does it work, what can it do, what do you need to know? These classes lay it out. Linux & Open Source Track: Open-source software has replaced "roll your own" operating systems across the board. Explore the technical issues, support questions, for Linux and more. Safety & Security Track: It's not so easy any more: embedded devices need to prevent unauthorized use as much as they need to enable intended uses. It's a two-sided challenge to create a device that does only what it's supposed to do. UML/SysML Track: Are modeling languages for you? You'll never know until you learn enough about them to make an informed judgment. Listen to the experts talk pro and con. Up-to-the-Minute Design Solutions Track: Engineers tell us they find solutions at our event that they didn't know they needed. To help you find the newest solutions, we've added this track featuring the latest technology topics and design information— so current that we will email attendees about topics as they are added. One class from the Up to the Minute Design Solutions Track will be offered during each 90-minute class timeslot.

Monday Tutorials • Architectural Design of Device Drivers • DSP Demystified • Embedded Linux Jumpstart • Java Jumpstart • Crafting Embedded Systems in C++ • Managing Embedded Projects • Programming Embedded Systems in C • Real-Time Kernels

Flexible Registration Packages • 1-day, 3-day, or the All-Access Pass value • Group rates – bring your team (save up to 35%) • Free no-hassle parking – Free WiFi Visit www.embedded.com/esc/boston/

Use Priority Code UX20

for full details

http://www.e-grid.net/conf/escb06.html


The IEEE Custom Integrated Circuits Conference is the premier event devoted to IC development, showcasing original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference for finding out how to solve design problems and improve circuit design and design techniques.

The technical program features new, state-of-the-art developments – 141 papers and 54 posters addressing a broad range of circuits, applications, design techniques, tools, test and reliability, and system-on-a-chip.

Technical Program Highlights • PLLs and DLLs • Oscillators • High Speed Analog • D/A, Delta-Sigma Converters • Advanced Memories • Signal and Data Processing • Programmable Devices • Wireless Transmitter Building Blocks • Clocking and Data Recovery • Power Optimized SOCs • Measurement/Verification Techniques • Developments and Fabrication Challenges • Productivity Enhancement and Design Optimization … and more

DISKCON USA 2006 September 13-15

Hyatt Regency Hotel/ Santa Clara Convention Center

Sept. 12-14 – Technical Conference and Exhibits Sept 15 – IDEMA Standards Workshops

The hard disk drive is celebrating its 50th anniversary and the

future has never been brighter for the disk drive industry. The industry is expected to ship as many drives in the next five years as it did in the last 50 years. Industry analysts such as Gartner, IDC and TrendFOCUS continue to forecast impressive unit and revenue growth for the global HDD market.

Today, the word “storage” is nearly synonymous with magnetic hard disk drives. This technology has given the world a robust storage capability unmatched in price, capacity and performance. But this industry is not resting on its accomplishments, significant as they may be. Instead, plans and strategies are in place to address storage of the future and how magnetic hard disk drives may evolve to meet new user requirements. DISKCON USA addresses the business and technology aspects of our industry: its past accomplishments, its future potential and how these could be implemented via a technology roadmap.

Presented by IDEMA

Education Sessions on September 10 A valuable opportunity to refresh key skills in traditional circuit-design methods and acquire knowledge in vital new areas.

Track 1 Integrated Phase-Locked Systems • Fractional-N PLLs for Frequency Synthesis • Mixed-Signal Approaches for PLL Design/Implementation • Noise Properties of VCOs in PLLs • Device and Circuit Modeling for Phase-Locked Systems

Track 2: Advanced RF Design Techniques • Circuit Design for Impulse and MB-OFDM UWB • CMOS Building Blocks for Emerging RF Technologies • Power Amplifier Design Techniques • Technology-Aware ESD-Reliable RF CMOS Design

Track 3: High Performance/Low Power Design • Technologies for Energy-Efficient DSP Design • Clockless Circuits for Analog and RF • Ultra Low Power/Voltage Design • Variability: A Barrier to Further CMOS Scaling?

Exhibit Hours: Mon. 3:00 - 7:00 pm, Tues 3:00 - 7:00 pm

For full information and registration details:

www.ieee-cicc.org

September 13: Keynote Dinner Disk - the Past, the Present and the Future Fred Moore, Futurist and Founder of Horison Information Strategies. The evolving role of hard disk drives in the overall storage industry including a look at future architectures, technology advancements and growth opportunities. Sessions: • Executive Presentations (Seagate, Western Digital, Veeco, Komag, Xyratex) • HDD Technology and its Future • Retrospect of HDD Industry and Future Business Directions • Highlights from Intermag 2006 • HDD Applications, Integration and Evolution: Users Speak Out • The Hybrid Landscape: Opportunity and Challenge

Deadline to enter the IPOD drawing: July 31st!

Register at www.idema.org or call 408.991.9430.

Exhibit at DISKCON USA 2006 – contact Paul Moschella at 781-769-8950

September 10 - 13, 2006 DoubleTree Hotel – San Jose

Showcase for circuit design in the heart of Silicon Valley

http://www.ieee-cicc.org/

http://www.idema.org/_smartsite/modules/news/show_news.php?cmd=display&news_id=1287


An Overview of the Texas Instruments MSP430

Architecture Speaker: TI Field Applications Engineer Time: 7:30 PM Pizza and drinks, 8:00 PM

presentation Cost: none ($1 donation suggested) Place: Cogswell College Board Room, 1175

Bordeaux Drive, Sunnyvale RSVP: to David Rivkin, [email protected] Web: http://www.ewh.ieee.org/r6/scv/ims

An overview of the MSP430 architecture will be provided with a focus on how each family fits into Test and Measurement applications.

WEDNESDAY August 30SCV Instrumentation and Measurement

Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835


New Approaches to Projection Lighting

Speaker: Tony McGettigan, CEO, Luxim Corp. Time: 7:00 PM Pizza and drinks,

8:00 PM presentation Cost: none Place: National Semiconductor Credit Union

Auditorium, 955 Kifer Rd., Sunnyvale RSVP: to [email protected] Web: www.ieee.org/scv/leos

Tony McGettigan is President and Chief Executive Officer of Luxim, Corp. Mr. McGettigan joined Luxim in Oct/2004. He has over 15 years experience in consumer electronics holding leadership positions in Manufacturing, Product Development, Business Development and Business Unit Management.

Mr. McGettigan spent his last 7 years working in the Projection Display business at Optical Coating Laboratory Inc. and Hewlett-Packard. He is a prominent figure in the Projection Display industry and is a recognized leader in both the technology and commercial aspects of the industry. Prior to working in Projection Display, Tony worked in the Inkjet Printing business at Hewlett-Packard where he helped transition the technology from desktop printing to digital photography.

Mr. McGettigan received his MSME and MBA from Massachusetts Institute of Technology where he graduated with full fellowship. He received his BSME (Summa Cum Laude) from University College Dublin.

High Intensity Discharge lamps have been

successful in applications where high brightness and/or high luminous efficiency is required. Examples include sodium lamps for street lighting, metal halide lamps for industrial and stage lighting, Xenon lamps for cinema projectors and high pressure mercury lamps for microdisplay projection systems. Despite their success, these lamps are notorious for their life and reliability issues.

The presentation will describe the fundamentals of high intensity discharge lamps and the challenges associated with designing these lamps for high brightness, long life applications. The presentation will go on to introduce Luxim’s LiFi™ technology and show how LiFi addresses the stability and lifetime issues associated with conventional HID lamps. In introducing the technology, the key characteristics and elegant simplicity of the technology will be explained. Other benefits of LiFi will be covered including time to brightness, restrike time and luminous efficiency.

TUESDAY September 5

SCV Lasers and Electro Optics

MET Laboratories

EMC – Product Safety

US & Canada

• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

Facilities in Union City and Santa Clara

www.metlabs.com [email protected] 510-489-6300


25-Micron Flip-Chip Bumping Technology:

Processes and Applications Speaker: Alan Huffman, Center for Material and

Electronic Technologies, RTI International Time: 6:30 PM dinner (optional);

7:30 PM Presentation Cost: Dinner is $25 (use our PayPal system); no

cost for presentation Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road, near Lawrence Expy), Sunnyvale

RSVP: Either through PayPal, or to Janis Karklins, [email protected]

Web: www.cpmt.org/scv Alan Huffman is a Research Engineer with the Center for Material and Electronic Technologies at RTI International in Research Triangle Park, North Carolina. After receiving the B.S. degree in Physics from the University of North Carolina at Chapel Hill in 1994, he joined the advanced packaging group at MCNC (RTP, NC) and was part of the research team that developed the flip chip technology that ultimately led to the formation of Unitive Electronics in the late 1990's. Since then, his primary interest has been in the development and application of fine pitch, large area array bumping and interconnect technologies for high energy physics detector applications, next-generation imaging devices, 3D integration, and MEMS. In March 2005, RTI International acquired the MCNC research divisions. He has authored and co-authored several publications and presentations on advanced packaging technologies, particularly in the area of fine pitch bumping. Alan is a member of IMAPS, IEEE CPMT, and serves on the Electronic Components and Technology Conference (ECTC) Interconnections committee.

Flip chip has become a mainstream packaging technology in the past 5 years. The continuing trend in microelectronics for smaller, faster, lighter, and cheaper products translates into flip chip technology continuing to push toward smaller bump sizes and I/O pitches. While most flip chip applications fall within the realm of geometries considered to be chip scale packages (200 micron bump diameters and larger), there are applications that require bump sizes and pitches that are far smaller than typical applications. Bumping technology that enables 25 micron bumps on a 50 micron pitch have been developed and perfected and have been finding niche applications in a number of imaging and detection devices for a number of years. In this presentation, we will discuss fine pitch flip chip technology, the differences between fine pitch and conventional pitch processes, applications that are using fine pitch flip chip, assembly of fine pitch flip chip devices, and where this technology is headed.

WEDNESDAY September 13SCV Components, Packaging and Manufacturing Technology







The Latest Update on Gb/s Wireless Communications

at 60GHz Speaker: Alan Huffman, Center for Material and

Electronic Technologies, RTI International Time: 6:00 - Refreshments and Social,

6:30 PM - Presentation Cost: none Place: National Semiconductor, Bldg #9,

Classroom #4, 2900 Semiconductor Dr., Santa Clara

RSVP: not required Web: www.mtt-scv.org

Luiz M. Franca-Neto earned his Electronic Engineering degree, with distinction, from ITA/CTA, SJC, Sao Paulo, Brazil, in 1989, and he received the TASA award for being first in class in communications. He received his M.Sc. and Ph.D. degrees from Stanford University, all in Electrical Engineering, in 1995 and 1999, respectively. From 1990 to 1992, he was a design engineer with ALCATEL/Elebra Telecom for public telecommunications and optical line terminal equipment. In USA from 1993-1996, he has worked for HP-Labs, Palo Alto, CA, and Texas Instruments, Dallas, TX. He was with Intel R&D Labs from 1999-2004, where he led research on CMOS for RF/Microwave/Millimeter wave frequencies. He created new circuit design methods such as "backing off" for LNAs and "optimum pump" for VCOs with demonstrated circuits operating from 2.4 GHz to 100 GHz (a world record for CMOS). He led the investigations for substrate noise in Pentium 4 processors and deep n-well isolation where he articulated how substrate noise spectrum structure can be exploited for full integration of digital processors and RF delicate circuits in the same die. Also in the labs, Luiz led the research to move all RF passives from the die to the substrate package in order to realize higher performance RF System-on-Package and free silicon area for hosting more digital functions and general-purpose processors. Since February 2004, Luiz has led the WiMAX RF & Analog IC internal development within the ICG/BWD group in Santa Clara.

This paper reviews recent CMOS demonstrations

of capabilities for Radio Frequency (RF), microwave & millimeter wave circuits for 60GHz ISM bands. More specifically, the focus is on the various RF challenges that exist and how such challenges can translate into circuit designs. Circuit design techniques are discussed to cope with intrinsic CMOS challenges and technology scaling. After reviewing the latest developments gathered from the recent IMS 2006 and RFIC 2006 Symposiums, a vision for CMOS technology and platform direction for Gb/s wireless communications is proposed.

THURSDAY September 14SCV Microwave Theory and Techniques

Valon Technology, LLC

valontechnology.com

[email protected]

RF and Wireless Product Design & Development

- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

Redwood City (650) 369-0575


Spin Electronics Speaker: Professor Michael Coey, School of Physics,

Trinity College Dublin, and 2006 IEEE Magnetics Society Distinguished Lecturer

Time: Refreshments at 7:30 PM, Presentation at 8:00 PM

Cost: none Place: KOMAG, 1710 Automation Parkway, San

Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Michael Coey received a BA degree in physics from Cambridge University in 1966, and a PhD from the University of Manitoba in 1971. He worked as a researcher in the Centre National de la Recherche Scientifique in the 1970s, before moving to Trinity College Dublin, where he has been Professor of Experimental Physics since 1986.

Michael Coey has broad interests in magnetism, spanning materials hard and soft, crystalline and amorphous, metallic, semiconducting and insulating as well as magnetic phenomena and devices. He coordinated the ‘Concerted European Action on Magnets’ (1984-94), a pioneering group of academic and industrial researchers devoted to all aspects of the understanding, development, and application of rare-earth iron permanent magnets. More recently, he led the Oxide Spin Electronics Network, OXSEN 1996-2000. Currently he is Deputy Director of Ireland’s nanoscience centre CRANN. He serves as Divisional Associate Editor of Physical Review Letters and on the editorial board of the Journal of Magnetism and Magnetic Materials.

His main research interests at present are in spin electronics, including magnetic semiconductors, as well as magnetotransport and magnetoelectro-chemistry. He has published more than 500 papers, and is co-author of books on Magnetic Glasses and Permanent Magnetism. Michael Coey is the recipient of the Charles Chree medal of the Institute of Physics, and the gold medal of the Royal Irish Academy. He is a fellow of the Royal Society, and a Foreign Associate of the National Academy of Science.

Conventional electronics has ignored the spin on the electron. Besides its fundamental unit charge, the electron has a magnetic moment due to its quantum of angular momentum. Things began to change in 1988, with the discovery of giant magnetoresistance in metallic thin film stacks. This led to the development of spin valves and magnetic tunnel junctions, which allowed magnetic recording to ride the tiger of 100% year-on year growth of recording density for the past ten years.

Tunnel junctions are the active elements for most schemes for nonvolatile magnetic random-access memory, which will be briefly surveyed. These

devices, which underpin the multi-billion dollar magnetic recording industry, are nothing more than sophisticated magnetoresistors, the simplest two-terminal electronic device. If we are to see a second generation of spin electronics, it will be necessary to develop more complex devices such as a three-terminal spin transistor with gain. Here magnetic semiconductors are required, or at least the ability to manipulate spin-polarized currents in normal semiconductors. The puzzling new family of dilute magnetic oxides, such as ZnO:Co or SnO2:Mn, and the

emerging class of d0 ferromagnets such as HfO2 or CaB6 may produce a new paradigm for magnetism in solids, and support entirely new device concepts. A major challenge is to separate spin and charge currents in solids, and transmit information magnetically, without dissipation.

TUESDAY September 19SCV Magnetics


Micromachined Transducers for Medical Ultrasound Imaging

and Therapy Speaker: Butrus T. Khuri-Yakub, Professor of

Electrical Engineering, Stanford University Time: optional dinner with the speaker, Stanford

Hospital cafeteria at 6:15 PM; presentation at 7:30 PM

Cost: none Place: Clark Center Auditorium, Stanford Hospital

and Medical School (parking free after 4 PM)

RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs/

pages/upcoming.html

Dr. Khuri-Yakub is a fellow of the IEEE and Senior Member of the Acoustical Society of America. He has been Professor of Electrical Engineering for almost 25 years at Stanford University, where he obtained his PhD and worked as Senior Research Associate for many years. Dr. Khuri-Yakub has received many awards, including Stanford University Outstanding Inventor in 2004. Research interests include microfluidic devices and air-coupled acoustic microsensors, in addition to micromachined ultrasonic arrays.

Capacitive Micromachined Ultrasonic Transducers (CMUTs) have been developed in the past decade as alternative transducers for generating and detecting ultrasound. Capacitor ultrasound transducers have been known for over 100 years; however, the advent of silicon micromachining has enabled the realization of the full potential of these transducers. Silicon micromachining allows the manufacture of capacitors with very thin gaps, and with electric fields of the order of 109 V/m that determines their performance. It is now possible to make immersion CMUTs with over 100% fractional bandwidth, with an electromechanical coupling coefficient close to unity, and to make single element and one-dimensional (1D) and two-dimensional (2D) arrays of tens of thousand of elements, as well as annular arrays. CMUTs have been operated in the frequency range of 100 kHz to 50 MHz, and with a dynamic range of the order of 150 dB/V/Hz.

This presentation will first review the modes of operation of CMUTs then introduce two different technologies for making CMUTs along with a technology for integrating electronics, which is one of the major advantages of this approach. Next, examples of various types of transducers (single element, 1-D, 2-D and annular arrays with frequency response ranging from 1-50 MHz) will be presented. Lastly, we will show examples of ultrasonic imaging, functional imaging, and high intensity focused ultrasound (HIFU) therapy applications.

WEDNESDAY September 20SCV Engineering in Medicine and Biology

VOICE COIL MOTORS Design - Control - Fabricate - Test

J. Arthur Wagner, Ph.D. 1649 Fair Orchard Ave.

San Jose, CA 95125

[email protected] (408) 269-7044 (408) 206-3049 cell


Tour of USS-POSCO Industries Time: 6:00 PM (for about 2 hours) Cost: none Place: USS-POSCO Industries, 900 Loveridge

Road, Pittsburg (north end of Loveridge Road)

RSVP: Please make reservations by September 19 to Mike Nakamura, [email protected], telephone: (510) 287-2066

Web: www.ewh.ieee.org/r6/oeb/ias.html

The September 21st meeting of the Industry

Applications Society for Oakland East Bay Section will feature a tour of USS-POSCO Industries. USS-POSCO Industries is located in Pittsburg, California, approximately 40 miles east of San Francisco. The company employs almost 1,000 people and converts hot rolled steel coils into three main product lines: cold rolled sheet, galvanized sheet, and tin plate. These products are shipped to customers who manufacture a wide range of products including office furniture, computer cabinets, metal studs, culvert, metal building material, downspouts, and food packaging.

The tour will last approximately two hours. Please wear close-toe shoes, long pants, and long-sleeve shirt (or jacket) for this tour. Be prepared to walk approximately 1 mile and climb 66 stairs, and to present valid picture identification at the security gate.

Space is limited so reserve early.

THURSDAY September 21

OEB Industry Applications


UPS System Design & Protection

Against Ground Faults Speaker: Kameel Andrawos, VP of Power Systems,

MGE UPS Systems Time: 6:00 PM dinner; 7:00 PM Presentation Cost: Dinner is $25 for Members, $30 for non-

members, $10 for students Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101


RSVP: by email to James Alvers, [email protected] (925) 730-3105

Web: www.e-grid.net/docs/0609-scv-pesias.pdf Kameel Andrawos is the VP of Power Systems

for MGE UPS SYSTEMS. Kameel started in the UPS industry in 1980 and has been with MGE UPS SYSTEMS for the past 20 years. His past experience includes UPS module and systems design. Kameel is an expert at designing and integrating UPS systems into a variety of facilities with a special expertise in designing systems to maximize UPS compatibility with switchgear, backup generators and power loads.

This presentation focuses on the design of UPS

systems. It will cover both single module UPS configurations as well as Redundant Configurations. As part of this discussion, you will learn about how to protect against ground faults on the UPS input source, DC bus and the UPS output. The discussion will focus on system designs that allow for full operation of the UPS, even during ground faults. General questions on UPS layout and configurations will also be discussed.

WEDNESDAY September 20SCV Power Engineering and Industry Applications







Application of Carbon Nanofibers for On-chip Interconnect

Applications Speaker: Quoc Ngo, PhD Candidate, Santa Clara

University Time: Refreshements/Networking at 6:00 PM,

Presentation at 6:30 PM Cost: none Place: National Semiconductor Building 31

Auditorium, 955 Kifer Road, Sunnyvale RSVP: Please make reservations by to

[email protected] Web: www.ewh.ieee.org/r6/scv/ssc

Quoc Ngo earned his B.S. in Electrical Engineering

from Oregon State University in 2001 and his M.S. from Santa Clara University in Electrical Engineering in 2003. His Master’s research involved the development of a compact model for MOSFET gate-current. He is currently pursuing the Ph.D. degree in Electrical Engineering with the Center for Nanostructures at Santa Clara University. His primary research interest includes synthesis and modeling of carbon nanofiber on-chip interconnects. Quoc is involved in the joint development with NASA Ames Research Center of a thermal interface material for microelectronic packaging applications using carbon nanofiber arrays. His summer internships at Intel Corporation from 1997-2002 have included Yield Analysis, Defect Metrology, Back-end Integration, and Interconnect Research and Development for developmental 300mm processes. Currently he is actively collaborating with the Center for Nanotechnology, NASA Ames Research Center in an initiative to incorporate carbon nanofibers into silicon-based technology.

In this work, we present electrical characteristics

of vertically aligned carbon nanofiber (CNF) arrays for on-chip interconnect applications. The study consists of the investigation of electron transport mechanisms in these structures using low-temperature (~4K-300K) I-V measurements. The measured resistivity in CNF arrays is modeled based on known graphite a-axis (parallel to basal plane) and c-axis (perpendicular to basal plane) electron conduction mechanisms. The model is verified using high-resolution scanning transmission electron microscopy (STEM) of the CNF-metal interface. We also show that the selection of catalyst material plays a vital role in the interface characteristics of CNFs. Electrical reliability measurements are performed at different temperatures to demonstrate the robust nature of CNFs for interconnect applications. We show that carbon-based nanostructures provide a viable alternative for an electromigration-resistant interconnect material.

THURSDAY September 21

SCV Solid State Circuits

Bernie Siegal

650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures


Conductors for Wiring Speaker: Richard Temblador, Director of Product

Development, Southwire Company Time: Social at 5:30 PM; Presentation at 6:00 PM,

Dinner at 7:00 PM Cost: $25 Place: Sinbad’s Restaurant, Pier 2 The

Embarcadero, San Francisco RSVP: to Jack Lin, SFPUC [email protected],

415.551.4894 Web: ewh.ieee.org/r6/san_francisco/ias

Richard Temblador is Director, Product Development, Electrical Division for Southwire Company in Carrollton, Georgia. He is a member of NEC Code Panels 5 & 8, and has previously served on NEC Code Panel 7, UL Standards Technical Panel 4 (covering AC and MC Cables), and the NEMA 7RV Building Wire Technical Committee.

This presentation will focus on conductors and will review 600 volt insulating materials, products, and selection parameters. There will also be a brief review of new products currently under development.

Assisting with the presentation will be Jim Bright, Western Regional Manager for Southwire Industrial Products Division. Jim manages all industrial products including Medium Voltage Tray Cable, Armored Cable, Transit, and MC Feeder Cable. He has 18 years in the electrical business including 11 years with 3M Electrical Products Division, and 4 years as District Manager with the Okonite Company.

TUESDAY September 26SF Industry Applications


Advanced Digital Cable Architectures and Technologies

Speaker: Greg Thompson, Chief Video Architect,

Cisco Systems Time: pizza and drinks at 6:30 PM; Presentation at

7:00 PM Cost: $5 for IEEE members, $10 for guests Place: HP Oak Room (Building 48), 19447

Pruneridge Avenue, Cupertino RSVP: not required Web: www.ieee.org/scvce

The focus of this meeting is on advanced Digital

Cable Architectures and Technologies. Hear about DCAS, NGNA, DSG, Digital Simulcast, Channel Bonding, Edge QAMs and a host of topics that the cable industry is working on right now and in the future to bring better services and be more competitive.

TUESDAY September 26SCV Consumer Electronics


3-D and Multi-Technology Packaging: Current Capabilities

Speaker: Phil Marcoux, SIP/MCP and Business

Development Manager, CORWIL Time: Buffet lunch at 11:45 AM;

Presentation at 12:15 Cost: Lunch is $15 (preregistered, or use our

PayPal system) or $20 at the door Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101


RSVP: Either through PayPal, or to John Jackson, Analog Devices, [email protected]

Web: www.cpmt.org/scv

Phil Marcoux is a Sr. Member of the IEEE and past Executive Director of MEPTEC. He's currently the SIP/MCP and Business Development Manager for CORWIL (Milpitas CA). Previously Phil was CEO of two well known start-ups and Associate Professor at the Graduate School of Engineering, University of Santa Clara.

The interest in multi-component (MCP) IC

packaging has created several new assembly technologies and demands. The nuances of some of these technologies are well understood for some and emerging daily for others. This presentation will summarize what is known and still challenging for the key technologies including wafer thinning, dicing before grid, die stacking, new die attach materials, wire bonding and flip chip. The speaker will cover the common substrate types, the economics, and the design challenges encountered by his company's experiences.

THURSDAY September 28SCV Components, Packaging and Manufacturing Technology


The Solid State Heat Capacity Laser (SSHCL) Program

Speaker: Bob Yamamoto, Lawrence Livermore

National Laboratory Time: Networking and Pizza Social at 7:00 PM,

Presentation at 8:00 PM Cost: none Place: National Semiconductor Credit Union

Auditorium, 955 Kifer Road, Sunnyvale RSVP: by email to ieeescvleos-

[email protected] Web: www.ewh.ieee.org/r6/scv/leos

Bob Yamamoto is currently the Program Manager and Project Engineer for the Solid State Heat Capacity Laser (SSHCL) program at the Lawrence Livermore National Laboratory. He received his BS in Mechanical Engineering from UC Berkeley, an MBA from Golden Gate University and is a registered professional mechanical engineer in the state of California. Mr. Yamamoto has worked in both the private sector (TRW and General Atomics) and National Labs (LLNL and LBNL) during his 29-year career. He has been the recipient of two R&D 100 awards (development of a human cancer treatment system utilizing magnetic fields and a diode-pumped laser for humanitarian mine clearing), has authored/co-authored 40 technical papers and his work has been the subject of 10 scientific magazine articles.

The Solid State Heat Capacity Laser (SSHCL)

program at the Lawrence Livermore National Laboratory (LLNL) has developed the world’s most powerful diode pumped “electric laser”. In January 2006, the SSHCL achieved 67 kW of average output laser power for short fire durations, which equates to 335 joules/pulse at our 200 Hz pulse repetition rate. As the name implies, the term “heat capacity” refers to the fact that the laser gain media stores any resultant energy in the form of heat during the lasing process, and has to subsequently be cooled off-line while another set of laser gain media are in use. Separating the lasing function from the cooling function for the laser gain media promotes straightforward and simple laser architecture, while allowing quasi-continuous laser operation.

The program has come to a major crossroad in its evolution as we prepare for its transition from a laser technology demonstration device in a laboratory setting, to a fully operational directed energy weapon capable of engaging live targets under actual battlefield conditions. In order to accomplish this, a fieldable prototype is needed that will allow those who would ultimately use the SSHCL in the battlefield to carry out laser performance and system operations testing in conjunction with reliability experiments. A 100 kW mobile SSHCL system is proposed to be built for this next step.

TUESDAY October 3SCV Lasers and Electro Optics

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

[email protected] www.ozeninc.com


Convergence Challenges of Photonics with Electronics

Speaker: Dr. Edward Palen, PalenSolutions

Optoelectronic Packaging Consulting Time: 6:30 PM dinner (optional);

7:30 PM Presentation Cost: Dinner is $25 (use our PayPal system); no

cost for presentation Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101


RSVP: Either through PayPal, or to Janis Karklins, [email protected]

Web: www.cpmt.org/scv

Dr. Edward Palen, P.E., specializes in creating solutions for the design, prototyping, qualification and manufacturing of optoelectronic and microelectronic devices through his business, PalenSolutions Optoelectronic Packaging Consulting. Services include packaging solutions for lower cost devices, component integration solutions, materials choices, process development, design-for-manufacturability, and generating configurations for integration of photonics with electronics, CMOS processing and assembly processing.

Prior to this Edward was Director of Advanced Process Development at Teledyne Optoelectronics for outsource manufacturing and product development for telecommunications markets. He was a lead materials and process problem solver for Mil-Sat payloads and satellite solar arrays at TRW Space & Electronics Group. At GM Hughes Electronics he was responsible for M&P troubleshooting in the business units of electro-optical data systems, satellites, radar, missiles, HRL and power products. Edward has a Ph.D. in Chemical Engineering from University of California Los Angeles and a B.Sc. in Chem. Eng. from University College London, England. He is based in the San Francisco Bay Area and consults with companies globally.

Photonics communication advantages of higher bandwidth, lower latency, and lower power consumption predestine photonics to be integrated with electronic integrated circuits. Convergent solutions are challenged by low cost requirements and CMOS compatibility. Cost requirements are 2 to 3 orders of magnitude lower than that of telecom and datacom photonic device configurations. Solutions that integrate photonics functionality with CMOS processing have yet to be widely explored. This presentation will address the challenges for convergence solutions, review state-of-the-art advances and predict future trends.

WEDNESDAY October 11

SCV Components, Packaging and Manufacturing Technology


Microwave High Power Amplifier Design and Testing

Speaker: Dr. Franco Sechi, Microwave Power Inc. Time: 6:00 - Refreshments and Social,

6:30 PM - Presentation Cost: none Place: National Semiconductor, Bldg #9,

Classroom #4, 2900 Semiconductor Dr., Santa Clara

RSVP: not required Web: www.mtt-scv.org

Dr. Franco Sechi received the doctor degree in electrical engineering from the Politecnico of Milano, Italy. He worked for 15 years at the RCA Laboratories in Princeton on R&D programs for solid-state power amplifiers. During this time he developed the first modern load-pull system, the first computer-controlled infrared microscope and the first system for measuring current and voltage microwave waveform in power transistors. He also developed the first miniature circuits on berillia substrates. In 1986 he co-founded Microwave Power Inc, a manufacturer of high performance solid-state power amplifiers where he served as President or Vice President. In 2004 Microwave Power Inc merged with AML Communications, a manufacturer of low-noise amplifiers. Dr. Sechi is presently a Vice President of AML and the General Manager of the Microwave Power Division. Dr. Sechi is author of many papers and patents. He is a member of the MTT-5 Committee on High Power Amplifiers and he is a life-member of IEEE.

Microwave power amplifiers are key components in many systems such as radars, radios, base stations and cell phones. Their performance is often a key factor in the performance of the overall system. This talk covers some of the most important aspects in the design of power amplifiers. It covers characterization techniques of active devices and design procedures for various types of power amplifiers. These include saturated amplifiers optimized for maximum output power, linear amplifiers optimized for low intermodulation, high-efficiency amplifiers optimized for maximum efficiency, and broad-band amplifiers optimized for maximum power-bandwidth product. Since the technological implementation of microwave circuits is a key factor in the performance of power amplifiers, this talk also outlines an advanced technology for the fabrication of monolithic circuits on ceramic substrates.

THURSDAY October 12SCV Microwave Theory and Techniques


One-day Symposium: The World with RFID

Speakers: From industry, VC community, government Time: 8:30 AM registration;

9:00 AM - 5:30 PM presentations Place: Biltmore Hotel, Santa Clara RSVP: See website, or email Dr. Martin Chen,

Conference Chair, [email protected] Web: www.natea.org/sv/conferences/

uthf/2006/program.php

• Dr. Krish Mantripragada, Director of SAP RFID Product Management

• Thomas Odenwald, Director of SAP RFID Research RFID Research

• Dr. Richard Swan, CTO, T3Ci (Also EPCglobal EPCIS working group co-chair)

• Dr. Elmer M. Hsu, VP & General Director of RFID Technology Center, ITRI, Taiwan

• Dr. Richard Zai, CTO, Adeptiden • Jeff Jacobsen, President of AWID • Richard Bravman, Chairman & CEO of

Intelleflex Corporation • Dr. Jimmy Li, Deputy Director, Initiative Office

for Government RFID applications, Ministry of Economic Affairs, Taiwan

• Keith Cotterill, President and Founder of Bonsai Development Corporation

RFID is a groundbreaking technology that will

serve as the replacement for UPC codes and has already been adopted by both retailer giants like WAL-Mart and Target, with the U.S. Department of Defense – the largest consumer of goods in the world – expected to follow suit. The trend of utilizing RFID to enable Real World Awareness is going to open new dimensions of applications across software and hardware. Theis one-day symposium aims to explore the solutions that are needed to enable RFID systems as well as the RFID applications.

SATURDAY October 14SCV Computer


Recollections of the Early History

of Video Tape Recording

Speaker: Fred Pfost, member of the original Ampex tape-recorder development team

Time: Refreshments at 7:30 PM, Presentation at 8:00 PM

Cost: none Place: KOMAG, 1710 Automation Parkway,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Fred Pfost spent ten years at The Ampex

Corporation in Redwood City directly after graduating from UC Berkeley in January of 1952. He was instrumental in the development of many of the audio, instrumentation, and video products that Ampex produced during his stay: the 21-channel instrumentation recorder; the 7-channel FM recorder; a semiprofessional portable audio recorder (model 600); a portable amplifier-speaker unit (model 620); an oil well logging recorder; the VR 1000 video recorder, and glass bonded ferrite heads for video recording.

Following his term at Ampex Mr. Pfost did consulting for the next 30 years doing work for 25 different local, national and international companies. He started three companies during that period and developed some breakthrough technologies that set the standards of achievement for the various industries:

(Continued, next page)

When one compares the information content

requirements for video recording versus audio recording, the ratio is about 1000 to 1. Pulling tape at high speeds is not practical when one considers tape speeds of 10 to 100 feet per second. RCA first tried 360 inches per second (30 feet per second) on 2-track recording and later lowered that to 240 ips (20 fps.) Crosby ran 100 ips (8.3 fps) using a 10 track multiplexed signal. England developed VERA that ran at 840 ips (70 fps) for 15 minutes of recording on a 21 inch diameter reel.

Ampex using a rotating head approach with frequency modulation and ran the tape at 15 ips but the head-to-tape speed was 1500 ips (when spinning at 14,400 rpm). This gave a video bandwidth of about 4 MHz which the industry wanted and needed. This also allowed 1 hour recording time on a 10.5 inch reel of 2 inch wide tape.

All of these developments were done in the early ‘50s. We originally used amplitude modulation but later changed to frequency modulation. The original FM circuitry used a high RF carrier frequency with subsequent heterodyning down to a frequency compatible with recording onto tape. This circuitry was followed by a simpler system directly modulating a multivibrator circuit running at a carrier frequency compatible with recording on tape (5 MHz).

The original rotary head orientation wrote arcuate traces across the tape. In playback we saw a scalloped output as the head crossed the tape. It took us quite a while to deduce the cause of this scalloping. We finally decided that the tape was longitudinally oriented and there was some longitudinal motion as well as transverse motion in the passage of the head across the tape in the arcuate sweep, and thus higher output near the tape edge and lower output near the middle of the head pass. This would require a large amount of automatic gain control. While I was developing this AGC circuit we decided to just change the head orientation to produce transverse paths across the entire tape, thus eliminating the variations in the output signal off-tape. (We also changed to unoriented tape.) This was the configuration used by the entire industry until the advent of the helical scan configuration some 20 years later.

(Continued, next page)

TUESDAY October 17SCV Magnetics


I was put in charge of the transducer design and video head assembly design. 15,000 “Quad” machines were produced by Ampex over the next 20 years with little change in this design. This required about 50,000 head assemblies to cover the use and replacement schedule. Head life was about 100 hours at the beginning and advanced to at least 5000 hours later with the advent of ferrite heads with glass gaps and air bearings.

Biography (continued, from prev page)

Several of Fred Pfost’s accomplishments:

• The computer industry’s first hard disc data recorder developed for Data Disc in Mtn. View -1963 (This technology was licensed to IBM and eventually became known as the Winchester Disc.)

• Stop action-instant replay hard disc video recorder developed for Mactronics in Mtn. View in 1965 (Ampex came out with their version of this device a year later.)

• Video Cartridge Recorder developed for Cartrivision in 1970

• High speed, high tension tape cartridge developed for Newell Research in 1975

• Automated Robotic Work Station (Automatic, Microprocessor Controlled Pipetter) for Infinitek (purchased by Beckman Industries) in 1985

• Automatic, spring-loaded, lever-cocked pool cue developed for Automatic Ball Driver, Inc. in 1992

Mr.Pfost has 50 U.S. Patents and hundreds of foreign patents.

He was awarded three EMMYs over the years. 1) for the Video Tape Recorder at Ampex in 1957; 2) for the Stop Action-Instant Replay Recorder at Mactronics in 1966; 3) for “Lifetime Achievement” on September 29, 2005. This last one was the first time that the Television Academy had ever given a “Lifetime Achievement” award in the technical EMMY category.


Status of Nanotechnology Initiatives at the University, State,

& Federal Levels

Speaker: Tom Kalil, Special Assistant to the Chan-cellor for Science and Technology at UC Berkeley, and formerly Deputy Assistant to President Clinton for Technology and Economic Policy

Time: Registration & light lunch 11:30 AM, Presentation & Q/A at Noon

Cost: IEEE Members and Students $5, Non-Members $10

Place: National Semiconductor Building 31, 955 Kifer Road, Santa Clara

RSVP: Please reserve by email to [email protected]

Web: www.ieee.org/nano There are a myriad of Initiatives at the University,

State, and Federal levels which are experiencing various levels of success. Tom will give a flavor of what it takes to start them and make them effective.

.

Thomas Kalil is currently the Special Assistant to

the Chancellor for Science and Technology at UC Berkeley. He has been charged with developing major new multi-disciplinary research and education initiatives at the intersection of information technology, nanotechnology, microsystems, and biology. He will also help develop a broad range of partnerships between 2 of the California Institutes of Science and Innovation (Center for Information Technology Research in the Interest of Society, California Institute for Bioengineering, Biotechnology and Quantitative Biomedical Research) and potential stakeholders in industry, government, foundations, and non-profits.

Previously, Thomas Kalil served as the Deputy Assistant to President Clinton for Technology and Economic Policy, and the Deputy Director of the White House National Economic Council. He was the NEC’s “point person” on a wide range of technology and telecommunications issues, such as the liberalization of Cold War export controls, the allocation of spectrum for new wireless services, and investments in upgrading America’s high-tech workforce. He led a number of White House technology initiatives, such as the National Nanotechnology Initiative, the Next Generation Internet, bridging the digital divide, e-learning, increasing funding for long-term information technology research, making IT more accessible to people with disabilities, and addressing the growing imbalance between support for biomedical research and for the physical sciences and engineering. He was also appointed by President Clinton to serve on the G-8 Digital Opportunity Task Force (dot force).

Prior to joining the White House, Tom was a trade specialist at the Washington offices of Dewey Ballantine, where he represented the Semiconductor Industry Association on U.S.-Japan trade issues and technology policy. He also served as the principal staffer to Gordon Moore in his capacity as Chair of the SIA Technology Committee. Tom also serves as a consultant for organizations such as the Semiconductor Industry Association, Internet2, CommerceNet, and the “Digital Promise” initiative proposed by Newton Minow and Larry Grossman.

Tom received a B.A. in political science and international economics from the University of Wisconsin at Madison, and completed graduate work at the Fletcher School of Law and Diplomacy. He is the author of articles and op-eds on S&T policy, nanotechnology, nuclear strategy, U.S.-Japan trade negotiations, U.S.-Japan cooperation in science and technology, the National Information Infrastructure, distributed learning, and electronic commerce.

TUESDAY October 17SCV Nanotechnology


Fall Banquet and Presentation

Speaker: Michael R. Peevey, President, California Public Utilities Commission

Time: 5:00 PM networking/social, 6:30 PM dinner, 7:30 PM presentation

Cost: Full-course dinner - IEEE Members $20, non-members $25 (thru Sept 17), $5 more afterwards(full-time students: $10)

Place: Monte Cristo Cafe, 4 Embarcadero Center, San Francisco

RSVP: Please see our website for menu selection and registration form

Web: ewh.ieee.org/r6/san_francisco/pes

Michael R. Peevey joined the California Public Utilities Commission in 2000 at the height of the energy crisis and went right to work forging strong bonds with sister agencies, such as the California Department of Water Resources, the Independent System Operator, the California Energy Commission, and the California Power Authority to deal with the crisis.

He encouraged the group to focus on assuring that California has adequate energy resources and transmission facilities to support its growing population and improving economy. Prior to joining the Commission, Mr. Peevey served as President of NewEnergy Inc. and President of Edison International and Southern California Edison Company. Mr. Peevey holds both a Bachelor and Master of Arts degree in economics from the University of California, Berkeley. He is married to Assembly member Carol J. Liu (D-La Cañada Flintridge). They have three children.

We asked the President of the California Public Utilities Commission, Michael Peevey, to talk about the Commission’s accomplishments this year and the major issues he sees for the electric industry in the coming one.

Please register (see the website for form) for this

banquet by September 17, and choose the entre you desire (Wild King Salmon with vegetables and fennel; Wood oven roasted Chicken with rosemary and garlic red potatoes; Risotto with vegetables, parmesan & thyme). We look forward to a great and informative evening! Validated parking is available in Embarcadero Center Garage.

TUESDAY October 17SF Power Engineering

Documents

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