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Upcoming Conferences
Oct 1-5: Broadband Comm’ns, Networks, Systems (BroadNets) – Doubletree Hotel San Jose [more]
Oct 9-11: Fall Micoprocessor Forum: Advances in Power Efficiency - Doubletree Hotel San Jose [more]
Oct 22-27: IEEE International Test Conference (Test Week 2006) - Santa Clara Conv Center [more]
Oct 25-27: IEEE Int'l Symposium on Workload Characterization - Hilton Hotel, San Jose [more]
Nov 5-9: Int'l Conference on Computer-Aided Design (ICCAD) Double Tree Hotel, San Jose [more]
Nov 12-17: AVS 53rd International Exhibition and Symposium - Moscone West, S.F. [more]
Nov 27 - Dec 1: Global Telecommunications Conf-erence (GLOBECOM) - Fairmont Hotel, S.F. [more]
Dec 3-6: Winter Simulation Conference - Portola Plaza Hotel, Monterey [more]
October 2006CHAPTER MEETINGS
SCV-LEOS - 10/3 | The Solid State Heat Capacity Laser (SSHCL) Program - transition from demonstration to operational weapon ... [more]
SCV-EDS - 10/10 | Overview of Next Generation Semiconductor Manufacturing - economics of the future sub-45nm processes ... [more]
SCV-CPMT - 10/11 | Convergence Challenges of Photonics with Electronics - low cost requirements and CMOS compatibility ... [more]
SCV-MTT - 10/12 | Microwave High Power Amplifier Design and Testing - for radars, radios, base stations and cell phones ... [more]
IEEE-SPECTRUM - 10/12 | SPECTRUM Career Accelerator Forum - 9 AM online live talks by career specialists, educators... [more]
SCV-CS - 10/14 | Seminar: The World with RFID - new dimensions of RFID applications across software and hardware ... [more]
SCV-Mag - 10/17 | Recollections of the Early History of Video Tape Recording - the Ampex team and first video tape recorder ... [more]
SCV-Nano - 10/17 | Status of Nanotechnology Initiatives at the University, State, & Federal Levels - a myriad of initiatives ... [more]
SF-PES - 10/17 | Fall Banquet - Michael R. Peevey, President, California Public Utilities Commission – major issues ... [more]
SF-CNSV - 10/17 | Protecting Your Intellectual Property - IP created while you work as a consultant, and patent law ... [more]
SCV-EMB - 10/18 | MEMS for Medical Applications - microsystems made from glass, silicon carbide, diamond, flexible polymers ... [more]
Monterey - 10/19 | Clock Generation and Distribution in High-Performance Processors - clock skew and jitter, low-power... [more]
SCV-CE - 10/24 | HANA: the High-definition AV Network Alliance - connectivity between AV devices via IEEE-1394 ... [more]
SCV-Rel - 10/25 | Trapped by MTBF? - common issues, significant errors, what questions you should ask ... [more]
SCV-EDS - 10/26 | Has The Time Arrived For Manufacturing High-K/Metal Gates? - full-day seminar ... [more]
SCV-CPMT - 10/26 | Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High-Volume Manufacturing - die-side bumps mated to eutectic tin-lead package-side bumps ... [more]
SCV-LEOS - 11/7 | Electro-Optic A/D Converters - digitizing a 10-GHz bandwidth signal at 10 bits resolution ... [more]
SCV-MTT - 11/9 | Calibration and Error Correction Techniques for Network Analysis - accuracy of measurements, calibration ... [more]
SCV-Mag - 11/14 | The Technology of Magnetic Hard Disk Drive Storage - advanced read/write heads - PMR, thin film media ... [more]
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MARKETPLACE – Services page 3
Chapter One-Day Seminars and Classes:
Seminar: The World with RFID October 14, at the Biltmore Hotel, Santa Clara [more] "Clear Business, Technical, and E-mail Writing" -- at
Exar Corporation (Fremont), October 17 [more]
"Collaborative Negotiating" -- at Carl Zeiss Meditec (Dublin), October 17 [more]
"Breakthrough Project Management" -- at TIBCO Software (Palo Alto), October 19-20 [more]
"Speed Reading for Engineers" -- at Exar Corporation (Fremont), October 25 [more]
"Collaborative Negotiating" -- at TIBCO Software (Palo Alto), November 9 [more]
"High-Impact Communication" -- at VeriSign (Mountain View), November 14 [more]
"Clear Business, Technical, and E-mail Writing" -- at TIBCO Software (Palo Alto), November 16 [more]
"Managing Time and Multiple Priorities " -- at Exar Corporation (Fremont), December 12 [more]
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 2
Your Networking Partner ®
October 2006 • Volume 53 • Number 10
IEEE-SFBAC ©2006
IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition
residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.
Editor: Paul Wesling IEEE GRID 12250 Saraglen Dr. Saratoga CA 95070 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net
NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net
DIRECTORS
Santa Clara Valley Lee Colby
Fred Jones
Oakland East Bay Alan Meyer Bill DeHope
San Francisco Dan Sparks Julian Ajello
OFFICERS Chair: Fred Jones
Secretary: Alan Meyer Treasurer: Dan Sparks
IEEE-SFBAC PO Box 2110
Cupertino, CA 95015-2110
IEEE GRID
O c t o b e r 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 3
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road, Palo Alto 94303
www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835
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650-961-5900
[email protected] www.thermengr.com
Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures
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• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available
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• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses
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EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)
Facilities in Union City and Santa Clara
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RF and Wireless Product Design & Development
- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness
Redwood City (650) 369-0575
Digital Chip Design Services
ASIC Design • EDA Evaluation • Verilog HDL • Synthesis • Design for Visibility • Timing • Scan • Verification • Low Power techniques • Power Analysis • BIST • DFT • ATPG • Silicon Debug
Testable logic for high-volume production with low DPM
Contact Mahesh Siddappa ME (CS, India), MS (EE, SUNY at Stony Brook)
[email protected] 408-981-6612
VOICE COIL MOTORS Design - Control - Fabricate - Test
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[email protected] (408) 269-7044 (408) 206-3049 cell
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 4
October 9-11, 2006 DoubleTree Hotel, San Jose
The Fall Microprocessor Forum provides concentrated insights about trends and architectures needed by designers and technical business people, accompanied by technical background and design considerations. Leading organizations present their PC processors, server processors, low-power embedded processors, consumer embedded, imaging DSPs, and on challenges of advanced semiconductor design. Presenters from multiple companies will compete for your attention via technical presentations – no marketing allowed.
Technical Sessions: • New Server Architectures (FJ SPARC64, IBM Power6, Sun Niagara2, more) • Processor Cores (RISC-free VoIP, PAC, FPGA-based) • Multicores for Embedded Applications (TeraOPS, gCORE16, Sensor-Processor, OCTEON CN48xx, SH-X3) • Multimedia at the HW-SW Interface (Embedded Audio, MSCB144 DSP, OpenGL Mobile GPU Core, Media Processor) - and more
Sponsors: IBM, Sun, VIA Exhibitors: ARM, CEVA, Green Hills, OCP, Obsidian, Tensilica, VaST, and others
October 25-27, 2006
Hilton Hotel San Jose
IISWC is dedicated to the understanding and characterization of workloads which run on all types of computer systems. New applications and programming paradigms continue to emerge as the use of computers becomes more widespread and more sophisticated. Improving process and communication technology, innovations in microarchitecture, compilers, and virtual-machine technology are also changing the nature of problems that are being solved by computing systems. Whether they are PDAs at the low end or massively parallel systems at the high end, the design of tomorrow’s computing machines can be significantly improved through the knowledge and ability to simulate the workload expected to run on them. We invite you to attend IISWC this year to participate in these advancements.
Monday full-day Seminar: “Maximum Performance, Minimum Power” with Max Baron, Senior Editor & Principal Analyst • Low power for mobile processors • Cooling techniques for very-high-performance engines • Presentation by Cadence on low power design tools • Presentation by Texas Instruments on low power technologies Keynote Addresses: “Energy Efficient Performance: The Next Frontier” Dr. Dileep Bhandarkar, Architect-at-Large, Digital Enterprise Group, Intel
“Priorities in Energy: Optimized Processing” John Cornish, Vice President, Processors Division, ARM
Our Chip Portfolio will highlight key industry players and their contribution to chip enhancement and performance over the years.
For full details, visit our website:
www.in-stat.com/FallMPF/
SESSIONS • Characterization of Multimedia and Games Workloads • Energy and Power Behavior of Applications • Characterization and Analysis of Bioinformatics Workloads • Benchmark Construction and Evaluation • Novel Insights and Techniques • Understanding Java Workloads • High Performance Computing Workloads • New Benchmarks
TUTORIALS AM: “Software Performance Tuning with the Apple CHUD
Tools,” Rick Altherr, Ryan Du Bois, Lance Hammond, and Eric Miller
PM: “Building Workload Characterization Tools with Valgrind,” Nicholas Nethercote, Robert Walsh
BENCHMARKS WORKSHOP Selected benchmarks, with authors presenting their programs and input data sets.
Advanced Registration Deadline: Wednesday, October 11
For further information, and to register:
www.iiswc.org
2006 IEEE International Symposiumon Workload Characterization
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 5
Developments in the field of vacuum technology have contributed significantly to the growth and success of the semiconductor industry in Silicon Valley. The 2006 Symposium addresses important issues in the research and development of thin films, electronic and photonic devices, biomaterials, magnetic materials and micro and nanostructures, as well as surface and interfacial issues, methods of processing, and manufacturing and vacuum technology. The conference covers a broad spectrum of cutting-edge topics that focus on physical and chemical phenomenon occurring at the interfacial regions of complex systems.
TECHNICAL SYMPOSIA: • Advanced Surface Engineering • Applied Surface Science • Biomaterial Interfaces • Electronic Materials and Processing • Magnetic Interfaces and Nanostructures • Manufacturing Science and Technology • Nanometer-Scale Science and Technology • Plasma Science and Technology • Surface Science • MEMS and NEMS • Thin Film • Vacuum Technology
TOPICAL CONFERENCES: • Energy Science & Technology • Nano-Manufacturing • Nucleic Acids at Surfaces • Ultra-Bright Light Sources
PUBLIC LECTURE: “The End of Oil: Dependence, Depletion, and Derail,” Paul Roberts, independent journalist – has written for Harper’s Magazine, The Los Angeles Times, The Washington Post, Slate, USA Today, Newsweek – author of book The End of Oil
PLENARY LECTURE: “Far-field Fluorescence Microscopy at the Macromolecular Scale”
SHORT COURSES: • Operation and Maintenance of Vacuum Pumping
Systems • Partial Pressure Analysis • Plasma Etching and RIE • Reactive Sputtering and Deposition • Sputter Deposition • UHV Design and Practices • X-ray Photoelectron Spectroscopy (XPS/ESCA)
EXHIBITION: FREE ADMISSION An extensive display of tools, equipment, services and consulting for film deposition, surface and interface measurements and analysis, materials, chemicals, and supplies, vacuum production and measurement, and related instrumentation for surface, interface and film measurements, as well as professional literature and publications.
SPECIAL SESSIONS & EVENTS: • AIP Industrial Physics Forum (IPF): Providing a “meeting
of the minds” in physics. The IPF is designed to foster the sharing of knowledge and collaboration, and is an opportunity to exchange ideas with other R&D leaders facing similar research and business challenges. The theme is ‘Nanotechnology in Society and Manufacturing’
• Biomaterials Plenary Session: Featuring three plenary lectures focusing on recent issues relating politics and science in the field of nanotoxicology (V. Colvin, Rice University), breakthrough nanofabrication innovations in novel microfluidic processing systems (H. Craighead, Cornell University), and nano-tag labeling methods for highly resolved detection, identification and analytical capabilities in complex biological systems (M. Natan, Nanoplex Technologies).
• Exhibitor Workshop: Emphasizing new techniques and/or applications in research, industrial, manufacturing or processing; technology transfer from R&D to manufacturing; Scale-up aspects and innovations in manufacturing practices; technology/economic aspects and market impact of new and innovative scientific and/or engineering technologies. The presentations will be held in a specially designated area of the Exhibit Hall.
• International Conference on Nanoimprint & Nanoimprint Technology (NNT): Offering an international platform for presentation of the latest developments related to the scientific and economic potential of NNT technology and applications. Leading groups from the United States, Asia, and Europe will discuss the ‘state of the art’ and focus on maintaining the close links between researchers, technologists and the emerging NNT industry. Further details on the program for NNT'06, are available at www.NNTconf.org
Registration Discount Deadline: October 23rd!
More Information: For more details, please access the AVS Website:
www2.avs.org/symposium/ sanfrancisco/
Short Courses – Technical Sessions – Exhibits
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 6
Getting More out of Test
The IEEE International Test Conference is the world's premier event dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.
ITC offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including: formal paper sessions, tutorials, panel sessions, case studies, lecture and application series, commercial exhibits and presentations, and a host of ancillary professional meetings. Keynote/Invited Addresses “Managing Test, Yield, Quality, and Cost in Fabless Manufacturing Model,” Chris Malachowsky, Co-Founder, NVIDIA Fellow and Senior Vice President “The Impact of Globalization on Test and the Test Engineer,” Gregg Jordan, Sr. Director, Manufacturing Test Engineering, Cisco Systems, Inc. “On the Need for Convergence Between Design Validation and Test,” Siva Yerramilli, General Manager, Design and Technology Solutions (DTS), Intel Corporation “It's Not What You Can Make—It's What You Can Test,” W. Robert Daasch, Professor, Electrical and Computer Engineering, Portland State University World-Class Exhibits Free exhibits-only admission on Wednesday afternoon and all day Thursday (with lunch included on Thursday).
Test Week: October 22-27 Conference and Exhibition: October 24-26 Santa Clara Convention Center
Sponsors: IEEE Computer Society Test Technology TC
The Philadelphia IEEE Section
Seventeen Full-day Tutorials, including • Semiconductor Test and DFT Fundamentals • Advanced Memory Testing • GHz Interconnects—Electrical Aspects • Design for Testability for RF Circuits and Systems • Test Strategies for System-in-Package • Statistical Methods for VLSI Test, Quality and Reliability • Soft Errors: Trends, System Effects and Protection Techniques • Debugging Compression-based Tests: OPMISR, XDBIST, EDT, LBIST • Wafer Probe Test Technology • Timing Issues for Sub-100-nm Designs—Modeling to Production Three Multi-day Workshops • Design-for-Manufacturability and Yield October 26-27 • Current- and Defect-based Testing October 26-27 • Silicon Debug and Diagnosis October 26-27 Three days of 33 technical sessions Including Manager's Track, 7 panels, 4 lectures • Making Decisions Based on Economics • Improving Test Efficiency • RF Testing • Xtreme ATE: Solving Jitter Challenges • xJTAG X 3 • Advances in Test Data Compression • Microprocessor Test • Mixed-Signal Test Techniques (plus 25 others)
Download the full program – plan to attend
Visit our website:
www.itctestweek.org
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 7
The IEEE GLOBECOM technical program is focused on research and development. GLOBECOM includes the general conference and 13 symposia conducted by the various COMSOC technical committees covering major industry technologies and numerous hot topics – over 1000 presentations. Keynote Presentations: Bill Smith, CTO, BellSouth Ki Tae Lee, President, Samsung Telecommunications
Network Business Christopher Rice, Executive Vice President, Network
Planning and Engineering, AT&T Services Prof. Jean Walrand, University of California Berkeley
Technical Sessions highlights (see full program) General Conference sessions: • Power Line Communications • Resource Management in Wired & Wireless Networks • Information Theory and Coding for Data Storage • Signal Processing for Data Storage
Advanced Technologies & Protocols For Optical Networks sessions: • Access Networks • Core Networks Design • Optical Packet Switching • Survivability • Test Bed & System Design • Traffic Engineering & Protocols
Communication Theory sessions: • Cooperative Networks • Detection and Coded Modulation • Diversity Techniques • Error Control Coding • LDPC and Convolutional Codes • MIMO Systems • OFDM Systems • Space-Time Codes
Control And Management Of High Performance Networks sessions: • Admission and Congestion Control • Dynamic Provisioning and Control • Dynamic Routing • Protection and Restoration Techniques • Transport Control Protocols
Internet Services And Enabling Technologies sessions: • Network Service Design and Deployment • Peer-to-Peer Services and Technologies • Service-Enabling Protocols and Extensions
Multimedia Communications sessions: • Multimedia Content Distribution Networks • Multimedia Processing • Multimedia Streaming • Peer-to-Peer Overlay Networks • Wireless Multimedia
Network And Information Security Systems sessions: • Ad-Hoc & Sensor Networks • Biometrics & Optical Networks • DoS & Intrusion/Anomaly Detection • Encryption, Authentication & Key Management • Information & Application Security
For EXPO and ACCESS Business Forum, co-located with GLOBECOM, see next page in GRID
• The full-spectrum communications event of the
year, right here in the Bay Area • 23 Tutorials plus 4 Workshops on a broad range
of topics of current interest • Design and Developers Forum: 14 topical half-day
and full-day sessions (see next page) Early Registration Deadline: October 30th Take BART and MUNI to the conference! For Advance Program and registration information:
www.ieee-globecom.org Next Generation Networks sessions: • Broadband Access • Network and Transport Layer Protocols • Next Generation Mobile Systems • QoS and Network Security • Switching and Routing
Quality, Reliability And Performance Modeling sessions: • Control of Network Services • Peer-to-Peer Networking and Traffic Engineering • Traffic Modeling and Scheduling • Voice and Video Quality Control
Satellite And Space Communications sessions: • Performance Evaluation • Physical Layer Solutions • Resource Optimization in Satellite Systems • Routing and Mobile Networking • Solutions for Next Generation Satellite Networks
Signal Processing For Communications And Electronics sessions: • Channel Estimation and Equalization • Coding and Wireless Systems • Communications Signal Processing • Equalization • MIMO Systems • OFDM Systems • Signal Processing Algorithms • Signal Processing for CDMA
Wireless Ad Hoc And Sensor Networks sessions: • Aggregation • Coverage • Cross-Layer Design • Energy Efficiency • Localization • Power Control • QoS • Resource Allocation • Resource Management • Routing • Security • Survivability
Wireless Communications And Networking sessions: • 3G and Beyond Systems • CDMA • Cellular Systems • Coding and Modulation • Network and Resource Management • OFDM Systems • Performance Analysis • UWB System Performance • WiMax • Wireless Network Design • Wireless Network Protocols • Wireless Sensor Networks • WLAN Networks
World Class Solutions sessions: • Information Highways and Infrastructures • Pricing and Cost • Services in the Global Era
The 49th Annual
IEEE Global Telecommunications Conference
and IEEE COMMUNICATIONS EXPO
27 November – 1 December, 2006 San Francicso Fairmont Hotel
(with sessions also at the Mark Hopkins and Stanford Court Hotels)
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 8
Also at GLOBECOM this year:
ACCESS ‘06 BUSINESS FORUM
The ACCESS Business Forum runs concurrently with GLOBECOM and is included in the registration fee. It is a new multi-disciplinary executive forum focused on the broad range of “last mile” access technologies being pursued by broadband and wireless service providers, municipalities, and other user communities. Topics of the forum include technology and business issues surrounding the introduction of FTTH, xDSL, cable, broadband over power line, WiFi, WiMax, 3G and beyond in broadband access networks. It consists of a three-day program with four (4) parallel technical sessions and two plenary sessions.
ACCESS’06 Talks: • Fiber Access Systems • Broadband Operations • Optical Access Networks • Community Networks • 3G Planning and Operations • Consumer Electronics in Access Networks • Wireless Options for the Last Mile • The Business of Broadband • Supporting Triple Play Services • Global Broadband Deployments • Broadband over Power Line • What’s Next in DSL Technology? • Technology & Business Lessons from around the Globe • Metropolitan Wireless Access Networks • Last Mile Wireless Technologies and the World Wide
Research Forum (WWRF) • Ensuring QoS and Securing Converged Services • Emerging Wireless/Networking/Communication
Technologies in China • Ubiquitous Human to Human Telecommunication
Systems Design, Development and Standardization • Session Initiation Protocol (SIP): A technology for
enabling next generation networks and services
GLOBECOM EXPO As part of GLOBECOM, we feature an exposition of
key providers of technology and tools, including Components, Subsystems and Systems, Test Equipment, Hardware, Software, and Middleware. A current listing of exhibitors is on the website.
To exhibit at GLOBECOM this year, in San Francisco, please contact Connie Shaw, + 1 800 564 4220, or email:
Full information and registration:
www.ieee-globecom.org DESIGN & DEVELOPERS FORUM
A special two-day series of half- and full-day seminars at GLOBECOM, to jump-start your knowledge in these technical fields. Included in your GLOBECOM registration!
Full-day Programs: Emerging Wireless Communication Standards and Technologies Dr. Dilip Krishnaswamy (Intel) Modeling and Simulation Tools for Network Designers and Developers Jack L. Burbank (JHU/APL), William Kasch (Johns Hopkins University/APL), and Jon Ward (JHU/APL) IPTV Interoperability, from Buzzword to Reality Richard Brand (Nortel) Photonic Design Automation of Optical Commu-nication Systems Dr. Andre Richter (VPIsystems) and Dr. James D. Farina (VPIsystems)
Half-day Programs: Netflow, IPFIX, and Beyond: Integrated Routing, Traffic Analysis, and Modeling for highly Accurate Network Engineering Cengiz Alaettinoglu, Packet Design Inc. Seamless Mobility Rana P. Sircar (Wipro Technologies) Challenges and Opportunities in Software Outsourcing to China Dr. Stanley Chum (Bitek Communications Inc.) and Dr. Jason Cheng (Beijing ZGC Software Association) BT Case Study – BT's 21st Century Next Generation Networks and Systems John P. Wittgreffe (BT Group PLC) Emerging Communications/Networking Technologies and Services in India Dr. Dilip Krishnaswamy (Intel) NSF and Industry Support for Convergence Curriculum Development Tim Ryan (City College of San Francisco), Pierre Thiry (City College of San Francisco) , and James Jones (Photisis Consulting) Beyond the Hype: the Theory, Practice, and Real World Application of Quantum Cryptography Audrius Berzanskis (MagiQ Technologies) and Andrew Hammond (MagiQ Technologies) Nanotechnology in Communications Dr. Amr S. Helmy (University of Toronto)
IEEE Global Telecommunications Conference and IEEE COMMUNICATIONS EXPO
27 November – 1 December, 2006
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 9
The Winter Simulation Conference (WSC) is the premier international forum for disseminating recent advances in the field of system simulation. In addition to a technical program of unsurpassed scope and quality, WSC provides the central meeting place for simulation practitioners, researchers, and vendors working in all disciplines and in the industrial, governmental, military, and academic sectors.
Tracks Cover the Full Range of Simulation Areas Choose from 11 full tracks and 12 minitracks.
Tutorials: Introductory to Advanced Learn how simulation methodologies work in dynamic environments in these 1 1/2 -hour sessions.
Introductory • Introduction to Simulation • Modeling and Generating Probabilistic Input Processes • Designing Simulation Experiments • How to Build Valid and Credible Simulation Models • Agent-Based Modeling and Simulation • Parallel and Distributed Simulation
Advanced • Bayesian Ideas and Discrete Event Simulation • Regression Metamodels and Experimental Designs for
Simulation Practice • Inside Discrete-event Simulation Software • Black-box Algorithms for Sampling from Continuous
Distributions • Splitting for Rare-Event Simulation
Visit the Exhibit Hall for the Latest Software Solutions A special Vendor Track features presentations with case studies, software demonstrations and advanced training.
NEW! Simulation 101: Pre-Conference Workshop Saturday, Dec. 2, 9:00am-6:00pm An intensive pre-conference workshop. Topics include: single-server queue, Monte Carlo simulation, next-event simulation, output analysis, and many more topics. For more details, see the website. Separate Workshop registration is permitted. Hear Top Industry and Academic Speakers Keynote presentations include: Simulators for Human-Oriented Training William R. Swartout, USC Inst for Creative Technologies Discrete Event Models: Getting the Semantics Right Edward A. Lee, University of California, Berkeley Taming the Complexity Dragon James O. Henriksen, Wolverine Software Comprehensive and Realistic Modeling of Biological Systems David Harel, Weizmann Inst of Science Innovation in Software for Systems Biology: Is there Any? Herbert M. Sauro, Keck Graduate Institute Hotel Reservations Portola Plaza Hotel Room Rates are $145 (single) and $168 (double) plus 10.05% occupancy tax. Go to our website to make a reservation.
Early registration deadline – Save $50! Register by November 1, 2006
Visit our website, for more information:
www.wintersim.org Sponsoring Societies: ACM/SIGSIM, ASA, IEEE/CS, IEEE/SMC, IIE, INFORMS-SIM, NIST, SCS
T H E P R E M I E R I N T E R N AT I O N A L C O N F E R E N C E F O R S I M U L AT I O N P R O F E S S I O N A L S
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 10
San Jose Doubletree Hotel
2050 Gateway Place (adjacent to the Airport) BROADNETS 2006 is an international conference focusing on broadband communications, networks and systems, and covers the entire gamut of next-generation networks, communications systems, applications and services. The conference consists of the following three symposia: Wireless Communications, Networks and Systems Symposium: covers mobility, routing for multihop, multimedia QoS and traffic management, cross-layer optimization, MAC and emerging physical layer technologies (UWB, MIMO) for high-speed wireless networking. Sessions: • MAC • Multi-hop Networks • Wireless Sensor Networks • Handoffs/Adaptive Association/QoS • Wireless TCP • Cross-Layer/PHY Optical Communications, Networks and Systems Symposium: covers WDM technologies, Ethernet and MPLS integration into the optical layer, Next-Generation SONET/SDH, as well as SAN extensions over DWDM/SONET/SDH, Optical and WDM communication systems and cross-layer design. Sessions: • Optical Network Survivability • Optical Burst Switching • Modeling of Optical Networks and Systems • Distributed Computing over Overlaid Optical Networks • Traffic Grooming and Processing • Optical Network Operation and Management • Optical Network Design General Symposium: covers theory and algorithms of networking such as routing, congestion control, traffic engineering, peer-to-peer/overlay and security; architectures and protocols such as VPLS, SIP and IMS; and applications and services such as L2/L3 VPNs, VoIP, IPTV, content services and location-based services. Sessions: • Multicast and Multihop • Routing and Traffic Engineering • Performance Evaluation and Measurement • Next-Generation Internet Architecture and Services • Congestion Control and Network Reliability
Sponsored by SUNDAY October 1st Broadband Advanced Sensor Networks Workshop Grid Networks Workshop MONDAY October 2nd Guaranteed Optical Service Provisioning Workshop Optical Burst Switching Workshop TUESDAY-THURSDAY, Oct 3rd-5th Main Conference
Organizing Committee
Co-Chairs: Dr. Suresh Subramaniam, George Washington University, and Dr. Mario Freire,
University of Beira Interior, Portugal
Wireless Symposium Program Co-Chairs Dr. Aura Ganz, University of Massachusetts, and
Dr. Ragupathy Sivakumar, Georgia Tech
Optical Symposium Program Co-Chairs Dr. Byrav Ramamurthy, University of Nebraska –
Lincoln, and Dr. Ahmed Kamal, Iowa State University
General Symposium Program Co-Chairs Dr. Indra Widjaja, Bell Labs, and Dr. Hagen
Woesner, Create-Net, Italy
Registration is now Open
Special rates for full-time students • Full-conference registrants save on one- or two-day
workshop registration Visit www.e-grid.net/conf/broadnets
for full details
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 11
ICCAD focuses on the pressing problems of
today's IC designs, such as power and variability, as well as the challenges of future technologies. The program addresses both physical design and system-level issues, and has special sessions for designers and for non-CMOS technologies. ICCAD 2006 offers an ideal place for all to meet and exchange ideas about the challenges and solutions for the future as we move into the era of nanoscale integrated circuits. Both professionals and researchers active in EDA as well as practicing designers will benefit from the knowledge provided in both regular paper sessions and selected embedded tutorials.
Keynote Talks: “An Industry in Transition: Opportunities and Challenges in Next-Generation Microprocessor Design,” Phil Hester, Chief Technology Officer, AMD “Innovation in Electronic Design Automation,” Leon Stok, Director of CAD, IBM Forty Technical Sessions: Particularly noteworthy this year is the technical track on system design issues, which runs the entire length of the conference and covers issues on power and performance optimization at the system-level; thermal and variability issues in architectures; and energy minimization in realtime embedded systems. Plus sessions on physical design, placement, routing and interconnect. The Designer’s Perspectives: an all-day event of three sessions focused on linking design technology and EDA research. We have invited over 15 IC designers to share their experiences in designing for reliability and robustness; to ensure logic, functional, and system verification; and in mixed-signal design. Nano Day: ICCAD has expanded its focus to include innovative research on design, modeling, simulation, analysis, synthesis and testing of nanoscale electronic devices, circuits and systems. Two regular sessions and two embedded tutorials are dedicated to nanotechnologies.
Sponsored by:
In cooperation with:
Sunday Workshop: “Design/Technology Convergence” Four experts from industry and academia cover the theme of convergence and interaction between traditionally disparate domains in IC design and technology. Six High-caliber, Half-day Tutorials: • Enabling Variability-Aware Analysis • DFM: Impact of Manufacturing Reality on Design • Power and Thermal Challenges for 65 nm and Below • Enhancing Yield at 45nm: DFM Solutions from Different Perspectives • Transistor, Cell, and Interconnect Modeling: Basics to Advanced • Advanced Routing Techniques for Nanometer IC Designs
Plus embedded tutorials: • Challenges in Designing and Mapping Algorithms to Multi-Core Systems • UML and SystemC for Industrial ESL Design • From Dual to Multi to Many Core: Opportunities and Challenges • Design and CAD Challenges in 45nm CMOS and Beyond • Automation in Mixed-Signal Design • Emerging Nanoelectronics • Integrating Nanoelectronics, Biotechnology and MEMS/NEMS
Technology Fair: Key CAD/EDA vendors will be displaying their products and be available to answer questions. on Tuesday November 7 from 10 AM-6 PM. The forum is beneficial to ICCAD attendees for stimulating new contacts, ranging from fruitful research collaborations to networking for the future. Check out current products and technologies, as well as those just around the corner. Display space still available: contact Amy Shaklee for details: 303-530-4562, [email protected]. Substantial savings for registration by October 18th
Can’t attend the full conference? Sign up separately for the Sunday Workshop and/or Thursday Tutorials.
See the website for more details:
www.iccad.com
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 12
The Solid State Heat Capacity Laser (SSHCL) Program
Speaker: Bob Yamamoto, Lawrence Livermore
National Laboratory Time: Networking and Pizza Social at 7:00 PM,
Presentation at 8:00 PM Cost: none Place: National Semiconductor Credit Union
Auditorium, 955 Kifer Road, Sunnyvale RSVP: by email to ieeescvleos-
[email protected] Web: www.ewh.ieee.org/r6/scv/leos
Bob Yamamoto is currently the Program Manager and Project Engineer for the Solid State Heat Capacity Laser (SSHCL) program at the Lawrence Livermore National Laboratory. He received his BS in Mechanical Engineering from UC Berkeley, an MBA from Golden Gate University and is a registered professional mechanical engineer in the state of California. Mr. Yamamoto has worked in both the private sector (TRW and General Atomics) and National Labs (LLNL and LBNL) during his 29-year career. He has been the recipient of two R&D 100 awards (development of a human cancer treatment system utilizing magnetic fields and a diode-pumped laser for humanitarian mine clearing), has authored/co-authored 40 technical papers and his work has been the subject of 10 scientific magazine articles.
The Solid State Heat Capacity Laser (SSHCL)
program at the Lawrence Livermore National Laboratory (LLNL) has developed the world’s most powerful diode pumped “electric laser”. In January 2006, the SSHCL achieved 67 kW of average output laser power for short fire durations, which equates to 335 joules/pulse at our 200 Hz pulse repetition rate. As the name implies, the term “heat capacity” refers to the fact that the laser gain media stores any resultant energy in the form of heat during the lasing process, and has to subsequently be cooled off-line while another set of laser gain media are in use. Separating the lasing function from the cooling function for the laser gain media promotes straightforward and simple laser architecture, while allowing quasi-continuous laser operation.
The program has come to a major crossroad in its evolution as we prepare for its transition from a laser technology demonstration device in a laboratory setting, to a fully operational directed energy weapon capable of engaging live targets under actual battlefield conditions. In order to accomplish this, a fieldable prototype is needed that will allow those who would ultimately use the SSHCL in the battlefield to carry out laser performance and system operations testing in conjunction with reliability experiments. A 100 kW mobile SSHCL system is proposed to be built for this next step.
TUESDAY October 3SCV Lasers and Electro Optics
ANSYS Channel Partner
• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses
Ozen Engineering (408) 732-4665
[email protected] www.ozeninc.com
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 13
Overview of Next-Generation Semiconductor Manufacturing
Speaker: Dr. Jai K. Hakhu, GM of the Technology
and Manufacturing Group, Intel Time: 6:00 PM - Pizza, 6:15 PM - Lecture Cost: none Place: National Semiconductor Building 31
Auditorium, 955 Kifer Road, Sunnyvale RSVP: by email to [email protected] Web: www.ewh.ieee.org/r6/scv/eds/
Dr. Jai K. Hakhu is the Corporate VP and GM of
the Technology and Manufacturing Group at Intel Corporation.
.
In this talk, Dr. Jai K. Hakhu will review the
projected economics of the future sub-45nm semiconductor manufacturing processes.
TUESDAY October 10 SCV Electron Devices
MET Laboratories
EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)
Facilities in Union City and Santa Clara
www.metlabs.com [email protected] 510-489-6300
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 14
Convergence Challenges of Photonics with Electronics
Speaker: Dr. Edward Palen, PalenSolutions
Optoelectronic Packaging Consulting Time: 6:30 PM dinner (optional);
7:30 PM Presentation Cost: Dinner is $25 (use our PayPal system); no
cost for presentation Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101
frontage road, near Lawrence Expy), Sunnyvale
RSVP: Either through PayPal, or to Janis Karklins, [email protected]
Web: www.cpmt.org/scv
Dr. Edward Palen, P.E., specializes in creating solutions for the design, prototyping, qualification and manufacturing of optoelectronic and microelectronic devices through his business, PalenSolutions Optoelectronic Packaging Consulting. Services include packaging solutions for lower cost devices, component integration solutions, materials choices, process development, design-for-manufacturability, and generating configurations for integration of photonics with electronics, CMOS processing and assembly processing.
Prior to this Edward was Director of Advanced Process Development at Teledyne Optoelectronics for outsource manufacturing and product development for telecommunications markets. He was a lead materials and process problem solver for Mil-Sat payloads and satellite solar arrays at TRW Space & Electronics Group. At GM Hughes Electronics he was responsible for M&P troubleshooting in the business units of electro-optical data systems, satellites, radar, missiles, HRL and power products. Edward has a Ph.D. in Chemical Engineering from University of California Los Angeles and a B.Sc. in Chem. Eng. from University College London, England. He is based in the San Francisco Bay Area and consults with companies globally.
Photonics communication advantages of higher bandwidth, lower latency, and lower power consumption predestine photonics to be integrated with electronic integrated circuits. Convergent solutions are challenged by low cost requirements and CMOS compatibility. Cost requirements are 2 to 3 orders of magnitude lower than that of telecom and datacom photonic device configurations. Solutions that integrate photonics functionality with CMOS processing have yet to be widely explored. This presentation will address the challenges for convergence solutions, review state-of-the-art advances and predict future trends.
WEDNESDAY October 11
SCV Components, Packaging and Manufacturing Technology
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 15
Microwave High Power Amplifier Design and Testing
Speaker: Dr. Franco Sechi, Microwave Power Inc. Time: 6:00 - Refreshments and Social,
6:30 PM - Presentation Cost: none Place: National Semiconductor, Bldg #9,
Classroom #4, 2900 Semiconductor Dr., Santa Clara
RSVP: not required Web: www.mtt-scv.org
Dr. Franco Sechi received the doctor degree in electrical engineering from the Politecnico of Milano, Italy. He worked for 15 years at the RCA Laboratories in Princeton on R&D programs for solid-state power amplifiers. During this time he developed the first modern load-pull system, the first computer-controlled infrared microscope and the first system for measuring current and voltage microwave waveform in power transistors. He also developed the first miniature circuits on berillia substrates. In 1986 he co-founded Microwave Power Inc, a manufacturer of high performance solid-state power amplifiers where he served as President or Vice President. In 2004 Microwave Power Inc merged with AML Communications, a manufacturer of low-noise amplifiers. Dr. Sechi is presently a Vice President of AML and the General Manager of the Microwave Power Division. Dr. Sechi is author of many papers and patents. He is a member of the MTT-5 Committee on High Power Amplifiers and he is a life-member of IEEE.
Microwave power amplifiers are key components in many systems such as radars, radios, base stations and cell phones. Their performance is often a key factor in the performance of the overall system. This talk covers some of the most important aspects in the design of power amplifiers. It covers characterization techniques of active devices and design procedures for various types of power amplifiers. These include saturated amplifiers optimized for maximum output power, linear amplifiers optimized for low intermodulation, high-efficiency amplifiers optimized for maximum efficiency, and broad-band amplifiers optimized for maximum power-bandwidth product. Since the technological implementation of microwave circuits is a key factor in the performance of power amplifiers, this talk also outlines an advanced technology for the fabrication of monolithic circuits on ceramic substrates.
THURSDAY October 12SCV Microwave Theory and Techniques
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 16
One-day Symposium: The World with RFID
Speakers: From industry, VC community, government Time: 8:30 AM registration;
9:00 AM - 5:30 PM presentations Place: Biltmore Hotel, Santa Clara RSVP: See website, or email Dr. Martin Chen,
Conference Chair, [email protected] Web: www.natea.org/sv/conferences/
uthf/2006/program.php
• Dr. Krish Mantripragada, Director of SAP RFID Product Management
• Thomas Odenwald, Director of SAP RFID Research RFID Research
• Dr. Richard Swan, CTO, T3Ci (Also EPCglobal EPCIS working group co-chair)
• Dr. Elmer M. Hsu, VP & General Director of RFID Technology Center, ITRI, Taiwan
• Dr. Richard Zai, CTO, Adeptiden • Jeff Jacobsen, President of AWID • Richard Bravman, Chairman & CEO of
Intelleflex Corporation • Dr. Jimmy Li, Deputy Director, Initiative Office
for Government RFID applications, Ministry of Economic Affairs, Taiwan
• Keith Cotterill, President and Founder of Bonsai Development Corporation
RFID is a groundbreaking technology that will
serve as the replacement for UPC codes and has already been adopted by both retailer giants like WAL-Mart and Target, with the U.S. Department of Defense – the largest consumer of goods in the world – expected to follow suit. The trend of utilizing RFID to enable Real World Awareness is going to open new dimensions of applications across software and hardware. Theis one-day symposium aims to explore the solutions that are needed to enable RFID systems as well as the RFID applications.
SATURDAY October 14SCV Computer
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 17
Recollections of the Early History
of Video Tape Recording
Speaker: Fred Pfost, member of the original Ampex tape-recorder development team
Time: Refreshments at 7:30 PM, Presentation at 8:00 PM
Cost: none Place: KOMAG, 1710 Automation Parkway,
San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag
Fred Pfost spent ten years at The Ampex
Corporation in Redwood City directly after graduating from UC Berkeley in January of 1952. He was instrumental in the development of many of the audio, instrumentation, and video products that Ampex produced during his stay: the 21-channel instrumentation recorder; the 7-channel FM recorder; a semiprofessional portable audio recorder (model 600); a portable amplifier-speaker unit (model 620); an oil well logging recorder; the VR 1000 video recorder, and glass bonded ferrite heads for video recording.
Following his term at Ampex Mr. Pfost did consulting for the next 30 years doing work for 25 different local, national and international companies. He started three companies during that period and developed some breakthrough technologies that set the standards of achievement for the various industries:
(Continued, next page)
When one compares the information content
requirements for video recording versus audio recording, the ratio is about 1000 to 1. Pulling tape at high speeds is not practical when one considers tape speeds of 10 to 100 feet per second. RCA first tried 360 inches per second (30 feet per second) on 2-track recording and later lowered that to 240 ips (20 fps.) Crosby ran 100 ips (8.3 fps) using a 10 track multiplexed signal. England developed VERA that ran at 840 ips (70 fps) for 15 minutes of recording on a 21 inch diameter reel.
Ampex using a rotating head approach with frequency modulation and ran the tape at 15 ips but the head-to-tape speed was 1500 ips (when spinning at 14,400 rpm). This gave a video bandwidth of about 4 MHz which the industry wanted and needed. This also allowed 1 hour recording time on a 10.5 inch reel of 2 inch wide tape.
All of these developments were done in the early ‘50s. We originally used amplitude modulation but later changed to frequency modulation. The original FM circuitry used a high RF carrier frequency with subsequent heterodyning down to a frequency compatible with recording onto tape. This circuitry was followed by a simpler system directly modulating a multivibrator circuit running at a carrier frequency compatible with recording on tape (5 MHz).
The original rotary head orientation wrote arcuate traces across the tape. In playback we saw a scalloped output as the head crossed the tape. It took us quite a while to deduce the cause of this scalloping. We finally decided that the tape was longitudinally oriented and there was some longitudinal motion as well as transverse motion in the passage of the head across the tape in the arcuate sweep, and thus higher output near the tape edge and lower output near the middle of the head pass. This would require a large amount of automatic gain control. While I was developing this AGC circuit we decided to just change the head orientation to produce transverse paths across the entire tape, thus eliminating the variations in the output signal off-tape. (We also changed to unoriented tape.) This was the configuration used by the entire industry until the advent of the helical scan configuration some 20 years later.
(Continued, next page)
TUESDAY October 17SCV Magnetics
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 18
I was put in charge of the transducer design and video head assembly design. 15,000 “Quad” machines were produced by Ampex over the next 20 years with little change in this design. This required about 50,000 head assemblies to cover the use and replacement schedule. Head life was about 100 hours at the beginning and advanced to at least 5000 hours later with the advent of ferrite heads with glass gaps and air bearings.
Biography (continued, from prev page)
Several of Fred Pfost’s accomplishments:
• The computer industry’s first hard disc data recorder developed for Data Disc in Mtn. View -1963 (This technology was licensed to IBM and eventually became known as the Winchester Disc.)
• Stop action-instant replay hard disc video recorder developed for Mactronics in Mtn. View in 1965 (Ampex came out with their version of this device a year later.)
• Video Cartridge Recorder developed for Cartrivision in 1970
• High speed, high tension tape cartridge developed for Newell Research in 1975
• Automated Robotic Work Station (Automatic, Microprocessor Controlled Pipetter) for Infinitek (purchased by Beckman Industries) in 1985
• Automatic, spring-loaded, lever-cocked pool cue developed for Automatic Ball Driver, Inc. in 1992
Mr.Pfost has 50 U.S. Patents and hundreds of foreign patents.
He was awarded three EMMYs over the years. 1) for the Video Tape Recorder at Ampex in 1957; 2) for the Stop Action-Instant Replay Recorder at Mactronics in 1966; 3) for “Lifetime Achievement” on September 29, 2005. This last one was the first time that the Television Academy had ever given a “Lifetime Achievement” award in the technical EMMY category.
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 19
Status of Nanotechnology Initiatives at the University, State,
& Federal Levels
Speaker: Tom Kalil, Special Assistant to the Chan-cellor for Science and Technology at UC Berkeley, and formerly Deputy Assistant to President Clinton for Technology and Economic Policy
Time: Registration & light lunch 11:30 AM, Presentation & Q/A at Noon
Cost: IEEE Members and Students $5, Non-Members $10
Place: National Semiconductor Building 31, 955 Kifer Road, Santa Clara
RSVP: Please reserve by email to [email protected]
Web: www.ieee.org/nano There are a myriad of Initiatives at the University,
State, and Federal levels which are experiencing various levels of success. Tom will give a flavor of what it takes to start them and make them effective.
.
Thomas Kalil is currently the Special Assistant to
the Chancellor for Science and Technology at UC Berkeley. He has been charged with developing major new multi-disciplinary research and education initiatives at the intersection of information technology, nanotechnology, microsystems, and biology. He will also help develop a broad range of partnerships between 2 of the California Institutes of Science and Innovation (Center for Information Technology Research in the Interest of Society, California Institute for Bioengineering, Biotechnology and Quantitative Biomedical Research) and potential stakeholders in industry, government, foundations, and non-profits.
Previously, Thomas Kalil served as the Deputy Assistant to President Clinton for Technology and Economic Policy, and the Deputy Director of the White House National Economic Council. He was the NEC’s “point person” on a wide range of technology and telecommunications issues, such as the liberalization of Cold War export controls, the allocation of spectrum for new wireless services, and investments in upgrading America’s high-tech workforce. He led a number of White House technology initiatives, such as the National Nanotechnology Initiative, the Next Generation Internet, bridging the digital divide, e-learning, increasing funding for long-term information technology research, making IT more accessible to people with disabilities, and addressing the growing imbalance between support for biomedical research and for the physical sciences and engineering. He was also appointed by President Clinton to serve on the G-8 Digital Opportunity Task Force (dot force).
Prior to joining the White House, Tom was a trade specialist at the Washington offices of Dewey Ballantine, where he represented the Semiconductor Industry Association on U.S.-Japan trade issues and technology policy. He also served as the principal staffer to Gordon Moore in his capacity as Chair of the SIA Technology Committee. Tom also serves as a consultant for organizations such as the Semiconductor Industry Association, Internet2, CommerceNet, and the “Digital Promise” initiative proposed by Newton Minow and Larry Grossman.
Tom received a B.A. in political science and international economics from the University of Wisconsin at Madison, and completed graduate work at the Fletcher School of Law and Diplomacy. He is the author of articles and op-eds on S&T policy, nanotechnology, nuclear strategy, U.S.-Japan trade negotiations, U.S.-Japan cooperation in science and technology, the National Information Infrastructure, distributed learning, and electronic commerce.
TUESDAY October 17SCV Nanotechnology
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 20
Fall Banquet and Presentation
Speaker: Michael R. Peevey, President, California Public Utilities Commission
Time: 5:00 PM networking/social, 6:30 PM dinner, 7:30 PM presentation
Cost: Full-course dinner - IEEE Members $20, non-members $25 (thru Sept 17), $5 more afterwards(full-time students: $10)
Place: Monte Cristo Cafe, 4 Embarcadero Center, San Francisco
RSVP: Please see our website for menu selection and registration form
Web: ewh.ieee.org/r6/san_francisco/pes
Michael R. Peevey joined the California Public Utilities Commission in 2000 at the height of the energy crisis and went right to work forging strong bonds with sister agencies, such as the California Department of Water Resources, the Independent System Operator, the California Energy Commission, and the California Power Authority to deal with the crisis.
He encouraged the group to focus on assuring that California has adequate energy resources and transmission facilities to support its growing population and improving economy. Prior to joining the Commission, Mr. Peevey served as President of NewEnergy Inc. and President of Edison International and Southern California Edison Company. Mr. Peevey holds both a Bachelor and Master of Arts degree in economics from the University of California, Berkeley. He is married to Assembly member Carol J. Liu (D-La Cañada Flintridge). They have three children.
We asked the President of the California Public Utilities Commission, Michael Peevey, to talk about the Commission’s accomplishments this year and the major issues he sees for the electric industry in the coming one.
Please register (see the website for form) for this
banquet by September 17, and choose the entre you desire (Wild King Salmon with vegetables and fennel; Wood oven roasted Chicken with rosemary and garlic red potatoes; Risotto with vegetables, parmesan & thyme). We look forward to a great and informative evening! Validated parking is available in Embarcadero Center Garage.
TUESDAY October 17SF Power Engineering
Protecting Your Intellectual Property
Speaker: R. Michael Ananian, Perkins Coie LLP Time: 7:00 PM presentation Cost: none Place: KeyPoint Credit Union, 2805 Bowers Ave.,
Santa Clara RSVP: not required Web: www.CaliforniaConsultants.org
R. Michael Ananian is a Partner at Perkins Coie,
LLP, in Menlo Park. He specializes in intellectual property and patent strategic counseling, as well as patent, trademark and copyright procurement. He has worked extensively with inventions in the semiconductor, computer, software, communications, medical and mechanical device, e-commerce and Internet fields. He is an IEEE member, and has Bachelors and Masters degrees in EE.
A tutorial on intellectual property and patents will be presented. This will include a discussion of the legal and technical requirements for filing and obtaining a patent in the United States and internationally, and some discussion of inventor rights, and the possible obligations to assign inventions to employers as employees and as consultants.
Recognizing and protecting intellectual property created in one's work is important for independent inventors, employees and consultants. Rights to inventions may vary from state to state, and may be modified by contract or agreement. Our speaker will describe the patenting process, and will address at least some of the issues associated with inventor rights during his tutorial on intellectual property law. There will also be a discussion of intellectual property, with a focus on patents for inventions. The requirements for writing, filing and prosecuting patent applications in the United States Patent & Trademark Office, and the importance of the written description and claims, will be presented. The importance of prior-art and possible bars to patentability will also be presented.
TUESDAY October 17SCV Consultants' Network of Silicon Valley
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road,
Palo Alto 94303 [email protected]
www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835
O c t o b e r 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 2 1
MEMS for Medical Applications Speaker: Dr. Alissa Fitzgerald, A.M. Fitzgerald &
Associates, LLC Time: ptional dinner with the speaker, Stanford
Hospital cafeteria at 6:15 PM; presentation at 7:30 PM
Cost: none Place: Clark Center Auditorium, Stanford Hospital
and Medical School (parking free after 4 PM)
RSVP: not required Web: www.ieee.org/scv/embs /
Alissa Fitzgerald founded A.M. Fitzgerald & Associates, LLC in 2003 to provide custom prototyping and R&D services to clients developing MEMS devices. Her company has consulted on MEMS sensors for automotive, industrial, and medical applications. Dr. Fitzgerald was previously employed by Sensant Corporation, where she worked on the development of micromachined ultrasound transducers for medical imaging applications. She has also been employed by the Jet Propulsion Laboratory and Orbital Science Corporation. Dr. Fitzgerald received her bachelor and master degrees from the Massachusetts Institute of Technology and her doctorate from Stanford University, all in the discipline of Aeronautics and Astronautics.
MEMS, or microelectromechanical systems, is a catch-all term for a manufacturing technology that enables the production of devices with micron-scale features. Although the technology developed from the semiconductor industry, it is quickly evolving beyond silicon-based devices to include microsystems made from glass, silicon carbide, diamond, and flexible polymers. The capability to create micron-sized devices from biocompatible materials, that may also be readily interfaced with microelectronics, opens up great opportunities for the development of novel medical devices.
In this talk, an overview of MEMS manufacturing approaches will be presented, in order to acquaint the audience with the huge potential for MEMS in medical applications. The products and approaches of some companies who are developing MEMS-based medical devices will also be presented and discussed.
WEDNESDAY October 18SCV Engineering in Medicine and Biology
O c t o b e r 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 2 2
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 23
Clock Generation and Distribution in High-Performance Processors
Speaker: Stefan Rusu, Intel Corp. Time: 6:30 PM social, 7:00 Presentation Cost: none Place: Business With Pleasure, 216G Mt. Hermon
Rd., Scotts Valley RSVP: to Marcelo Siero at [email protected] Web: www.ee.com/clock
Stefan Rusu received the MSEE degree from the Polytechnic Institute in Bucharest, Romania. He first joined Intel Corp. in 1984 working on data comm-unications integrated circuits. In 1988 he joined Sun Microsystems working on microprocessor design with a focus on clock and power distribution, packaging, standard cell libraries, CAD and circuit design methodology. He re-joined Intel Corp. in 1996, working on the clock and power distribution, cell library, I/O buffers and package for the first Itanium® processor. He is presently a Senior Principal Engineer in Intel's Enterprise Microprocessor Group, leading the technology and special circuits design team for the Xeon® Processors Family. His technical interests are high-speed clocking, power distribution, I/O buffers, power and leakage reduction, and high-speed circuit design techniques. Stefan has authored or co-authored more than 70 papers on VLSI design methodology and microprocessor circuit technology. He holds 25 U.S. patents with several more pending. He is a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences and an Associate Editor of the IEEE Journal of Solid-State Circuits.
This presentation is an overview of clock generation and distribution techniques, with emphasis on high-performance microprocessor designs. We describe practical techniques to reduce clock skew and jitter, with examples from several industry leaders. As power consumption is a limiting factor for all modern designs, low-power clock distribution techniques and flip-flop implementations will be reviewed. Several clock-related design-for-test and debug techniques will be described with practical implementation examples.
THURSDAY October 19 Monterey Bay Subsection
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 24
HANA: the High-definition AV Network Alliance
Speaker: Jack Chaney, VP of Business Development,
Samsung Time: pizza and drinks at 6:30 PM;
Presentation at 7:00 PM Cost: $5 for IEEE members, $10 for guests Place: HP Oak Room (Building 48), 19447
Pruneridge Avenue, Cupertino RSVP: not required Web: www.ieee.org/scvce
The High-Definition Audio-Video Network Alliance is the first cross-industry collaboration to address the end-to-end needs of connected, high-definition, home entertainment products and services.
SCV Consumer Electronics
TUESDAY October 24
Valon Technology, LLC
valontechnology.com
RF and Wireless Product Design & Development
- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness
Redwood City (650) 369-0575
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 25
Trapped by MTBF? Speaker: Fred Schenkelberg, OPS A La Carte and
FMS Reliability Time: Refreshments and social at 6:30 PM;
Presentation at 7:00 PM Cost: none Place: Hewlett-Packard Building 48, Oak Room,
19111 Pruneridge Ave, Cupertino RSVP: not required Web: ewh.ieee.org/r6/scv/rl/events.htm
Fred Schenkelberg is a senior consultant/
technical director at both FMS Reliability and OPS A La Carte. Fred joined the ranks of independent consultants to focus on reliability engineering in June 2004. He currently works with a wide variety of clients using reliability assessments as a starting point to develop detailed reliability plans and programs. He also uses his reliability engineering and statistical knowledge to design and conduct accelerated life tests.
Fred previously worked at HP starting in February 1996 in Vancouver, WA. In January 1998, he joined HP’s Electronic Systems Technology Center, ESTC, in Palo Alto, where he co-founded the HP Product Reliability Team. In that role, Fred was responsible for the consulting, training, and community-building aspects of HP's Product Reliability Program. He was also responsible for research and development on selected product reliability management topics at HP.
Fred has a Bachelors of Science in Physics from the United States Military Academy and a Masters of Science in Statistics from Stanford University. Fred is an active member of the RAMS Management Committee and is currently the IEEE Reliability Society Santa Clara Valley Chapter Vice Chair and ASQ Reliability Division Treasurer.
.
Mean Time Between Failure, MTBF, is the worst
four letter acronym. It leads to misunderstanding, misinterpretation and misinformed decisions. And MTBF is widely used. It is embedded in countless industries and ‘the way’ of discussing reliability. As you already know, MTBF is the parameter for the exponential life distribution and it has common estimation techniques. MTBF is the key element of modeling, planning, test development and vendor selection, among many other elements.
In this presentation, let’s review the common issues around MTBF and how these problems have led to significant errors. Then let’s explore what to do given that organizations and industry will continue to use MTBF. What questions should you ask? How should you clearly explain the issues and proper use of MTBF and related probabilities? And what basic calculation should you conduct every time you run across MTBF?
Within the world of reliability engineering and statistics there has rarely been a more widely difficult metric to properly understand. Many engineers and managers do not take the time to really understand basic statistics. With very simple formulas, arguments, and definitions, we can help our respective industries advance product reliability. Used properly, there is nothing wrong with MTBF. Let’s talk about how to use MTBF properly and encourage others to do the same.
WEDNESDAY October 25SCV Reliability
October 2006 V i s i t us a t w w w . e - G R I D . n e t Page 26
Full-Day Seminar: Has The Time Arrived For Manufacturing High-
K/Metal Gates?
Speakers: see program, at right Time: Registration: 9-9:30 AM;
Sessions 9:30 AM - 6:00 PM Cost: none (includes lunch, refreshments); free
parking Place: Hotel Valencia, 355 Santana Row, San
Jose RSVP: Send registration information to Jeff Watt,
Altera, [email protected] Web: www.ewh.ieee.org/r6/scv/eds/
IEEE EDS Chapter and Applied Materials will host a symposium to illuminate challenges and solutions surrounding high-K/metal gate technology. A distinguished speaker line-up from both industry and academia will share their insights and future outlooks regarding this critical topic. Critical questions to be answered are:
- Can scaling continue without high-K/metal gate? - Which high-K/metal gate pairings will work best? - How much will high-K/metal gate cost?
We hope that you will be able to join us for what is certain to be a provocative discussion !
This symposium is co-sponsored by the local IEEE SCV EDS Society Chapter and by Applied Materials. The Symposium Chair is Dr. Jeff Watt of Altera, who is also the 2005/2006 Chairman of the local IEEE SCV EDS Society Chapter. The Applied Materials co-sponsor is Dr. Reza Arghavani.
The currently scheduled symposium speakers and speaker topics: 9:30 AM Introduction and Opening Remarks · Jeff Watt, Altera 10:00 AM The High-K/Metal Gate Industry Landscape · Dr. Raj Jammy, Sematech 11:00 AM Materials, Depositions, and Requirements · Professor Paul McIntyre, Stanford 11:30 AM Interface Engineering for High-K/Metal Gate Integration · Professor Veena Misra, North Carolina State
12:00 Noon to 1:00 PM - Lunch Break (no cost)
1:00 PM High-K/Metal Gate Activities at IBM · Dr. Michael Chudzik, IBM 2:00 PM High-K/Metal Gate Integration Challenges · Dr. Sri Samavedam, FreeScale Semiconductor 3:00 PM The High-K/Metal Gate Equipment Landscape · Thomas Mele, Applied Materials 3:30 PM Integration Challenges for NVM · Dr. Nirmal Ramaswamy, Micron Technology 4:00 PM High-K/Metal Gate Activities at AMD · Dr. Rusty Harris, AMD 4:30 PM Closing Remarks · Jeff Watt, Altera 4:45 PM Speaker Interviews and Reception · Network with Symposium Attendees 6:00 PM Adjourn
THURSDAY October 26
SCV Electron Devices
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Copper Die Bumps (First Level Interconnect) and
Low-K Dielectrics in 65nm High-Volume Manufacturing
Speaker: Andrew Yeoh, Logic Technology
Development, Intel Corporation Time: Buffet lunch at 11:45 AM; Presentation at
12:15 Cost: Lunch is $15 (preregistered, or use our
PayPal system) or $20 at the door Place: Ramada Inn, 1217 Wildwood Ave (Fwy
101 frontage road, near Lawrence Expy), Sunnyvale
RSVP: Either through PayPal, or to John Jackson, Analog Devices, [email protected]
Web: www.cpmt.org/scv
Dr. Andrew Yeoh has been at Intel Corporation for 9 years. He is presently Integration Group Leader for the passivation/C4/assembly area in the 65nm and 32nm technology nodes at Intel’s Logic Technology Development division located in Hillsboro, Oregon. In this role, Dr. Yeoh is responsible for developing the process integration of die-package I/O interconnects.
Prior to joining the process integration group, Dr. Yeoh was a CMP module engineer responsible for process development in the areas of oxide, tungsten, and copper planarization.
Dr. Yeoh received his PhD in Materials Science and Engineering from the University of Texas at Austin in 1995. His academic background is in the areas of tribology, electromagnetic propulsion, and non-ferrous metallurgy.
The benefits of copper die-side bumps for flip chip
application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD’s) into back end interconnect architectures have made integrating copper bumps challenging, primarily due to low-k ILD cracks and delamination. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump CD floor, continued scaling of passivation openings that is driven by silicon interconnect line widths, a drastically simplified underbump metallization scheme, and extensions to higher I/O densities.
With copper bumps, underbump metallization (UBM) now functions solely as an adhesive layer for the die-side bump, as the bump and silicon interconnect metals are identical. The barrier requirements of the UBM stack are eliminated since the highly reactive tin (Sn) constituent from the package-side solder is naturally isolated from the die-level copper interconnects by the die bump. Copper also brings a new geometry to the first level interconnect (FLI), where non-reflowed columns replace the familiar mushroom bumps that are reflowed into spheres. Eliminating die bump reflow simplifies the fab process flow in addition to enabling higher bump count per unit area.
Integrating copper bumps requires added measures in the silicon architecture as the stiffer metal more directly transmits chip-attach stresses into the die when compared to SnPb. Assembly and reliability results that demonstrate the robustness of the overall architecture will be discussed. Fracture-mechanics-based modeling supports the empirical data and estimates a sizeable stress reduction within the low-k layers from utilizing SiO2.
Enabling copper bumps brings to the table significant electrical benefits to design, scaling, and fabrication flow simplification. Beginning with the 65nm technology and incrementally going forward, each improvement that copper die bumps allow will be realized.
THURSDAY October 26
SCV Components, Packaging and Manufacturing Technology
September 2006 V i s i t us a t w w w . e - G R I D . n e t Page 28
Electro-Optic A/D Converters Speaker: Prof. John P. Powers, Naval Postgraduate
School Time: Networking and Pizza Social at 7:00 PM,
Presentation at 8:00 PM Cost: none Place: National Semiconductor Credit Union
Auditorium, 955 Kifer Road, Sunnyvale RSVP: by email to [email protected] Web: www.ewh.ieee.org/r6/scv/leos
John Powers is a Distinguished Professor Emeritus of Electrical Engineering at the Naval Postgraduate School (NPS). He received his BSEE from Tufts University, his MSEE from Stanford University, and his PhD in Electrical Engineering from the University of California, Santa Barbara. He has been with the Department of Electrical and Computer Engineering at the Naval Postgraduate School since 1970. He also served as Chairman of that department from 1987-1990 and 2002-2005, was Dean of Faculty for NPS from 1994-1995 and Dean of Science and Engineering from 1995-1996. In 1974-75 he was an Exchange Scientist at the University of Paris, working in the area of acoustic imaging. Professor Powers has taught in the areas of electro-optics, fiber optics, and electronics. He is the author of two editions of Introduction to Fiber Optic Systems (McGraw-Hill) and the editor of Acoustical Imaging, Vol. 11 (Plenum Press). Professor Powers’ research interests are in naval applications of fiber optics, acousto-optics, scalar-wave diffraction, and acoustic imaging.
We seek to design and test an analog-to-digital converter that can digitize a signal with a 10-GHz bandwidth at a resolution of 10 bits. An electro-optic modulator with a pulsed laser input, used as a sampler, requires pulses on the order of a picosecond in duration with a temporal stability of 10s of femtoseconds. We have constructed a mode-locked fiber laser to use in the sampling of the rf wave. This talk will discuss the features and performance of this laser. We will also briefly discuss parallel digitization of the samples based on the symmetric number system as well as preliminary thoughts on an optical implementation of a sigma-delta converter for these wide bandwidth signals.
SCV Lasers and Electro Optics
TUESDAY November 7
September 2006 V i s i t us a t w w w . e - G R I D . n e t Page 29
Calibration and Error Correction Techniques for Network Analysis
Speaker: Dr. Doug Rytting, Agilent Technologies Time: Refreshments and social at 6:00 PM;
Presentation at 6:30 PM Cost: none Place: National Semiconductor Bldg #9, Classroom
#4, 2900 Semiconductor Dr., Santa Clara RSVP: not required Web: www.mtt-scv.org
Doug Rytting graduated with a BSEE from Utah State University and MSEE from Stanford University.
He joined HP in June 1966 and worked on virtually all microwave network analyzers introduced since 1966. He was a hardware designer on the 8405 vector voltmeter and 8410 network analyzers, and hardware project manager of the 8540, 8541, and 8542 automatic network analyzers, as well as section manager of the 8505, 8754 RF network analyzers, and the 8510C microwave network analyzer family. He managed the development of the 8340 microwave synthesized sources and the startup of the microwave CAE design software, and provided technology support for the RFMT (RF Manufacturing Test) system products.
Most recently he supported the architecture design and analysis of the new Microwave Performance Network Analyzer family and served as director of the Microwave Measurement Center of Technology at Agilent Technologies, developing new measurement methods, instrument and system block diagrams, error correction techniques, and key microwave components for future products.
Doug Rytting is now retired and consulting on microwave measurements and calibration techniques.
Doug is heavily involved in error correction methods, accuracy analysis, nonlinear measurements, and general measurement techniques in the microwave industry. He has served on various advisory boards and committees for universities, government agencies, and industry.
The accuracy of Vector-Network-Analyzer (VNA)
measurements depends critically on calibration and error correction techniques. This talk will cover the evolution of conventional VNA calibration methods from the start of network analysis through the development of new calibration methods for waveform and large-signal analysis. Included will be the original SOLT (Short-Open-Load-Through) methods, the newer self-calibration techniques like TRL, LRL and Unknown-Thru, and the strengths and weaknesses of these various VNA calibration approaches. The talk will conclude with a discussion of new state-of-the-art extensions of the traditional VNA calibration strategy for calibrated waveform measurements at microwave frequencies capable of capturing the both the temporal and large-signal behavior of microwave and digital devices.
THURSDAY November 9SCV Microwave Theory & Techniques
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The Technology of Magnetic Hard Disk Drive Storage
Speaker: Ed Grochowski, Executive Director, IDEMA
USA Time: Refreshments at 7:30 PM,
Presentation at 8:00 PM Cost: none Place: KOMAG, 1710 Automation Parkway,
San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag
Ed Grochowski began his career with IBM’s microelectronic silicon activity in New York and later joined the IBM Almaden Research Center in California where his interests included hard disk drive and component technology, and their evolutionary trends. Dr. Grochowski holds nine patents and has authored and presented numerous articles on magnetic disk drives and component technology, including a website of storage trend charts. These charts are regarded as industry road maps and are widely quoted as references. He earned a Ph.D. from New York University (1971) in Chemical/Materials Engineering. Ed currently is the Executive Director of IDEMA USA (International Disk Drive Equipment and Materials Association), a non-profit hard disk drive organization serving the storage industry. He chairs the conferences and technical committee for DISKCON USA and DISKCON Asia Pacific, as well as the IDEMA Symposium series, and coordinates the 4K byte long sector standards committee for IDEMA. Ed is also a member of the IEEE and is a well known speaker on hard disk drive trends and technology. After 41 years with IBM, Dr. Grochowski retired and next joined Hitachi GST. Besides his IDEMA responsibilities, he is presently active as a storage industry consultant. His prior and present clients include IDC (International Data Corp.) and TrendFocus.
Today’s hard disk drive has evolved through miniaturization into a small storage device with up to 750 Gigabytes of storage, with the promise of a one terabyte product appearing in the very near future. This storage device, based on reduced form factors and large capacity, is well suited for today’s storage applications, from large server units to mobile and consumer based products. The technology which made this storage device possible includes advanced read/write heads which now include PMR, thin film media, PRML data channels and many other features which have added to the usefulness of HDD’s while significantly reducing price per gigabyte. An analysis of this technology will be given as well as projections of where newer advances could extend the applications of magnetic storage products to the future. A comparison of HDD storage to alternative non-volatile technologies including Flash memories and MRAM devices will be discussed. A major part of the presentation will include trend charts, with technical rationale, to assist in the projecting the future.
TUESDAY November 14SCV Magnetics
VOICE COIL MOTORS Design - Control - Fabricate - Test
J. Arthur Wagner, Ph.D. 1649 Fair Orchard Ave.
San Jose, CA 95125
[email protected] (408) 269-7044 (408) 206-3049 cell
