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Improving ESD Robustness of pMOS Device WithEmbedded SCR in 28-nm High-k/Metal

Gate CMOS ProcessChun-Yu Lin, Member, IEEE, Pin-Hsin Chang, and Rong-Kun Chang

Abstract— A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD)robustness has been proposed and implemented in a 28-nmhigh-k/metal gate CMOS process. An additional p-type ESDimplantation layer was added into the pMOS to realize theproposed device. The experimental results show that the proposeddevice has the advantages of high ESD robustness, low holdingvoltage, low parasitic capacitance, and good latchup immunity.With better performances, the proposed device was more suitablefor ESD protection in a sub-50-nm CMOS process.

Index Terms— Electrostatic discharge (ESD), pMOS,silicon-controlled rectifier (SCR).

I. INTRODUCTION

THE scaling in CMOS technologies to improve deviceperformances has attracted interest. As CMOS tech-

nologies keep scaling down, thin oxide thickness ofMOS transistors has made ICs to be sensitive to the elec-trostatic discharges (ESD). To protect the IC products againstthe ESD damages, ON-chip ESD protection devices must beequipped for the pads that may be stressed by ESD. Althoughhigh-k dielectric has been introduced in sub-50-nm CMOStechnologies, the MOS transistors are still sensitive toESD [1], [2]. Moreover, because the average cost of a diein sub-50-nm technologies is expensive, it is important tooptimize ESD protection devices to have a high ESD robust-ness within a limited cell area.

To discharge the high ESD energy without causingdamage to ICs, the turn ON of parasitic bipolar junctiontransistors (BJTs) inherent in nMOS or pMOS transistorsplays an important role [3]–[7]. The nMOS and the pMOSwith gate connected to source have been used as theESD clamp devices, that is to say, gate-grounded nMOS(GGnMOS) and gate-VDD pMOS (GDpMOS) [3], [4].The device cross-sectional views of the GGnMOS and the

Manuscript received October 28, 2014; revised January 23, 2015;accepted January 24, 2015. This work was supported in part by GlobalUnichip Corporation, Taiwan, in part by the Ministry of Science andTechnology, Taiwan, under Contract MOST 103-2220-E-003-001 and ContractMOST 103-2221-E-009-197-MY2, in part by the Biomedical ElectronicsTranslational Research Center, National Chiao Tung University, Hsinchu,Taiwan, and in part by the National Taiwan Normal University, Taipei, Taiwan.The review of this paper was arranged by Editor R. M. Todi.

C.-Y. Lin and R.-K. Chang are with the Department of Electrical Engi-neering, National Taiwan Normal University, Taipei 10610, Taiwan (e-mail:cy.lin@ieee.org).

P.-H. Chang is with the Institute of Electronics, National Chiao TungUniversity, Hsinchu 30010, Taiwan.

Digital Object Identifier 10.1109/TED.2015.2396946

Fig. 1. (a) Schematic circuit and (b) cross-sectional view of the GGnMOS.

Fig. 2. (a) Schematic circuit and (b) cross-sectional view of the GDpMOS.

GDpMOS are shown in Figs. 1 and 2, respectively. Whenthe GGnMOS or the GDpMOS is under ESD stress, theparasitic n-p-n (n+, p-well, and n+) or p-n-p (p+, n-well,and p+) BJT will be triggered to discharge ESDcurrent. Since the electron mobility is higher thanthe hole mobility in the CMOS technologies, theturn-ON efficiency of n-p-n embedded in nMOS is muchbetter than that of p-n-p embedded in pMOS. Therefore,the nMOS-based ESD clamp devices have the better ESDrobustness [6]. The pMOS-based ESD clamp devices can beused with no snapback or low-leakage applications, becausethe leakage current of nMOS was often larger than that ofpMOS in advanced CMOS technologies [6], [7]. Of course,the device dimension of pMOS should be larger than that ofnMOS to achieve the same ESD robustness.

The silicon-controlled rectifier (SCR) device has beenreported to be useful for ESD protection due to its highESD robustness, small device size, and excellent clamp-ing capabilities (low holding voltage and small turn-ON

resistance) [8]–[10]. Besides, the SCR device can be safelyused without latchup danger in advanced CMOS technologieswith low supply voltage [11]. The ESD protection designfor I/O cells with embedded SCR [12] and the high-voltageoutput arrays with embedded SCR [13] have been reported.To enhance the turn-ON efficiency of pMOS-based ESD clampdevice, a novel ESD protection design using pMOS devicewith an embedded SCR is proposed in this brief.

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TABLE I

DEVICE DIMENSIONS AND MEASUREMENT RESULTS

Fig. 3. Cross-sectional view of the proposed device.

II. PROPOSED ESD PROTECTION DESIGN

The new ESD protection design is proposed for theself-protecting outputs or the stand-alone ESD protectiondevice. The device cross-sectional view of the proposed pMOSdevice with the embedded SCR is shown in Fig. 3, wherethe p-ESD denotes the p-type ESD implantation [14]. Thisimplantation was typically used to improve the turn-ON abilityof the GGnMOS. In this design, additional n+ region is addedinto the cathode side of the proposed device. This n+ isseparated from the p+, and the silicide blocking is used onthe surface of this n+ and p+. Besides, the p-ESD layerat the cathode side is used to isolate the n-well and n+ region.The SCR path consists of p+/p-ESD, n-well, p-ESD, and n+.The p-ESD layer at the anode side is used to enlarge the SCRpath. As ESD zapping from the anode to the cathode, thepMOS device will quickly breakdown to discharge the initialESD current through the parasitic p-n-p, and then the positive-feedback regenerative mechanism of p-n-p (p+/p-ESD, n-well,and p+/p-ESD) and n-p-n (n-well, p-ESD, and n+) results inthe SCR path highly conductive to discharge the major ESDcurrent. Under normal circuit operating conditions, the pMOSis turned OFF and the SCR is also kept OFF.

III. VERIFICATION IN SILICON

To verify the proposed design in silicon chip, a 28-nmhigh-k/metal gate CMOS process is used in this brief.

All the GGnMOS (Fig. 1), GDpMOS (Fig. 2), and theproposed device are implemented. Each test device isdrawn in multifinger style with a finger width of 20 µm.The channel widths of the test devices are selected to be120 µm (six fingers) and 360 µm (18 fingers). The channellengths are kept at 0.13 µm. All these dimensions of the testdevices are listed in Table I. The GGnMOS, GDpMOS, and theproposed device are implemented with ground-signal-groundpads to facilitate on-wafer RF measurement.

A. ESD Robustness

The human-body-model (HBM) ESD robustness is tested.The failure criterion is defined as the I–V curve seen betweentest pads shifting over 30% from its original curve after ESDstressed at every ESD test level. All ESD robustness of thetest devices are measured and listed in Table I. Accordingto the measurement results, the proposed devices with120- and 360-µm widths can pass 5- and 8-kV HBMESD tests, respectively, while the GGnMOS can only pass0.5- and 1.5-kV HBM ESD tests, respectively. The GDpMOSeven cannot pass 0.5-kV HBM ESD tests.

B. TLP and VF-TLP I–V Characteristics

A transmission-line-pulsing (TLP) system with a 10-nsrise time and a 100-ns pulsewidth is used to evaluate thetrigger voltage (Vt1), holding voltage (Vhold), turn-ON resis-tance (RON), and secondary breakdown current (It2) of thetest devices in the time domain of HBM ESD event. TheTLP-measured I–V curves of the test devices are shownin Fig. 4. The proposed devices with 120- and 360-µm widthscan achieve the TLP-measured It2 of 3.43 and 4.87 A, whilethe GGnMOS have 0.60 and 1.25 A, and the GDpMOS haveonly 0.03 and 0.09 A. The Vhold values of the proposed devicesare ∼1.7 V. The Vhold values of the proposed devices exceedVDD (0.9 V in the given CMOS process), which is safe fromlatchup event. The proposed ESD protection design with lowerVhold and higher It2 is more suitable for ESD protection.

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LIN et al.: IMPROVING ESD ROBUSTNESS OF pMOS DEVICE WITH EMBEDDED SCR 3

Fig. 4. Measured TLP I–V curves.

Fig. 5. Measured VF-TLP I–V curves.

Another very fast TLP (VF-TLP) system with 0.2-ns risetime and 1-ns pulsewidth is also used to capture the transientbehavior of the test devices in the time domain of charged-device-model (CDM) ESD event. The VF-TLP-measuredI–V curves of the test devices are shown in Fig. 5. TheVF-TLP-measured It2 of the proposed devices with 120- and360-µm widths are 2.49 and 4.05 A, respectively, while thoseof the GGnMOS/GDpMOS are 1.94/1.68 A and 4.44/3.47 A,respectively. In the proposed devices, most of the currentsare discharged through the pMOS, so the VF-TLP-measuredIt2 values of the proposed design are similar to those of theGDpMOS. Even so, the measurement results show that allthe test devices are fast enough to be turned ON under thefast CDM-like ESD-transient events. All TLP-measured andVF-TLP-measured I–V characteristics are listed in Table I.

C. Parasitic Capacitance

If the ESD protection device is adopted for theself-protecting output, the parasitic capacitance should beconsidered. The two-port S-parameters of the test devices aremeasured on the wafer. The parasitic effects of the pads andmetal routing have been removed using the deembedding tech-nique [15]. The parasitic capacitance of each test device wasextracted from the S-parameters. Fig. 6 shows the extractedparasitic capacitances of the test devices, including GGnMOS,GDpMOS, p+/n-well diode (DP), n+/p-well diode (DN),and proposed devices. At 5 GHz, the parasitic capacitancesof the proposed devices with 120- and 360-µm widths are90 and 234 fF, respectively, while those of the GGnMOS/GDpMOS are 202/173 fF and 607/480 fF, respectively.

Fig. 6. Measured parasitic capacitances.

Fig. 7. Measured TLP I–V curves of the proposed device (W = 120 µm)under different trigger currents.

D. Trigger Mechanism

To investigate the relationship between the trigger currentand the Vt1, an additional trigger pad is connected to the drainterminal of pMOS device with the embedded SCR. The dctrigger current (Itrig) was injected into the trigger pad of theproposed device when measuring the TLP I–V curves. Fig. 7shows the TLP-measured I–V curves of the proposed deviceunder different trigger currents. The Vt1 of the proposed devicecan be further reduced with the larger trigger current. If thetrigger current is continually increased, the Vt1 of the proposeddevice will be reduced to a value close to its Vhold. Besides,the trigger current will not degrade the Vhold, RON, and It2of the test devices. According to this measurement result, anadditional trigger circuit, such as an RC inverter, can be usedto reduce the Vt1 of the proposed device. Besides, the triggercircuit can prevent the p-ESD from floating during the normalcircuit operation.

E. Failure Analysis and Discussion

After ESD tests, the scanning electron microscope (SEM)was used to find the failure locations. Fig. 8 shows the SEMphotographs of the proposed devices with 120- and 360-µmwidths after HBM ESD tests. The failure points are locatedat the SCR paths and the gate oxide. The SEM photographsindicated that the proposed device with 120-µm width can beuniformly turned ON under HBM ESD stress. However, theproposed device with 360-µm width can be further improvedby optimizing its metal routing. After adding the metal line to

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4 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 8. SEM photos of the proposed devices. (a) W = 120 µm and(b) W = 360 µm after HBM ESD tests.

the edge of the proposed device with 360-µm width, the HBMESD robustness and the It2 should be increased. Besides, theRON could be further decreased by shortening the length ofdrain (p+) of pMOS device with the embedded SCR to shortenthe SCR path.

IV. CONCLUSION

The new ESD protection device of the pMOS with embed-ded SCR has been designed, fabricated, and characterized ina 28-nm high-k/metal-gate CMOS process. As verified on thesilicon chip, the proposed device with 120-/360-µm width hasa 5-/8-kV HBM ESD robustness and a 90.1-/233.5-fF parasiticcapacitance, which are much better than those of the GGnMOSor GDpMOS. Therefore, the proposed device can be a bettersolution for ESD protection in a sub-50-nm CMOS process.

ACKNOWLEDGMENT

The authors would like to thank Prof. M.-D. Ker, NationalChiao Tung University, Taiwan, and W.-T. Wang, GlobalUnichip Corporation, Taiwan, for their great help during thedesign and measurement. The authors would also like to thankHanwa Electronic Industry Corporation Ltd., Japan, for theirhelp to the TLP measurement.

REFERENCES

[1] Y. Yang et al., “Degradation of high-k/metal gate nMOSFETs underESD-like stress in a 32-nm technology,” IEEE Trans. Device Mater.Rel., vol. 11, no. 1, pp. 118–125, Mar. 2011.

[2] T.-H. Chang, Y. Hsu, T. Tsai, J.-C. Tseng, J. Lee, and M.-H. Song,“High-k metal gate-bounded silicon controlled rectifier for ESD protec-tion,” in Proc. 34th EOS/ESD Symp., 2012, pp. 1–7.

[3] S. Dong, X. Du, Y. Han, M. Huo, Q. Cui, and D. Huang, “Analysisof 65 nm technology grounded-gate NMOS for on-chip ESD protectionapplications,” Electron. Lett., vol. 44, no. 19, pp. 1129–1130, Sep. 2008.

[4] M.-D. Ker, S.-H. Chen, and C.-H. Chuang, “ESD failure mechanismsof analog I/O cells in 0.18-µm CMOS technology,” IEEE Trans. DeviceMater. Rel., vol. 6, no. 1, pp. 102–111, Mar. 2006.

[5] E. R. Worley, “New ballasting method for MOS output drivers and powerbus clamps,” in Proc. 43rd Annu. IEEE Int. Rel. Phys. Symp., Apr. 2005,pp. 458–461.

[6] P.-Y. Tan, I. Manna, Y.-C. Tan, K.-F. Lo, and P.-H. Li, “A study of highcurrent characteristics of devices in a 0.13 µm CMOS technology,” inProc. EOS/ESD Symp., 2002, pp. 186–193.

[7] C.-T. Yeh, Y.-C. Liang, and M.-D. Ker, “PMOS-based power-rail ESDclamp circuit with adjustable holding voltage controlled by ESD detec-tion circuit,” in Proc. 33rd EOS/ESD Symp., 2011, pp. 1–6.

[8] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic dischargeprotection design with SCR-based devices in CMOS integrated circuits,”IEEE Trans. Device Mater. Rel., vol. 5, no. 2, pp. 235–249, Jun. 2005.

[9] H. Hwang and T. Tang, “Silicon controlled rectifier device for electro-static discharge protection,” U.S. Patent 7 910 998, Mar. 22, 2011.

[10] C.-H. Huang, C.-C. Shih, H.-S.-K. O, and Y. Liu, “Fast and compactSCR ESD protection device for high-speed pins,” U.S. Patent 7 471 493,Dec. 30, 2008.

[11] G. Boselli, V. Reddy, and C. Duvvury, “Latch-up in 65 nm CMOStechnology: A scaling perspective,” in Proc. 43rd Annu. IEEE Int. Rel.Phys. Symp., Apr. 2005, pp. 137–144.

[12] M.-D. Ker and K.-H. Lin, “ESD protection design for I/O cells withembedded SCR structure as power-rail ESD clamp device in nanoscaleCMOS technology,” IEEE J. Solid-State Circuits, vol. 40, no. 11,pp. 2329–2338, Nov. 2005.

[13] J.-H. Lee et al., “Novel ESD protection structure with embedded SCRLDMOS for smart power technology,” in Proc. 40th Annu. IEEE Int.Rel. Phys. Symp., Apr. 2002, pp. 156–161.

[14] M.-D. Ker, C.-H. Chuang, and W.-Y. Lo, “ESD implantations for on-chipESD protection with layout consideration in 0.18-µm salicided CMOStechnology,” IEEE Trans. Semicond. Manuf., vol. 18, no. 2, pp. 328–337,May 2005.

[15] L. F. Tiemeijer and R. J. Havens, “A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-qualityinductors and high-speed transistors,” IEEE Trans. Electron Devices,vol. 50, no. 3, pp. 822–829, Mar. 2003.

Chun-Yu Lin (M’09) received the Ph.D. degreefrom the Institute of Electronics, National ChiaoTung University, Taiwan, in 2009.

He is currently the Assistant Professor withthe Department of Electrical Engineering, NationalTaiwan Normal University, Taiwan, and also theSecretary-General of Taiwan ESD Association.His current research interests include ESD protectiondesigns and biomimetic circuit designs.

Pin-Hsin Chang received the B.S. degree from theDepartment of Electrical Engineering, Feng ChiaUniversity, Taiwan, in 2012, and the M.S. degreefrom the Institute of Electronics, National ChiaoTung University, Taiwan, in 2014. Her currentresearch interests include ESD protection designs.

Rong-Kun Chang received the B.S. degree fromthe Department of Applied Electronics Technol-ogy, National Taiwan Normal University, Taiwan,in 2013. His current research interests include ESDprotection designs.