IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012 463

5-V Buck Converter Using 3.3-V Standard CMOSProcess With Adaptive Power Transistor Driver

Increasing Efficiency and Maximum Load CapacityHyunseok Nam, Youngkook Ahn, and Jeongjin Roh, Senior Member, IEEE

Abstract—A high-voltage-tolerant buck converter with a noveladaptive power transistor driver is proposed in this paper. In orderto minimize the RON of the cascode power transistor, the proposedscheme uses optimized and separated driving voltages for bias ofthe pMOS and nMOS power transistors. This increases not only theconversion efficiency, but also the maximum allowable load currentfor the transistor driver with small layout size, when compared tothe buck converter with the earlier scheme. The measurementsshow that when the supply voltage is 2.5 V and the load currentis 150 mA, the efficiency of the buck converter with the earlierscheme is 82%, whereas the efficiency of the buck converter withthe proposed scheme is 92%, showing a maximum improvementof 10%. The designed buck converter uses the 0.35-μm-thick gateoxide CMOS process, and at 2.5–5 V of voltage, can supply up to380 mA of load current. The total chip size is 2.7 mm2 .

Index Terms—Adaptive power transistor driver, cascode powertransistor, conduction loss, dc–dc converter, maximum allowablevoltage.

I. INTRODUCTION

A LONG with the continuous decrease in the size of high-performance transistors, the supply voltage of highly in-

tegrated systems has also decreased, resulting in higher relia-bility, lower leakage current, and lower dynamic power. Fig. 1shows the changes in supply voltage, according to the scaling-down of the CMOS process [1]–[4]. As shown in this graph,the supply voltage decreases along with the scaling down ofthe CMOS process, which applies to the operation of smallertransistors in a stable voltage range. However, if the transistorsoperate in a high supply voltage range, three major problems canresult [5].

1) Oxide breakdown: With electrical fields being appliedabove and below the oxide, the current may flow throughthe oxide causing oxide breakdown.

2) Oxide degradation: Hot carriers, which obtain energyfrom the high electric field applied between the source

Manuscript received July 27, 2010; revised October 22, 2010; acceptedOctober 29, 2010. Date of current version December 16, 2011. This workwas supported by Mid-career Researcher Program through National ResearchFoundation (NRF) grant funded by the Ministry of Education, Science and Tech-nology (MEST) (No. 2010-0022808). The chip fabrication and computer-aideddesign (CAD) tools were supported by the IC Design Education Center (IDEC).Recommended for publication by Associate Editor Y. C. Liang.

The authors are with the Department of Electrical Engineering, HanyangUniversity, Ansan 426-791, Korea (e-mail: jroh@hanyang.ac.kr).

Digital Object Identifier 10.1109/TPEL.2010.2091287

Fig. 1. Power supply voltage scaling with technology generation.

and the drain, collide with the silicon lattice. Some hotcarriers penetrate the oxide around the drain, degradingthe oxide.

3) Leakage current: Avalanche breakdown occurs due to thehigh reverse-bias voltage of the p-n junction, which gen-erates a reverse diode current.

Many studies to resolve these problems are currently ongoing.Several solutions have been proposed: a technological solutionusing multiple oxides [6]–[8], the use of extended drain devicesin baseline CMOS technology [9], and control of the voltagedifference between transistors under the maximum voltage usingnovel circuit solutions. Systems designed with circuit solutionsprovide greater advantages in performance and cost, comparedto other methods [10]–[12].

Recently, since the supply voltage used in portable devices hassignificantly decreased, the difference between supply voltageand battery voltage has increased considerably. Moreover, sincehigh system integration and performance require more supplycurrent, an inductor-type switching converter, with higher con-version efficiency, is suitable for supplying dc voltage to thesedevices [13]–[16]. Therefore, this paper discusses the designof a buck converter, which is an inductor-type switching con-verter that converts a voltage higher than the maximum allow-able voltage to the lower voltage required in a specific system.The proposed buck converter significantly improves efficiencyand maximum allowable load current, compared to the buckconverter with the earlier scheme.

Section II presents the operations of other recently proposedschemes and Section III discusses the details of the circuit pro-posed in this paper. Section IV presents experimental results.

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464 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 2. Conventional buck converter.

Fig. 3. Earlier high-voltage-tolerant buck converter.

Finally, Section V summarizes the information presented in thispaper and presents concluding remarks.

II. EARLIER HIGH-VOLTAGE-TOLERANT BUCK CONVERTERS

Fig. 2 shows the circuit of a conventional buck con-verter [17], [18]. It consists of power transistors, gate drivers,and a pulsewidth modulation/pulse frequency modulation(PWM/PFM) controller. If this circuit is designed in an ad-vanced CMOS process, the problems mentioned in Section Ican occur due to the low maximum allowable voltage of thetransistor.

To resolve these problems, a circuit using novel techniques[11], [12] has recently been proposed, as shown in Fig. 3. Thecircuit consists of a PWM/PFM controller, a voltage regulatorthat supplies power to the controller, cascode power transis-tors, and gate drivers. The technique used in [12] includes onlya PWM controller. The circuit in Fig. 3 is designed in sucha way that even if the supply voltage (VDDH ) is higher than

the maximum allowable voltage (Vmax ), the difference in nodevoltages will not exceed Vmax . Furthermore, the PWM/PFMcontroller can be stably operated by using the VDDL (<Vmax)that is equal to the VDDH/2 produced through the voltage reg-ulator. This concept was used in [11] and [12] with the high-voltage-tolerant regulators, which are shown in Fig. 4. Fig. 4(a)consists of Amp1, Amp2, MP1, MN1, Cm1 (decoupling ca-pacitor), and ΔV/2 for decreasing the quiescent current of thevoltage regulator when the VDDL remains at a constant voltage.Fig. 4(b) consists of a reference block, ADCs, digital buffers,DACs, Cm2 , and Cm3 (decoupling capacitors). The amplifier,ADC, and DAC in Fig. 4(b) use the inverter, which not only in-stantaneously supplies a large output current, but also consumesvery little current when idle.

In the earlier schemes, however, when VDDH and VDDL be-came lower, since VDDL was always equal to VDDH/2, the ef-ficiency of the buck converter decreased due to the increasedRON of the cascode power transistor [19], [20]. If the widthof the cascode power transistor increased, larger gate driverswere required to solve this problem. The switching loss wasincreased and a larger decoupling capacitor to remove instanta-neous switching noise was needed.

The buck converter proposed in this paper uses cascode powertransistors to solve the reliability problem as well as an adap-tive power transistor driver to change the driving voltage levelaccording to the supply voltage, both of which increase the effi-ciency and maximum allowable load current. Furthermore, thetotal chip area is decreased because the sizes of the decouplingcapacitor and power transistor are reduced.

III. PROPOSED HIGH-VOLTAGE-TOLERANT BUCK CONVERTER

A. System Design

Fig. 5 shows a block diagram of the proposed high-voltage-tolerant buck converter. The proposed scheme consists of cas-code power transistors, an adaptive power transistor driver, aPWM/PFM controller, a class A-type voltage regulator to sup-ply power to the PWM/PFM controller, and a bandgap referencecircuit that supplies constant bias voltage and current to the en-tire circuit. Unlike the earlier schemes, the proposed schemeis designed to separate the bias voltage driving the cascodepower transistor from the power supplied to the PWM/PFMcontroller. This separation of power allows stable operation ofthe PWM/PFM controller, free from the large switching noisegenerated by the driving of the power transistor. Since the regu-lator for the controller used in the proposed scheme needs onlyto supply constant voltage and current to the PWM/PFM con-troller, a class A-type voltage regulator has been designed withcascode power transistors (MP3, MP4). Here, Cc and Cm areused as the compensation capacitor and the decoupling capaci-tor of the voltage regulator, respectively. The VDDL is generatedby using a class A-type voltage regulator. In this design, theVDDL is set at 1.9 V. Therefore, even if the VDDH changes, thePWM/PFM controller receives a constant VDDL . In this way, itimproves the characteristics of the buck converter by minimiz-ing the effects of amplifier offset and channel length modulationdue to large changes in supply voltage (VDDH ).

NAM et al.: 5-V BUCK CONVERTER USING 3.3-V STANDARD CMOS PROCESS 465

Fig. 4. Earlier high-voltage-tolerant voltage regulators for VDDL . (a) Class B-type voltage regulator [11]. (b) Class AB-type push–pull regulator [12].

Fig. 5. Block diagram of the proposed high-voltage-tolerant buck converter with adaptive power transistor driver.

B. Proposed Adaptive Power Transistor Driver

Fig. 6 shows the concept and the architecture of the pro-posed scheme, which has following advantages over the earlierschemes.

1) The proposed scheme reduces the total chip area becauseit has a lower RON , even with a small-sized cascode powertransistor.

2) The proposed scheme also reduces the size of the powertransistor driver because of the small size of the cascode

power transistor. This improves conversion efficiency dueto reduced switching loss.

3) The proposed scheme reduces the size of the decouplingcapacitor.

Fig. 6(a) and (b) shows the operation of the proposed scheme.The proposed scheme adjusts the Bias-p and Bias-n voltages ap-propriately, according to the changes in the VDDH . Specifically,when the VDDH is higher than Vmax , the PS1 and PS3 switchesare turned on and the NS1 and PS2 switches are turned off. The

466 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 6. Proposed scheme. (a) VDDH > Vm ax . (b) VDDH < Vm ax . (c) Circuit implementation.

V pR and V nR voltages are supplied to the gate drivers, and thegate biases of the MP2 and the MN2 power transistors throughPS1 and PS3 switches, respectively. If the VDDH keeps decreas-ing and becomes lower than Vmax , the PS1 and PS3 switches areturned off, the NS1 and PS2 switches are turned on, and Bias-pand Bias-n have VSS and VDDH (<Vmax ).

The implementation of this circuit is presented in Fig. 6(c).It has cascode power transistors (MN1, MN2, MP1, and MP2)and gate drivers to drive the power transistors. The circuit hasbias generators for reference voltages, which are at the samevoltage levels as the V pR and V nR, and two dual-loop push–pull linear regulators, which are voltage regulators, to supplystable reference voltages to the gate drivers [21]. Furthermore,the circuit has a power transistor control circuit that prevents thecurrent from shorting out, when the nMOS and pMOS powertransistors are activated simultaneously, and changes the signalsfrom the PWM/PFM controller to an appropriate voltage fordriving the power transistors. In addition, the circuit has switches(PS1, PS2, PS3, and NS1) and a switch controller that controlsthe Bias-p and Bias-n voltages, depending on the state of theVDDH .

The MC1 and MC2 transistors are used as decoupling capac-itors to prevent voltage changes in the Bias-p and the Bias-ndue to instantaneous switching current. Fig. 7 shows the cur-rent flowing into the Bias-p node and voltage waveforms. Asshown in Fig. 7(a), the current is divided into two components,defined as I1 and I2 . I1 is the current flowing from the PD nodewhen the MND transistor is turned on. I2 is the current flowingthrough the parasitic capacitor CGD2 due to rapid changes atthe SW node. The Biasp voltage may become too high due tothese two currents. Fig. 7(b) shows the voltage waveforms ofFig. 7(a). This high Bias-p voltage momentarily increases the

operating voltage of the transistors connected to this node overVmax and increases the RON of the power transistor MP2, whichresults in decreased efficiency and a reliability problem. There-fore, an appropriate decoupling capacitor is required to solvethis problem.

Fig. 8 shows the bias generators for V p and V n voltages andthe two dual–loop push–pull linear regulators for the V pR andV nR voltages used in Fig. 6(c). As shown in this figure, theV p voltage changes, together with the changing VDDH . It isdesigned using resistors (R1, R2) and a decoupling capacitor(C1). The V n voltage is designed using a current source, aresistor (R3), and a decoupling capacitor (C2) to generate aconstant voltage, even if the supply voltage changes.

Fig. 9 shows the switch controller circuit. The V s voltagegenerated using resistors R1 and R2 is compared through a com-parator with the VR voltage generated using a constant currentsource and R3. The comparator has hysteresis characteristics toprevent abnormal operation of the comparator due to noise. Thedesigned circuit is restricted in its operation by Hbias1. Assum-ing that the OUTb node is high and the OUT node is low, in orderfor the OUT node to become high, the OUTb node voltage mustsatisfy the equation: VOUT b ≤ VDDH − |Vth·p4 |. Furthermore,since the minimum voltage of VOUTb is Hbias1 + |Vth·.p1 |

Hbias1 ≤ VDDH − |Vth·p1 | − |Vth·p4 |. (1)

The magnitude of the Hbias1 voltage must be determined inconsideration of (1). Positive feedback does not work unless (1)is satisfied. Here, the voltage ranges of Switch1 and Switch2 arefrom the VSS to the VDDH .

Fig. 10 shows the simulation result of the proposed schemeusing the aforementioned circuits. As shown in this figure, whenthe VDDH is high, the Bias-n and Bias-p voltages are identical to

NAM et al.: 5-V BUCK CONVERTER USING 3.3-V STANDARD CMOS PROCESS 467

Fig. 7. (a) Current flowing into the Bias-p node and (b) voltage waveforms.

Fig. 8. Bias generators and dual-loop push–pull linear regulators.

Fig. 9. Switch controller.

Fig. 10. HSPICE simulation result of the proposed scheme.

the V n and V p voltages, respectively. When the VDDH is verylow, the Bias-n and Bias-p voltages are identical to the VDDHand VSS , respectively. Even if the VDDH decreases, the proposedscheme can maintain the low RON of the power transistor dueto sufficient gate-to-source voltage.

Fig. 11 compares the changes in RON according to the VDDHthrough HSPICE simulation between the earlier scheme and theproposed scheme. As shown in Fig. 11(a), when the VDDH issmaller than Vmax , the RON of the cascode pMOS power tran-sistor using the earlier scheme continuously increases, whereasthe RON of the cascode pMOS power transistor using the pro-posed scheme is reduced significantly. Furthermore, as shownin Fig. 11(b), when the VDDH decreases, the RON of the cascodenMOS power transistor using the earlier scheme continuouslyincreases, whereas the RON of the cascode nMOS power tran-sistor using the proposed scheme not only maintains a constantbut also is significantly reduced.

468 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 11. HSPICE simulation of RON . (a) RON of the cascode pMOS power transistor. (b) RON of the cascode nMOS power transistor.

C. Efficiency and Maximum Allowable Load Current

As shown in Fig. 11, with the earlier scheme, the RONquickly increases when the supply voltage decreases from 3.1 to2.5 V. On the other hand, the proposed scheme provides smallerRON in the same supply voltage range (2.5–3.1 V), thus greatlydecreasing conduction loss, compared to the earlier scheme, re-sulting in significantly improved total efficiency. Furthermore,since the proposed scheme has lower turn-on resistance in therange of 2.5–3.1 V than in the range of 3.1–5 V and can greatlydecrease switching loss at lower VDDH , the proposed schemehas higher efficiency in the range of 2.5–3.1 V than in the rangeof 3.1–5 V.

In addition, the proposed scheme can supply more load cur-rent to the systems than the earlier schemes due to the small RONof the power transistor. Fig. 12(a) shows the switching modelof the power stage. RL is the model of the load system and Reqis the equivalent resistance, which is affected by the duty ratio,RON ·p , and RON ·n , is the equivalent resistance. Fig. 12(b) showsthe inductor current variation according to the Req variation. I1 ,I2 , and I3 are the inductor currents, which come under Req1 ,Req2 , and Req3 , respectively. Here, Req1 < Req2 < Req3 . t1 ,t2 , and t3 represent the on-time of the pMOS power transistorand tmax is the maximum on-time of the pMOS power transis-tor for stable operation of the buck converter. Therefore, if theon-time exceeds tmax , the buck converter may oscillate or fail.

When the pMOS power transistor turns on, the inductorcurrent increases with the slope of the (VDDH − Io(Req +RDCR) − Vo)/L, and when the nMOS power transistor turnson, the inductor current decreases with the slope of the(VSS − Io(Req + RDCR) − Vo)/L. Therefore, from the slope

Fig. 12. (a) Switching model of the power stage. (b) Inductor current variationaccording to the Req .

of the inductor current

Ihigh =VDDH − Io(Req + RDCR) − Vo

Ltn + Ilow ,

n = 1, 2, 3. (2)

NAM et al.: 5-V BUCK CONVERTER USING 3.3-V STANDARD CMOS PROCESS 469

Fig. 13. Micrograph of the fabricated chip.

Because tmax is a maximum value of tn

tmax >(Ihigh − Ilow )L

VDDH − Io(Req + RDCR) − Vo. (3)

Then, the maximum load current can be expressed as follows:

Io <VDDH − Vo − (Ihigh − Ilow )L/tmax

(Req + RDCR). (4)

Therefore, since the maximum of Io is increased when Reqcontinues to decrease, the proposed scheme can significantlyimprove the load current limitation problem existing in earlierschemes.

IV. EXPERIMENTAL RESULTS

The performance and experimental results of the proposedhigh-voltage-tolerant buck converter are summarized here. Ituses L = 4.7 μH, C = 4.7 μF, and fixes 1.8 V to the outputof the buck converter. The proposed high-voltage-tolerant buckconverter was fabricated in a standard 0.35-μm 3.3-V CMOSprocess. Fig. 13 shows the micrograph of the designed high-voltage-tolerant buck converter.

In Fig. 14(a), waveforms of the buck converter, when a verylow VDDH is applied, are shown in the PFM mode. The testconditions are VDDH = 3 V and load current = 10 mA. As shownin Fig. 14(a), since the VDDH is lower than Vmax , the PD and NDsignals, which are the driving signals of the power transistors,have a voltage range between VSS and VDDH . In Fig. 14(b),when a VDDH that is higher than the maximum allowable voltagein the process is applied to the proposed scheme, the resultingwaveforms of the buck converter are as shown in the PFM mode.The test conditions are VDDH = 5 V and load current = 10 mA.Because the VDDH is higher than Vmax , the PD signal range is2.5–5 V, and the ND signal range is 0–2.7 V.

Fig. 15 shows the changes in output voltage according to loadcurrent. As shown in this figure, PFM and PWM operations are

Fig. 14. Measured PD and ND waveforms with (a) VDDH = 3 V and(b) VDDH = 5 V.

Fig. 15. Measured load-transient response.

used for light load and heavy load, respectively, to maximizeefficiency. The test conditions are VDDH = 4.5 V and loadcurrent = 15–280–15 mA. The output voltage shows a well-controlled waveform for both modulation periods. When theload current changes abruptly, no significant overshoot can beobserved from the output voltage. This does not mean that thefeedback control is perfect; it simply means that the ripple of

470 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 1, JANUARY 2012

Fig. 16. Comparison of efficiency according to the supply voltage (load cur-rent = 150 mA).

Fig. 17. Comparison of efficiency and maximum load current (VDDH = 2.5V).

TABLE IPERFORMANCE COMPARISON

the output voltage during the PFM is so large that the overshootcan be easily masked by the PFM ripple voltage.

Fig. 16 shows the measurement of the efficiency of the buckconverter, according to VDDH under heavy load (150 mA). Tocompare the performance of the proposed and earlier schemes, atest pin, which can control output voltages of the bias generators,is implemented. If a test pin is connected with VDD or VSS , thecontrol circuit selects the proposed scheme or the earlier scheme,respectively. The proposed scheme exhibits approximately 10%higher efficiency compared to the earlier schemes at low supplyvoltage. In addition to high efficiency, as shown in Fig. 17, theproposed scheme increases the range of maximum allowableload current because the lower RON decreases the conductionloss generated from the power transistors. Table I summarizesthe measurement results of the proposed scheme compared toearlier published results.

V. CONCLUSION

This paper presents a novel high-voltage-tolerant buck con-verter with high efficiency and high integration. Because theproposed scheme changes the driving voltage of the power tran-sistor according to the supply voltage, it increases not only con-version efficiency, but also the maximum allowable load currentfor transistor driver with small layout size when compared toearlier schemes. The performances of both the proposed andearlier schemes are compared and summarized in Section IV ofthis paper. From these results, we concluded that the proposedscheme is significantly more effective when designing a buckconverter for a high-voltage-tolerant circuit using the advancedCMOS process.

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Hyunseok Nam received the B.S. degree in elec-tronic and electrical engineering science from Hal-lym University, Chuncheon, Korea, in 2005, the M.S.degrees in electrical engineering and computer sci-ence, in 2007 from Hanyang University, Ansan, Ko-rea, where he is currently working toward the Ph.D.degree.

His research interests include power managementcircuits and mixed-signal integrated circuits.

Youngkook Ahn received the B.S. degree in elec-tronic and electrical engineering science from Kyeon-sang University, Jinjoo, Korea, in 2006, the M.S.degrees in electrical engineering and computer sci-ence, in 2009 from Hanyang University, Ansan, Ko-rea, where he is currently working toward the Ph.D.degree.

His research interests include power managementcircuits and mixed-signal integrated circuits.

Jeongjin Roh (SM’10) received the B.S. degree inelectrical engineering from the Hanyang University,Seoul, Korea, in 1990, the M.S. degree in electricalengineering from the Pennsylvania State University,University Park, in 1998, and the Ph.D. degree incomputer engineering from the University of Texas,Austin, in 2001.

From 1990 to 1996, he was a Senior CircuitDesigner at the Samsung Electronics, Kiheung, Ko-rea for several mixed-signal products. From 2000 to2001, he was at the Intel Corporation, Austin, TX.

Since 2001, he has been with the faculty of the Hanyang University, Ansan, Ko-rea. His current research interests include oversampled delta–sigma convertersand power management circuits.