R. Kass N64-4 1IEEE08/NSS

Radiation-Hard/High-Speed Data Transmission Using Optical Links

W. Fernando, K.K. Gan, A. Law, H.P. Kagan, R.D. Kass, J. Moore, D. S. SmithThe Ohio State University

Richard KassThe Ohio State University

OUTLINEIntroduction-ATLAS/Pixel Detector/SuperLHC

System Architecture-issues 0.13 μm opto-chip prototype

Summary

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The Current ATLAS Pixel Detector

A pixel module contains:1 sensor (2x6cm) ~40000 pixels

16 front end (FE) chips 2x8 array

Flex-hybrid1 module control chip (MCC)There are ~1744 modules~1.85m

Pixel Detector:ATLAS’s Inner most charged particle tracker Measures (x,y,z) to ~30 mPixel detector is based on silicon Pixel size 50m by 400 m ~80 million pixelsRadiation hardness is an issue must last ~ 10 years

ATLAS is a detector at CERN designed to study 14 TeV pp collisions Detector upgrade planned for Super-LHC in 2016

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Present Pixel Opto-link ArchitectureCurrent optical link of pixel detector transmits signals at 80 Mb/sOpto-link separated from FE modules by ~1m

transmit control & data signals (LVDS) to/from modules on micro twisted pairs

Use PIN/VCSEL arrays

Use 8 m of rad-hard/low-bandwidth SIMM fiber fusionspliced to 70 m rad-tolerant/medium-bandwidth GRIN fiber Simplify opto-board and FE module production Sensitive optical components see lower radiation level than modules PIN/VCSEL arrays allow use of robust ribbon fiber

VCSEL: Vertical Cavity Surface Emitting Laser diodeVDC: VCSEL Driver CircuitPIN: PiN diodeDORIC: Digital Optical Receiver Integrated Circuit

optoboard holds VCSELs, VDCs, PINS

~80m

optoboard

~1m

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SLHC Pixel Opto-link Architecture

Present

Proposed

Opto-pack

HousingPin arrayDORICVCSELVDC

2cm

published in: NIM A 555 (2005)

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R&D Issues for Super-LHCRadiation hardness of all components PIN array VCSEL arrays Opto-board ASICs: VDC, Receiver (replace DORIC)

SI (PIN) @ SLHC (3000fb-1)1.5 x 1015 1-MeV neq/cm2

2.6 x 1015 p/cm2 or “69 Mrad” for 24 GeV protons GaAs (VCSEL) @ SLHC (3000fb-1)

8.2 x 1015 1-MeV neq/cm2

1.6 x 1015 p/cm2 or “34 Mrad” for 24 GeV protonsIncreased speed of componentsReceiver: 160Mb/s or 320Mb/sVDC: 3.2Gb/sClock multiplier: generates fast clock for 3.2Gb/s serializer

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640 Mb/s VCSEL Driver

3.2 Gb/s VCSEL Driver

640 MHz clock multipliers(4 x 160 and 16 x 40 MHz)

PIN receiver/decoder(40, 160, 320 MHz)

Designed with 0.13μm process

Opto-Chip Prototype

1.5 mm x 2.6 mm

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Testing the 0.13um Opto-Chips

Use CERN’sT-7 beamline, 24 GeV protons to test:

Chips were tested in our lab at OSU Chips were irradiated to SLHC dose at CERN

8 VDCs 4 “Slow” & 4 “Fast” 4 Clock Multipliers 4 Purely Electrical Receivers 4 Receivers + 4 Si PIN (Taiwan)

Due to limitations in the cabling could only operate DORIC/VDC at 40Mb/s Designed special card to allow testing of PLL at 640MHz

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VDC: VCSEL Driver Chip

Slow VDC 640 Mb/s

Fast VDC 1 Gb/s

Fast VDC 3.2 Gb/s

PLCCpackage

Both blocks (fast/slow) work in preliminary study BER < 10-13 at 3.2 GB/s driving Optowell VCSEL

LVDS-like receiver works at high speed (3.2Gb/s)

Need detailed study with smaller/no package

2.5Gb/s VCSEL+macro-packagenot optimal

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VDC

Fast VDC

Irradiation resultsVDC driving 25Ω with constant Iset and 40MHz input signal

bright

dim

power supply

Decrease in drive current can be compensated by increase in Iset

Slow VDC

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Receiver

Properly decodes 40, 80, & 160 Mb/s BPM signals recovered clock jitter < 250/100/50 ps for 40/80/160 MHz (<1%)

LVDS-like output has good amplitude and baseline Amplitude 475mV, baseline=0.625V rise/fall time 125 ps

No significant degradation after irradiation to SLHC dose

BER Threshold

40 Mb/s BER threshold for 1 bit error/s

PIN Receiver/Decoder Chip

Peak to Peak thresholdssupply current @1.5V

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Clock MultiplierNeed to multiply recovered clock 160MHz/40MHz up to 640MHz for serialization.Both 4x and 16x clock multipliers workLow Clock jitter < 8 ps (0.5%)No change in current consumption after irradiation BUT: Two of the four chips lost lock during irradiation & needed power cycling to resume operation at 640 MHz Could not reproduce this behavior at OSU on test bench

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Summary

First 0.13μm chip submission mostly successful Full characterization of pre/post irradiation in progress Waiting for the chips to “cool off” so they can be shipped from CERN to OSU Aim for next chip submission in winter 2009 Will irradiate the chips at CERN, summer 2009

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extra slides

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Setup for Irradiation in Shuttle at CERN

Opto-boards

Rad hard optical fibers

25 meter optical fiber

Remotely moves in/out of beam

CERN T7 CERN T7

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Radiation-Hardness of PINGb/s Responsivity (A/W)

GaAs Pre Post

ULM 4.25 0.50 0.13

AOC 2.5 0.60 0.19

Optowell 3.125 0.60 0.25

Hamamatsu G8921 2.5 0.50 0.32

Si

Taiwan 1.0 0.55 0.33

Hamamatsu S5973 1.0 0.47 0.37

Hamamatsu S9055 1.5/2.0 0.25 0.21

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Real Time Monitoring in T7 Beam TestReal time testing of opto-board system using loop-back setup

dataDORIC

clockPIN

VDCVCSEL

Opto-board

VDCVCSEL

bi-phase marked optical signal

decoded data

decoded clock

Signal routed back to opto-baord via test board

attached to 80-pin connector & test board

Bit error test setupat CERN’sT-7 beamline24 GeV protons

Compare transmitted and decoded data

measure minimum PIN current for no bit errors

Measure optical power

In control room

25m optical

fiber cable

In beam

Two VCSEL arraysfrom same vendor per opto-board

Opto-Chip setup