IJSETR389-07

8/12/2019 IJSETR389-07

http://slidepdf.com/reader/full/ijsetr389-07 1/4

www.semargroups.org,

www.ijsetr.com

ISSN 2319-8885

Vol.02,Issue.14,

October-2013,

Pages:1549-1552

Copyright @ 2013 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.

High Performance of HDLC Protocol Design using OCP based on Xilinx FPGAK.NAGESH

1, SHARIQ-UL-PERWEZ

2,V.HARIBABU

3

1PG Scholar, Dept of ECE, MallaReddy Institute of Technology & Science, Hyderabad, AP-INDIA,

E-mail: [email protected]. 2PG Scholar, Dept of ECE, MallaReddy Institute of Technology & Science, Hyderabad, AP-INDIA,

E-mail: [email protected] Prof, Dept of ECE, MallaReddy Institute of Technology & Science, Hyderabad, AP-INDIA,

E-mail: [email protected].

Abstract: A digital communication techniques must adapt the packet based data transmission. HDLC is a specification for the

data link layer and lies between the physical layer and the network layer. The data link layer, of which HDLC is a part of, is

responsible for passing the data between two nodes on the same network. HDLC takes packets from the network layer andattaches address control and data integrity information to them. An efficient bus protocol for the core communication between

IP blocks is OCP. The Open Core Protocol (OCP) reduces the design time, design risk and manufacturing costs for the SoC

designs. This paper focus on the design and implementation of bus bridge using OCP master and HDLC Receiver protocol. The

designed HDLC-OCP protocol is carried out using Verilog HDL.

Keywords: HDLC, OCP, Verilog, Bus Bridge.

I. INTRODUCTION

Networks are defined by the ISO using the OSI

reference model. This model consists of seven layers which

detail different aspects of a network. HDLC is a

specification for the data link layer and lies betweenPhysical layer and Network layer. The data link layer, of

which HDLC is a part of, is responsible for passing the data

between two nodes on the same network. HDLC takes

packets from the network layer and attaches address, control

and data integrity information to them. Once formatted the

packets are sent down the wire using physical layer. The

physical layer specifies how the bits are transmitted. This

can include but is not limited to the data signal encoding,

the connector form factor and pin out and the cabling

interfaces. When the packet is received using the Physical

layer the packet frames up the seven layer and arrives at the

application.

High Level Data Link Control (HDLC) is one of the

bit-oriented synchronous communication protocols. It

retains powerful error detection capability as well as

efficient and simultaneous transmission characteristic.

HDLC have been used in various high-speed data

transmission systems. Implementation of HDLC usually

uses software programming or ASIC devices. Software

programming can be modified depends on different

applications of HDLC. It uses more CPU resources for

program running, so software programming is often used in

single channel and low-speed signal processing systems.

ASIC devices are simple but they are lack of flexibility, the

ASIC devices have the defects; there are various versions of

HDLC protocol which makes it hard for ASIC devices

focusing on some specific purpose to cover all these versions,data storage capacity in ASIC is limited. Open Core Protocol

interface addresses communication between the functional

units that comprise a system on a chip. OCP provides

independence from bus protocols without having to sacrifice

high performance access to on chip inter connects. The

interface boundary defined by the reusable IP cores without

regard for the ultimate target system. OCP unifies all inter-

core communications, including sideband control and test

harness signals. OCP synchronous unidirectional signaling

produces simplified core implementation, integration and

timing analysis. OCP eliminates the task of repeatedly

defining, verifying, documenting and supporting proprietary

interface protocols. The OCP readily adapts to support newcore capabilities. Clearly delineated design boundaries enable

cores to be designed independently of other system cores

yielding definitive, reusable IP cores with reusable

verification and test issues.

Present work is divided as follows: Section II presents the

related work; section III presents the Architecture view,

explanation of each block presented; section IV is dedicated to

results and V section is for concluding the work.

mailto:[email protected]

mailto:[email protected]

8/12/2019 IJSETR389-07


K.NAGESH, SHARIQ-UL-PERWEZ,V.HARIBABU

International Journal of Scientific Engineering and Technology Research

Volume.02, IssueNo.14, October-2013, Pages:1549-1552

II. RELATED WORK

A. HDLC Frame

Figure1. HDLC Frame

HDLC protocol embeds information in data frame that

allows devices to control data flow and correct errors.HDLC is an ISO standard developed from the synchronous

data link control (SDLC) standard proposed by IBM in

1970’s. HDLC uses frame to indicate an entity of data (or a

protocol data unit) transmitted from one station to another.

The HDLC protocol format as described in fig no1 with data

sizes of each field. HDLC is a bit-oriented, synchronous

data link layer protocol; it specifies data encapsulation on

synchronous serial links.

1. Flag Field

Every frame on the must begin and end with a flag

sequence field (F). Stations attached to the data link must

continually listen for a flag sequence. The flag sequence isan octet looking like 01111110. Flags are continuously

transmitted on the link between frames to keep the link

active. The time between the transmissions of actual frames

is called the interframe time fill. The intertime fill is

accomplished by transmitting continuous flags between

frames. HDLC is a code transparent protocol.

2. Address Field

The Address field identifies the primary or secondary

stations involvement in the frame transmission or reception.

Each station on the link has a unique address.

3. Control Field

HDLC uses the control field (C) to determine how to

control the communication process. This field contains the

commands, responses and sequence numbers used to

maintain the data flow accountability of the link, defines the

functions of the frame and initiates the logic to control the

movement of traffic between sending and receiving stations.

It has the three field formats1.Information transformation,

2.Supervisory format, 3.Unnumbered format.

4. Information Field

This field is not always in a HDLC frame, is only present

when the information transfer format is being used in ctrl

unit. It contains actual data to be send from transmitter to

receiver.

5. Frame Check Sequence (FCS)

This contains 32-Bit or 16-Bit Cyclic Redundancy Check

(CRC) used for error detection.

B. Open Core Protocol (OCP)Open Core Protocol (OCP) is a signal exchange protocol

over a family of on-chip core interfaces. OCP data transfer

models range from simple request-grant handshaking

through pipelined request-response to complex out-of order

operations. OCP provides a master/slave connection between

two cores. One core, the OCP initiator core has an OCP

master interface. A master interface enables a core to generate

OCP requests such as READ or WRITE and receive the

READ responses. The other core, called the OCP target core,

has an OCP slave interface which allows it to receive and

respond to requests. Strength of OCP is the ability to

configure an interface to match a core’s communication

requirements. Profiles address only the OCP interface, with

each profile consisting of OCP interface signals, specific

protocol features, and application guidelines.

The bridging profiles of OCP are designed to simplify or

automate the creation of bridges to other interface protocols.

The bridge can have an OCP master or slave port. This paper

discusses the Peripheral OCP profile with Simple Write and

Read transfer and Generic OCP profile with data handshaking.

The Master gives Requests and accepts responses. The slave

receives and responds to the Requests provided by the master.

Bus Bridge act as both a master and slave on the internal SoC

interconnect. The master sent the bus traffic to the desired

location and the slave WRITEs or READS the bus bridgeinternal control or status registers. Handshake signals are

provided for both Master and Slave which indicates

acknowledgements. The processor designed with OCP master

is interfaced with the HDLC controller. During write

operation the master starts a request phase by switching its

command field to write and presents a valid data and address.

The slave accepts the command and captures data and address

and a write is performed according to the design. The master

starts a Read request by switching its command field to Read.

It presents a valid address and slave accepts the command.

The slave captures data from the specified the address and is

driven to the Master. The response is also given to master to

indicate that the data is valid.

III. PROPOSED DESIGN

Figure2. HDLC OCP Architecture

8/12/2019 IJSETR389-07


High Performance of HDLC Protocol Design using OCP based on Xilinx FPGA



Functional blocks of HDLC frame formation and De-

framing as shown in fig 2. The main functional blocks in

framer blocks are Serializer and CRC computation block, as

same in De-framer block are De-Serializer and CRC check

block. The detailed explanation of each block as follows.

A. CRC Block

CRC is a one of the most famous and strongest error

control methods. A CRC (Cyclic Redundancy Check) is an

error detecting code. The CRC is a short-fixed length data sum

for an arbitrary data block. The CRC computation depends on

polynomial division. In this paper to compute CRC a

hardware circuit called LFSR was used. LFSR (Linear Feed

Back Shift Register) is a shift register whose input bits are a

linear function of its previous state. The most commonly used

linear function of single bit is XoR. Thus an LFSR is most

often a shift register whose input is driven by the XoR

(Exclusive OR) of some bits of the overall shift register value.

Figure 3 represents the 16-bit LFSR circuit.

Figure3. LFSR Circuit.

B. Serializer Block

The function of the Serializer block is to convert the parallel data in to serial form. The functional blocks inside

the Serializer are shift register and a counter. The shift

register here is to perform to receive parallel data and

transmit it into a serial form; the counter here is to count the

clock pulses for every bit transmission. This helps the

wastage of clock pulses during serial conversion. The state

diagram represents the function of the Serializer.

Figure4. Serializer State diagram

C. CRC check Block

The function of the CRC Check block is same as CRC

block in transmitter section. The difference here is it

compares the every generated CRC at receiver section to the

received CRC, if the received CRC is exactly same as

generated CRC it indicates CRC_OK signal is 1 if not it

indicates 0.

D. De-Serializer Block

Function of the De-Serializer is reverse function of the

Serializer block. Here it receives serial data and stored in to

a register by shifting the data received; after reaching all bits

of data it will transmit. The function of the counter here is to

count the clock pulses during loading the data in to register.

The state diagram represents the functionality of the de-

Serializer.

Figure5. De-Serializer State diagram

E. OCP Master

During the write operation OCP master gives the write

requests to the OCP slave and accepts the responses from

OCP slave as a write response signal. During the readoperation this transaction will continue with read request and

read response signals.

F. OCP Slave

During the master to slave write operation the slave will

receive write request signal from master and sends write

response signal to the master. This will continue in read

operation of master from slave with the read request and read

response signals.

IV. RESULT DISCUSSION

The design is carried out using Verilog HDL in ISE andXST. The simulation is carried out in ISE and implementation

is carried out using Xilinx Synthesis Tool (XST) on

XC3S500e-5fg320 device. The optimized architecture is

designed and RTL code is developed using Verilog HDL.

FPGA synthesis and implementation (Translation, mapping

and placing & routing) is carried out using Xilinx ISE. The

maximum frequency and device utilization for the HDLC with

OCP and without OCP is listed.

8/12/2019 IJSETR389-07


K.NAGESH, SHARIQ-UL-PERWEZ,V.HARIBABU



TABLE 1.

Timing report and Device summary of HDLC controller

with and without OCP.

HDLC with

OCP

HDLC without

OCP

Maximum

Frequency270.136Mhz 256.681Mhz

Total Area

Usage 160276kb’s 159512kb’s

Logic Utilization

Slices 45 40

Flip Flops 46 38

LUTs 82 76

Minimum period 3.702 ns 3.896 ns

I/p Arrival Time 4.088 ns 4.072 ns

O/p required time 4.063ns 5.589 ns

V.CONCLUSION

This paper presents a parameterizable and reconfigurable

OCP complaint bus bridge interface system specifically

targeted to the high speed applications. The primary trigger

to the development of such design is the lack of availability

of a common interface that can be used with the different IP

cores in a SoC design. In a SoC the different IP cores are

interfaced through different protocols. In this sense OCP

provides a common platform for all the IP cores and offers

IP core reusability. In this work comparing the existing

HDLC protocol with and without OCP, it is clear that there

is variation in the speed of operation with the use of OCP.

Synthesis results show that the device utilization is better in

compliant designs.

VI. REFERENCES

[1]. “Open Core Protocol specification 3.0” 2009

international partnership OCP-IP association.

[2]. OCP-IP “Open core protocol international partnership”.

[3]. Ramesh bhakthavatchalu “design and analysis of low

power OCP complaint interface using VHDL” IEEE-2011.

[4]. Wang Lie, Yi Ming “Design of HDLC controller based

on Xilinx FPGA” IEEE-2011.

[5].ISO/IEC13239 “information technology telecommuni-

cateions and information exchange between systems- Highlevel Data link control procedures” international organiza-

tion for standardization, pp 10-17, July 2002.

Documents

IJSETR389-07