IMPACT OF NANOMETER TRANSISTOR ON ANALOG

IMPACT OF NANOMETER TRANSISTOR ON ANALOG PERFORMANCE

MOHAMAD ASFA HUSAINI BIN ZAKARIA

A thesis submitted in fulfilment of therequirements for the award of the degree of

Master of Engineering (Electrical)

Faculty of Electrical EngineeringUniversiti Teknologi Malaysia

DECEMBER 2011

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To my beloved father and mother

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ACKNOWLEDGEMENT

I would like to express my gratitude to the people who helped me during the

research. Firstly, i like to thanks to Prof. Dr. Abu Khari A’ain for being a good and

supportive supervisor to me. The guidance and encouragement he showed is the key

to the successful of this project.

I also would like to express my thanks to En Izam Kamisian and Muhamad

Faisal Bin Ibrahim. They had provided me with brilliant ideas and supportive

feedback to aid me in my technical paper writing and research.

Next, I would like to thank my parent. They are really supportive and always

encourage me to finish up this project. I would also like to thank to my friends,

Muhamad Ridzuan bin Radin Muhamad Amin and Mohd. Fairus bin Ahmad for

sharing information and knowledge. Their contribution in this project really helps me

to develop my knowledge and understanding.

Lastly, I extend my acknowledgement to Intel Technology Sdn. Bhd. for

providing the research grant for the project.

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ABSTRACT

Scaling down of transistor dimension is generally being well accepted and

adapted by digital designers as they could introduce more design features at almost

no increase in silicon area. However, for analog designers, using smaller transistors

in their design would cost them extra design efforts as they have less design

headroom in hand –amongst others are low supply voltage, signal to noise ratios and

transconductance. These issues become more obvious as designers are now using

transistor size in nanometer region. This calls for better understanding on how

smaller transistor affect circuit performance. This research addresses the above

issues, using predictive transistor model, process technologies of 130 nm, 90 nm, 65

nm, 45 nm, and 32 nm as case studies. Analyses have been be carried out to

understand which of the analog performances such as gain, power dissipation, output

voltage swing, and cut-off frequency would be severely affected as the process

shrinks to nanometer region. The circuits designed for the research have also been

subjected to variations in process corner namely typical, slow, and fast. The

outcome of the research points out several disturbing impacts of nanometer size

transistors. First of all, its impact on analog performance of cascode amplifier is truly

a great concern. Low voltage supply in nanometer transistors presents a design

challenge to cascode amplifier in circuit design. Almost all its major performances

are severely affected. For telescopic amplifier circuit, the analog performances such

as gain and cut-off frequency are also greatly affected due to linearity issues of the

design when one moves toward smaller transistor sizes. However, results on

differential circuits have some positive news as it helps soften the impact on voltage

gain and voltage swing. It is also worth to mention that based on rough estimation,

designers would take longer time to complete the design task, thus slowing down the

time of manufactured devices to be marketed.

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ABSTRAK

Pengecilan dimensi bagi transistor secara umumnya diterima baik khususnya

bagi pereka litar digital di mana mereka dapat memperkenalkan lebih banyak rekaan-rekaan

terbaru tanpa perlu bimbang akan kepadatan transistor dalam ruang silikon. Namun begitu,

bagi pereka litar analog penggunaan dimensi transistor yang kecil di dalam rekaan litar

menyebabkan mereka memerlukan masa serta usaha yang lebih memandangkan terpaksa

menghadapi ruang operasi yang lebih kecil. Antara lain adalah sumber bekalan voltan yang

kecil, nisbah isyarat-hingar dan trankonduktan. Hal ini menjadi lebih kritikal dengan

penggunaan saiz transistor dalam skala nanometer digunakan oleh pereka litar analog dalam

rekaan pada masa ini. Dengan ini, pemahaman yang lebih mendalam mengenai kesan

penggunaan dimensi yang kecil kepada prestasi litar adalah perlu untuk meringankan beban

hasil daripada penskalaan dimensi transistor ini. Penyelidikan ini memberi fokus kepada isu-

isu di atas dengan menggunakan model ramalan transistor iaitu 130 nm, 90 nm, 65 nm, 45

nm, dan 32 nm dalam projek ini. Analisis telah dijalankan untuk memahami prestasi litar

analog yang manakah akan terjejas teruk apabila teknologi proses nanometer digunakan.

Prestasi litar analog yang dikaji tersebut adalah gandaan voltan, kuasa lesapan, ayunan voltan

keluaran dan sambutan frekuensi. Proses variasi iaitu “typical”, “slow”, and “fast”

dilaksanakan pada rekaan litar analog tersebut. Hasil daripada penyelidikan ini, terdapat

beberapa impak negatif dalam nanometer transistor. Pertamanya adalah impak prestasi

rekaan litar analog pada penguat kaskod. Sumber voltan yang rendah dalam nanometer

transistor telah mewujudkan satu bentuk cabaran dalam merekabentuk penguat kaskod dalam

litar analog. Hampir kesemua prestasi litar terjejas dalam penguat kaskod. Bagi litar penguat

teleskopik, apabila dimensi proses teknologi berganjak ke dimensi yang lebih kecil, prestasi

analog seperti gandaan voltan dan sambutan fekuensi terjejas akibat isu kestabilan dalam

rekaan litar. Namun demikian, hasil dari pemerhatian pada litar penguat pembeza, ia telah

menunjukkan satu perkara yang memberansangkan di mana impak kepada gandaan voltan

dan ayunan voltan keluaran dapat dikurangkan. Selain daripada itu, berdasarkan kiraan

secara kasar, peruntukkan masa yang lebih akan diperlukan oleh pereka litar analog dalam

merekabentuk litar dan ini akan menjurus kepada kelewatan peranti yang dikilang untuk

dipasarkan.

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TABLE OF CONTENT

CHAPTER TITLE PAGE

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLES xi

LIST OF FIGURES xii

LIST OF SYMBOL xvi

LIST OF ABBREVIATION xvii

LIST OF APPENDICES xviii

1 INTRODUCTION

1.1 Background 1

1.2 Problem Statements 2

1.3 Objectives 3

1.4 Scope 3

1.5 Contribution 4

1.6 Thesis Organization 5

2 LITERATURE REVIEW

2.1 Analog trade-off 6

2.2 Predictive Technology Model 7

2.3 SPICE Model for Circuit Simulation 8

2.4 Process Variation 9

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2.5 Design challenge due to scaling in nanometer 10

regime

2.6 Scaling effect due to scaling in nanometer 15

regime.

2.7 Opportunity of analog design in nanometer 18

regime.

2.8 Transistor variation and intrinsic gain 19

2.9 Power Reduction 21

2.10 Threshold Voltage variation 22

2.11 Reuse design 23

2.12 Power scaling 24

2.13 Summary 28

3 METHODOLOGY

3.1 General flow for the research 29

3.2 Method of Design and simulation 31

3.3 SPICE simulator 32

3.4 SPICE Model Parameter 35

3.4.1 Corner Process 36

3.4.2 Voltage Supply, Vdd 48

3.4.3 Hand Calculation 49

3.4.3.1 Derivation for Cascode Amplifier 49

3.4.3.2 Derivation for Differential Amplifier 51

3.4.3.3 Derivation for Telescopic Amplifier 53

3.4.3.3 Tuning Procedure 55

3.4.4 Spice Simulation 56

3.5 Reuse Design 59

3.6 Summary 61

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4 AN ANALYSIS ON ANALOG CIRCUIT

PERFORMANCE

4.1 Analog Performance 62

4.2 The analysis on corner process and node process 62

4.3 The impact of W and L 87to analog performances 74

4.3.1 Gain 74

4.3.2 Cut-off frequency 78

4.3.3 Power Dissipation 86

4.3.4 Output Voltage Swing 93

4.4 Summary 100

5 CONCLUSIONS AND RECOMMENDATIONS

5.1 Summary and Conclusion 102

5.2 Recommendations 105

REFERENCES 106

Appendices A-B 109-186

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LIST OF TABLES

TABLE NO. TITLE PAGE

2.1 Transistor Intrinsic Gain 21

2.2 Threshold voltage variation 23

2.3 Scaling factors between two node processes. 23

3.1 Requirement in SPICE simulation 33

3.2 Variation parameter 36

3.3 Voltage supply for technology node process. 47

3.4 Reuse design for 130 nm and 32 nm 60

3.5 Operating region 60

4.1 An Impact for Gain 100

4.2 An Impact for Cut-Off 100

4.3 An Impact for Power Dissipation 100

4.4 An Impact for Voltage Output Swing 101

5.1 Duration of design 104

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LIST OF FIGURES

FIGURE NO. TITLE PAGE

2.1 Analog design octagon 6

2.2 Features for robust design exploration 7

2.3 Supply voltage vs Node process 10

2.4 Velocity saturation occurs at smaller 11

channel lengths

2.5 Velocity saturation reduces the gain 11

2.6 Noise 12

2.7 Design rules complexity 13

2.8 Microprocessor power trends 13

2.9 Supply Voltage Vdd, Threshold Voltage Vth Oxide 16 Thickness Tox and Matching parameter AVth as a

function of Technology geometry Lmin.2.10 Transistor gate length critical dimension 19

variations versus Node process and contacted

gate pitch

2.11 Inverter delay random variation 202.12 Inverter delay systematic variation 202.8 Analog switched capacitor circuit model 25

2.9 Id vs. Vgs-Vt for several channel length 27

3.1 General flow of the research 30

3.2 Design and analysis flowchart 30

3.3 a) Differential Amplifier 31

b) Cascode Amplifier 32

c) Telescopic Differential amplifier 32

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3.4 An example of netlist file 34

3.5 SPICE Model Parameter netlist file 35

3.6 Ids vs Vds and Ids vs Vgs –NMOS (130 nm) 37

3.7 Ids vs Vds and Ids vs Vgs –PMOS (130 nm) 38









3.16 W and L varied relatively in each transistor 56

3.17 Gain and cut-off frequency measurement 57

3.18 Output voltage swing measurement 59

4.1 a) Cascode amplifier – 45 nm 63

b) Differential amplifiers – 130 nm 64

c) Telescopic amplifiers – 45 nm 64

4.2 a) Differential percentage(Gain)- 65

Differential Amplifier

b) Differential percentage(Gain)- 65

Cascode Amplifier

c) Differential percentage(Gain)- 66

Telescopic Amplifier

4.3 a) Cascode amplifier (130 nm) 67

b) Telescopic amplifiers (90 nm) 68

c) Differential amplifiers (32 nm) 68

4.4 a) Differential percentage(f3dB)- 69

Differential amplifiers

b) Differential percentage(f3dB)- 69

Telescopic amplifiers

4.5 a) Differential percentage(power dissipation)- 70


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b) Differential percentage(power dissipation)- 71

Cascode amplifiers

c) Differential percentage(power dissipation)- 71


4.6 a) Differential percentage(voltage output swing)- 72


b) Differential percentage(voltage output swing)- 73

Cascode amplifiers

c) Differential percentage(voltage output swing)- 73


4.7 a) Output resistance for differential amplifier 74

(node process-65 nm)

b) Output resistance for cascode amplifier 75


c) Output resistance for Telescopic amplifier 75


4.8 a) Gain vs W/L for differential amplifier 76

node process 32 nm

b) Gain vs W/L for cascode amplifier 77

node process 45 nm

c) Gain vs W/L for Telescopic amplifier 77

node process 90 nm

4.9 Cut-off frequency vs W/L for 78-79

differential amplifier


cascode amplifier


Telescopic amplifier

4.12 Power dissipation vs W/L for 86-88

Differential amplifier

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Cascode Amplifier



4.15 Output voltage swing vs W/L for 93-95

Differential amplifier


Cascode amplifier


Telescopic amplifier

5.1 Design time 104

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LIST OF SYMBOL

Vgs - Gate-to-source voltage

Vgd - Gate-to-drain voltage

Vds - Drain-to-source voltage

Vth - Threshold voltage

VT - Thermal voltage

Vdd - Supply voltage

Vd/Vs/Vg - Drain/source/gate voltage

Vout - Output voltage (logic) for gate leakage detection circuit

Vlimit - Limit voltage corresponds to allowable Igtotal level

Id/Ids - Drain current

Ibias - Biasing current

Iref - Reference current

TT - Typical process corner

FF - Fast process corner

SS - Slow process corner

� - Open loop gain

Tox - Oxide thickness

Leff - Effective channel length

Ndep - Channel doping

Cox - Oxide capacitance

Cjs - Depletion region capacitance

W - Channel width

L - Channel length

T - Temperature

�� - Channel length modulation

�� - micrometer

nm - nanometer

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LIST OF ABBREVIATION

CMOS - Complementary Metal Oxide Semiconductor

SoC - System On Chip

NIMO - Nanoscale Integration and Modeling

ASU - Arizona State University

MOS - Metal Oxide Semiconductor

IC - Integrated circuit

MOSFET - MOS Field effect transistor

NMOS - n type MOS

PMOS - p type MOS

BSIM - Berkeley short channel IGFET model

SPICE - Simulation Program with Integrated Circuit Emphasis

CUT - Circuit under test

BSIMPD - BSIM partial-depletion SOI MOSFET model

SOI - Silicon on insulator

PTM - Predictive Technology Model

CD - Critical Dimension

ACLV - Across the Chip Length Variation

SNR - Signal Noise Ratio

RDF - Random Dopant Fluctuations

LER - line-edge roughness

LWR - line-width roughness

DR - Dynamic Range

TT - typical process

SS - slow process

FF - fast process

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LIST OF APPENDICES

APPENDIX TITLE PAGE

A Figure of Gain 108

B Node process for 130 nm, 90 nm, 65nm, 111

45 nm and 32 nm.

CHAPTER 1

INTRODUCTION

1.1 Background

In the past, analog design has comfortable settled down using large scale of

complementary metal oxide semiconductor, CMOS transistor. But, it is quite obvious

that when analog designs move to smaller dimensions, there should be considerable

improvements in performances. Though such advantages are obvious, the finding of

the pathways to their realization is a hard task. Careful examination is required in

both physical device behaviors and simulation methods. Attempts to design analog

circuits at smaller dimensions come with a price. There are a lot of problems that are

new to most of analog designers.

As transistors size move towards smaller dimension, the problem faced by

circuit design engineers becomes more pressing and this is especially true for analog

designers. The nature of analog design which is very sensitive to process variations

pose serious design issue when one does vertical or horizontal migration. Horizontal

migration refers to migration from foundry to foundry due to economic or costs

reason. Vertical migration refers to migration from one process node to smaller

process node. Between these two, vertical migration causes serious concern as

smaller transistor dimension bring with it new sets of design issues which are of not

real concern for digital circuits. An example is channel modulation, � which has big

impact on analog circuit performance. Its value is getting smaller when it migrates to

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smaller node which causes difficulty for analog designers to achieve high gain and

good match between transistors. For that reason, analog designers will continuously

iterate the design cycle till all the design specifications are met. In the era where

competitors are aiming to reach their product to market as early as possible, this

traditional analog design process is surely of great concern.

The above scenario cause serious concern for analog designers and one of the

approaches which could be taken is to make sure that they have the knowledge on the

impact of vertical scaling on circuit performance. Since smaller device behavior is

very difficult to model accurately, analytical descriptions used for circuit simulation

will inevitably introduce further error into the design effort. Thus it could be pointed

out that it is an utmost important for analog designers to appreciate and understand

which of the design parameters would severely affect design specifications as this

could reduce time to market through reduction in fine tuning the design.

1.2 Problem Statement

Demand for System On Chip (SoC) has led to the integration of mixed mode

digital and analog circuits on the same substrate. In digital design, the fundamental

idea of ‘more is better’ [15] tells us an obvious challenge in analog design. It is not

surprising that most of the design infrastructure is focused on digital applications,

particularly in the nanometer regime. However, with considerable growth occurring

outside of mainstream ‘computational’ applicators (such as communications),

increasing attention is being paid to ‘analog issues’ in both simulation and design. As

these issues begin to be addressed, analog design at smaller dimensions becomes

possible.

This has left analog designers of no choice but to face design problems

introduced by the nanometer size transistors. The problems to maneuver and ‘juggle’

all the design specification require deep understanding of how the process affects the

circuit performance. Only with good understanding of the challenges brought by

small size transistor will pave the way for fine tune in the design process to meet all

design specifications. Good understanding of the challenges will only be available

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once detail analysis has been performed on the advantages and disadvantages of

analog performance posed by small transistor size in particular nanometer range.

1.3 Research Objective

This research aims to focus on these issues:

1. To study the impact of vertical scaling on analog circuit performance based

on several generation of Predictive Technology Model (PTM) which was

developed by Nanoscale Integration and Modeling (NIMO) Group at Arizona

State University [1]. The processes are 130 nm, 90 nm, 65 nm, 45 nm and 32

nm. The study was conducted through literature review as well as hand

calculation and simulation work using Tanner Tools design software. Analog

specifications such as power dissipation, gain, output resistance, cut-off

frequencies and stability have been used as gauge meter to determine the

impact of vertical scaling on smaller transistor dimension.

2. To evaluate the effectiveness of design reuse

3. To find out the degree of design difficulty when design migrates to nano

region process

1.4 Scope

There are 3 phases in this research. This research was totally based on

simulation using PTM which is 130 nm, 90 nm, 65 nm, 45 nm and 32 nm processes.

Circuit performance such as gain, power dissipation, output swings were monitored

in all process corners analysis.

Based on available PTM models, sample circuits which are widely used have

been designed. In particular, the performance of single input and differential inputs

circuits were compared. Circuits such as cascode amplifier, simple differential

amplifier as well as differential telescopic amplifier have been used as sample

circuits. All these circuits have been simulated in process corners analysis to

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understand the impact of scaling down on specific circuit performance. Analyses

have also been carried out on circuit performances mentioned above. Comparison on

performance was also conducted to get more insight on design issues. Analysis on

design time has also been conducted as the node process move toward smaller

dimension.

1.5 Contributions

The literature review conducted in this research indicates that there is

inadequate work conducted to analyze the impacts of transistor scaling in nanometer

regime which focuses more on circuit analog performances such as output voltage

swing, cut-off frequency despite the impact on gain and power dissipation. The usage

of mathematical analysis in nanometer transistor seems hard to deal with since there

are many more physical parameters have to be considered than before. Because of

that, researchers always tend to use mathematical CMOS level 1 model. Since most

researchers tend to use mathematical analysis, the actual impact of transistor in

nanometer regime will not entirely visible. Thus, in order to understand the impact of

nanometer transistor, the data were manipulated into figures and tables. This is the

main contribution of this work since a lot of data based on simulation results from

130 nm, 90 nm, 65 nm, 45 nm and 32 nm processes are presented.

The concept of ‘design reuse’ that has been introduced by other researchers is

also less reliable when the transistor size moves towards a smaller dimension. This is

another contribution of this work where it is shown that ‘reuse design’ has its own

issue.

Another contribution of the work come from the result presented from

differential amplifier which shows that it is less affected by vertical scaling. The last

but not least contribution is an indicator that shows design time will be prolonged as

one migrates towards nanometer region.

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1.6 Thesis Organization

There are five chapters in this thesis. In chapter 1, the background of this

research is introduced to highlight a general idea about this research as well as the

problem statement, research objectives, project scope and its contributions.

Literature review is covered in chapter 2. This chapter consists the research

papers that been studied during this research. The introduction of process variation in

analog design is discussed in this chapter. Besides, the design challenges as well as

scaling effect in nanometer transistor are also discussed in this chapter. At the end of

chapter 2, recent works by other researchers on nanometer transistor are introduced.

The methodology of this research is described in chapter 3.The flow of the

circuit simulation is described as well as the explanation on how to rewrite the

SPICE model parameter to include the process variation effect in it. The explanation

of analog circuit performances is also included in this chapter.

Chapter 4 consists the analysis regarding the impact of nanometer transistor

on analog performances. There are three types of analysis in this chapter which are

the impact of corner process, node process and transistor size to analog performances

in nanometer transistor.

The last chapter which is chapter 5 concludes this research and recommends

possible future work.

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CHAPTER 2

LITERATURE REVIEW

2.1 Analog trade-off

Analog design involves optimization and trade-off between several

conflicting metrics. What aspects of the performance of an amplifier are important?

[2]. Other than gain and speed, other parameters such as power dissipation, supply

voltage, linearity, noise and maximum voltage swings are also important. Besides,

the input and output impedance determine how the circuit interact with early and

later stages [2]. In practice, most of these metrics trade with each other, making the

design a multi-dimensional optimization problem [2].

Figure 2.1: Analog design octagon

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Figure 2.1 above illustrates analog design octagon which represents the trade-

off between these analog performances. Such trade-off presents many challenges in

the design of high performance amplifiers which require intuition and experience to

reach at acceptable compromise [2].

2.2 Predictive Technology Model

A Predictive Technology Model (PTM) is important for early circuit design

study. It connects the process development and circuit simulation through device

modeling which is important in assessing potentials and limits of new technology

and in supporting early design work. PTM is developed by the Nanoscale Integration

and Modeling (NIMO) Group at Arizona State University (ASU) [1]. The PTM

project is sponsored by FCRP Focus Center for Circuit and System Solutions (C2S2),

Materials Structures and Devices Center (MSD), and Semiconductor Research

Corporation (SRC) [1].

PTM provides precise, customizable, and predictive model files for future

transistor and interconnect technologies [1]. These predictive model files are well-

matched with standard circuit simulators, such as SPICE, and scalable with a wide

range of process variations [1]. With PTM, competitive circuit design and research

can start even before the advanced semiconductor technology is fully developed

[1]. As an evolution of previous Berkeley Predictive Technology Model (BPTM),

PTM will offer the novel features for robust design exploration toward the 10 nm

regime as shown in figure 2.2 [1].

Figure 2.2: Features for robust design exploration

PTM

Predictions of different

transistor structures

New methodology of prediction,

which is more physical, scalable,

and continuous over technology

generations.

Predictive models for

emerging variability and

reliability issues

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2.3 SPICE Model for Circuit Simulation

Simulation Program with Integrated Circuit Emphasis (SPICE) is a general

purpose analog electronic circuit simulator. It is a superior program that is used in

Integrated Circuit (IC) and board-level design to verify the integrity of circuit designs

and to predict circuit behavior. Circuit simulation in SPICE gives analog designer a

choice to choose between various types of model to model the behavior of devices

used in their circuit. Device such as transistor can be categorized using 2 models

which are macro model or compact model. Macro model is still being used to model

new and recent phenomenon which is not covered in compact model such as the fault

and defect model. Meanwhile in frequent practice, analog designer tends to use

compact model since it is supported by most of SPICE simulator such as HSPICE

and TSPICE.

There are various types of compact model but the most popular and widely

used in analog design is Berkeley Short-channel IGFET MODEL (BSIM) model.

BSIM model is the standard industrial model which has several types of model in it

such as BSIM3, BSIM4 and BSIMSOI. BSIM4 model was introduced to model the

transistor in 90 nm and below accurately. It includes the gate leakage model which

the previous BSIM3v3 model has ignored.

To simulate the circuit designed using SPICE simulator, model parameter

must be included in circuit netlist. The model parameter’s value is different for

different node processes meaning that different fabrication house will has different

parameter value although they use the same compact model to model their transistor.

BSIM model acts as an intermediate layer that relates the CMOS process which is

fabrication house and simulator tools. Since the results of circuit simulation using

SPICE depends on this compact model, fabrication house always develop the model

as accurate as possible so that the miscorrelation between fabricated circuit and

simulation result can be minimized. As a result, the fabricated circuit will function

according to the design specification.

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2.4 Process Variation

To fabricate a design, CMOS process has always been the designer choice

because of its low power and high integration characteristic. The scaling in channel

length, L benefits the designer which resulted in more function and logic can be

implemented in a single IC. But, as the channel length become smaller, process

variation will be more obvious. Technology process scaling beyond 90 nm is causing

higher levels of device parameter variations, which are changing the design problem

from deterministic to probabilistic [3, 4].

Process variation can be divided into two main categories which are intra and

inter die variation [5]. For intra die variation (local process variation), it occurs in

identical devices in the same circuit within the same die. The variation in electrical

properties will lead to component mismatch for example the variation in oxide

thickness and doping profile during fabrication step. But, for inter die variation

characterization, the variation is in die to die, wafer to wafer or lot to lot variation

which mean the same variation is assumed in devices in the same circuit. Between

these two, inter die variation has more influence to digital circuit [5]. In contrast, for

analog circuit, both variations have significant impact towards the circuit

performance especially the intra die variation [5]. The variation is always modeled

by using corner process model with fast, slow and typical models.

To generate a corner model, the model parameters in typical model are

skewed to their acute value. These model parameters are varied relatively in the same

percentage proportionately to each model parameter’s standard deviation. The

standard deviation is referred as sigma in the model parameters. But, in this model

parameter, only a few parameters have been varied because by varying all the

parameters in the compact model, it will be inefficient. Thus, only certain parameters

in the model are varied such as effective channel length, threshold voltage, oxide

thickness, and channel doping [6]. These parameters are the critical parameters to

determine the major behavior of the MOS transistor [6]. But, this does not mean that

the other parameters are unimportant. Depending on specific process, the number of

critical process parameters that should be considered might be more than these four

10

[7]. By varying these parameters to the right (positive) and left (negative), fast and

slow models are obtained.

2.5 Design challenge due to scaling in nanometer regime

Analog design in nanometer regime requires more precise models. The

critical questions such as “What will be the I-V characteristic? ,What will be the

maximum speed? ,What will be the 1/f noise? ,What will be their mismatch

coefficients?” always firstly been addressed due to transistor scaling. MOSTs models

started with only a few parameters such as threshold voltage, a current parameter KP

and a body-�� ].The continuous reduction in channel length has

always increase the number of parameter. Weak inversion operation at low current

and velocity saturation operation at high current have increased this number as well

[14]. At this point, the number has become unmanageable and it will become even

worse in the future.

The power supply voltage history is shown in Figure 2.3 [27]. Reduction in

the supply has slowed down in recent generations due to the inability to reduce

transistor threshold voltage (Vth) because the transistor off state leakage (Ioff) has

become a significant proportion of the total logic chip power [27]. This is because of

digital power considerations and not because of the challenge with the analog circuit

functionality [27]. A low supply voltage of around 1.0V does mean that the analog

signal swing and the headroom for a current source are greatly constrained but it

does not mean that designer does not have enough dynamic range [27].

Figure 2.3: Supply voltage vs Node process [27]

11

In nanometer CMOS technologies, several new effects emerge due to short

channel-length effects. This is true for velocity saturation and gate leakage currents.

As a result improved transistor models are required to allow accurate prediction of

analog circuit performance. The transconductance and speed are both limited by

velocity saturation. Also noise and mismatch suffer from smaller channel lengths, as

a result of the thinner gate oxides used. Moreover the supply voltage is also reduced

creating new challenges for analog circuit design [8].

Shorter channel lengths lead to lower magnitude of transconductance [8]. The

reason is that the velocity saturation effects arise at smaller values of Vgs-Vt. This

can be seen in figure 2.4 [8]. Indeed the cross-over value of VGSvs-Vt is about

proportional to the channel length L. As a result the region of constant

transconductance, gmsat occurs earlier as well leading to lower values of gain. This

can be seen in figure 2.5 [8].

Figure 2.4: Velocity saturation occurs at smallerchannel lengths

Figure 2.5: Velocity saturation reduces the gain

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The thermal noise is inversely proportional to tranconductance and do not

increase at shorter channel lengths as shown in figure 2.5 [8]. The 1/f noises do not

increase as WL factor is balanced by oxide thickness mean that the nanometer

CMOS is not a real concern in low noise design. This can be seen in figure 2.6 [8].

Figure 2.6: Noise

As increasing of design size and complexity, it is becoming more severe and

difficult to meet the manufacturing requirement. This is true as process geometry

continues to shrink, the industry faces several designs and manufacturing

convergence issues. One of the obvious design challenges is productivity [11]. The

study by Semiconductor Manufacturing Technology (SEMATECH) showed that

although the level of on-chip integration, expressed in transistors per chip, increases

at an approximately 58% per year compound growth rate, the design productivity,

measured in transistors per person-month, grows only at a 21% per year compound

rate [11]. Such a mismatch of silicon capacity and design productivity, if not

resolved timely, will seriously limit the potential of achieving high-degree on chip

integration, and significantly increase time-to-market [11].

As design size and complexity are increasing, multi site design teams are

required. Yet, the number and complexity of design rules are exponentially increase

as node process goes toward smaller dimension or shrink. This phenomenon is

illustrated in figure 2.7 below which show the design rules with shrinking geometries

[9].

13

Figure 2.7: Design rules complexity.

Power consumption in CMOS circuits includes both static and dynamic

power dissipation. The static power dissipation, caused by leakage currents and sub-

threshold currents usually contributes to a small percentage of total power

consumption, while the dynamic power dissipation, resulted from charging and

discharging of capacitive loads of interconnects and devices dominates the overall

power dissipation[11]. Even though rapid shrinking of device dimensions and

reduction of the supply voltage reduce the power dissipation of individual device

significantly, the exponential increase of degree and operating frequencies still

results in a steady increase of total power consumption [9]. Supply voltage, Vdd will

gradually reduce as node technology process move down to smaller dimension but as

a contribution in power reduction, it is definitely not satisfactory. Power dissipation

increases due to transistors count and higher operating frequencies which is shown in

figure 2.8 [10].

Figure 2.8: Microprocessor power trends

14

As the IC technology deeply move toward nanometer regime, the

interconnect reliability becomes another challenge to the design technology. The

interconnect reliability includes both the signal reliability and manufacturing

reliability. The signal reliability requires that the signal carried by the interconnect

always stabilizes at its intended value within its specified delay bounds [11]. The

manufacturing reliability requires that the interconnect structures meet the design

rules and the connectivity specification throughout the manufacturing process and

the life span of the ICs [11]. Process variation and noise are mainly affecting the

signal reliability.

The process variations in nanometer designs also contribute to a large degree

of uncertainty to the signal delay and skew values in various portions of the chip.

Experts indicate that the across the chip length variation (ACLV) of wire widths can

be as large as 20% in the 0.1um technology and below [13]. In this case, layout

parameters have to be treated as statistical variables instead assuming fixed values

[11]. Models and tools are needed to handle and optimize a large number of

statistical variables to assure the signal reliability [11].

The other parameter that affects signal reliability is a noise. One major source

of noise is crosstalk, especially the capacitive coupling crosstalk, which becomes

very significant due to the rapid increase of coupling capacitance with the technology

scaling [11]. The value of crosstalk noise depends not only the coupling capacitance

of adjacent wires, but also a number of other factors, such as the driver and receiver

sizes, the patterns and relative timing of the signals on neighboring wires, etc [11].

Another source of noise is the power and ground bounce which is caused by

simultaneous switching of a large number of devices on the chip [11]. As a result, the

voltage of power supply or ground, (gnd) may change considerably. The noise in the

power and ground also depend on the temporal correlation of the signals on the chip

as well as their distribution [11]. Both types of noise are extremely difficult to predict

and calculate, especially in the early phase of design process, as they depend on the

detailed layout and timing information [11].

The manufacturing reliability of interconnects is affected by defect density

and electro migration. The defect density is mainly determined by the manufacturing

15

technology meanwhile electro migration, which forms open or short to neighboring

lines due to the transport of the metal atoms when an electric current flows through

the wire, may limit the lengths and widths of interconnects in order to control the

current density [11]. It is predicted that the electro migration current density

limitation of Cu will become an issue at the 70 nm technology [12]. The electro

migration constraint and other constraints related to design for manufacturing needs

to be properly considered by future design tools.

2.6 Scaling effect due to scaling in nanometer regime.

Of all the aspects of design in deep sub-micron technologies, the scaling of

the supply voltage, Vdd is the most obvious and most severely affects analog circuit

design [15]. Based on figure 2.9 [15], for technologies larger than (or equal to)

��m, Vdd stays flat and equals 5.0V.In smaller technologies, Vdd scales roughly

linear with minimum feature size (although it follows a staircase function) [15].

Figure 2.9 shows that both oxide thickness (Tox) as well as matching (AVth) scales

down linearly with technology [15]. Figure 2.9 also shows threshold voltage Vth,

clearly not scaling linearly, but more like a square-root function. The effect of that on

voltage headroom is still not that strong as Vth is still only 25% of Vdd [15]. This

might change below 0.1 �m as preliminary estimates show Vth to have a lower limit

of approximately 300 mV [15].

16

Figure 2.9: Supply Voltage Vdd, Threshold Voltage Vth OxideThickness Tox and Matching parameter AVth as a function of

Technology geometry Lmin.

Foundries have begun to offer low Vth devices .Usually the low Vth device is

a native device, meaning no threshold voltage adjustment has been applied [15].

Sometimes zero-Vth devices with threshold voltage adjustment are also offered, along

with medium Vth devices [15]. Disadvantages of these devices are the fact that often

they do require extra masks, increasing cost and turn-around time, they are often less

well characterized and can differ substantially from foundry to foundry, making the

design foundry dependent[15]. But no doubt, this is one of the easiest ways to get

around the problem and a good choice when time-to market is most important [15].

In gain stages, it becomes questionable whether or not the use of cascodes is

appropriate. If the voltage efficiency �vol=Vsig/Vdd decreases, equation (2.1) predicts

the power to go up [15]. From [15], we see that the average value of �vol in these

designs has been about 25%. So, by assuming a Vdsat=150mV and requiring

�vol=25%, cascoding both the N and the P-side could be maintained to a supply

voltage of 800mV and no margin would be left [15]. Practically that means that

17

below 1.0V supply (0.1 �m technology), cascoding at full signal swing becomes

difficult [15]. Without cascoding however, gain-boosting is not possible and multi-

stage amplifiers become the only alternative [15].

P = 2�Ttech*(�vol.�cur)-1*n2*DR2*Fsig. (2.1)

Device performance has improved dramatically as the channel length has

been reduced. However, as Lg is scaled below 100 nm, short channel effects (SCE)

and the degradation in transport start to limit the enhancement in digital transistor

performance. In the case of analog devices, SCE seriously degrades Rout. Moreover,

improvement in gm is limited by velocity saturation and mobility degradation (mostly

due to the increase in NA and decrease in Tox). Biasing a device in the region where

its gm/Ids is higher generally leads to better intrinsic gain [14]. However, varying the

physical parameters of a device to improve gm/Ids can lead to a worse gain [14]. For

each channel length, as the bulk doping is reduced, gm/Ids improve due to better

mobility but gain degrades due to more severe SCE [14]. The overall gm/Ids vs.

intrinsic gain trade-offs degrade slightly with scaling. Yet, when same threshold

voltage is maintained, scaled devices show large improvement in gm/Ids, however the

intrinsic gain degrades much more severely [14]. Since scaling improves the trade-

offs except for gm/Ids vs. gain, analog performance of the device is generally

enhanced as channel length is reduced.

It is well known that analog device/circuit frequency performance can be

improved by increasing the bias current. This results in a trade-off between power

and fT. However, higher bias current leads to a lower gain due to smaller Rout. Longer

channel length devices do not show any improvement in overall intrinsic gain vs. fT

trade off with increasing Ids as the improvement in fT is countered by degradation in

gain [14]. While for longer L, devices, Rout is dominated by channel length

modulation (dependant on Ids), Rout of smaller Lg, devices is dominated by DlBL

(weakly dependant on Ids), therefore the curves shift upwards with increasing Ids,

since fT improves while gain is not reduced significantly. However, the curves

saturate for higher values of Ids because the improvement in fT is limited by both the

velocity saturation and mobility degradation. Consequently, there is no improvement

in the trade-off at higher currents even for Lg=50nm devices.

18

As devices are scaled according to Vth parameters, fT increases dramatically

while intrinsic gain only decreases modestly [14]. However, the threshold voltage

increases from 0.24 V to 0.33 V as the channel length is reduced from 150 nm to

50nm, which is not acceptable since the power supply is reduced as Lg is reduced.

The solid curve shows the scaling impact on gain and fT, if a threshold voltage of -

0.2V is maintained [14]. In this case the gain decreases severely and the gain greater

than 20 dB would be difficult to achieve as Lg approaches 50 nm [14]. Scaling Lg

and Tox , improves gm/Ids .However, the improvement is limited by the increasing of

NA, the decrease of Xj and the velocity saturation effects. Scaling with a constant Vth,

has better performance in terms of gm/Ids and fT but at the expense of lower gain. This

is mainly due to the fact that bulk doping is not as high as in the case of digital

transistors.

2.7 Opportunity of analog design in nanometer regime.

Analog once was the field in which the main chunk of signal processing was

done. Since a few decades a continuous shift towards digital signal processing with

some analog processing (or conditioning) of the inputs and outputs of the digital core

is apparent. However, still analog circuits are required to get meaningful data into

and out of the digital core in an area-efficient and power efficient way. Although the

area where pure analog is applied will inevitably shrink to a (non-zero) minimum,

the requirements on analog circuits will continue to increase while the CMOS

implementation environment gets worse and worse.

One critical issue for analog CMOS circuits is the lowering supply voltage.

Based on [17], this problem can be tackled in 2 ways. Design analog circuits that

operate at a low voltage or design analog circuits that can withstand higher than

nominal supply voltages [17]. In the past 15 years, the first approach is been used for

quite some time where the supply dropped from 5 V down to 1.2 V today. Recently,

there are a lot of new circuit techniques have been developed for example the

switched op-amp technique where switches in switched capacitor are moved from the

signal path to the supply path, where they need less gate drive [17]. Today, the

estimation of minimum supply for an analog circuit seems to be VGS + VDS(SAT) +

19

Vswing, where Vswing is the signal swing [17]. If still enough SNR is needed then the

noise has to be lowered [17]. This can simply be done through impedance level

scaling, and the result is that 10 dB less noise will result in 10 times more power

consumption [17].

Thermal noise is also can be cancelled but at the cost of power dissipation

[16]. 1/f noise is one of a major concern as well since the corner frequency, where

thermal noise dominates the 1/f noise seems to be proportional to fT in a given

technology. So since fT prefers to be high, to benefit from the bandwidth, 1/f noise

will be large too. Chopping and double correlated sampling can remove 1/f noise for

low frequency application [17]. Switched bias technique can reduce the intrinsic 1/f

noise of transistors [17].

2.8 Transistor variation and intrinsic gain

The later 45 nm and 32 nm technology process issues to a number of sources

of variation such as random dopant fluctuations (RDF), line-edge roughness (LER)

and line-width roughness (LWR), gate dielectric thickness variations, fixed charge,

defects and traps in the gate dielectric and gate dielectric-silicon interface, patterning

and proximity effects, polishing effects for the gate and shallow trench isolation,

transistor strain and implant and annealing effects.The trend for the components of

gate length critical dimension, CD variation is shown in Figure 2.10 with the

reference 0.7X scaling of the gate CD variation.

Figure 2.10: Transistor gate length critical dimension variations versus

Node process and contacted gate pitch (nm).

20

While the systematic and random variations have been kept under control for

logic, as shown in Figure 2.11 and Figure 2.12 respectively, the random variation

effects which have inverse area dependence, such as RDF and LER, are not

improving enough to stop transistor mismatch from increasing. At the 65 nm and 45

nm node, simulations to measure the RDF contribution to total Vth random variations

indicated that 60 to 65% of it is due to RDF. Because analog circuit area has to

provide scaling across technology nodes for a microprocessor, this scaling analog

circuit transistor size is going to increase to some extent the circuit Vth and Leff

variations.

Figure 2.11: Inverter delay random variation

Figure 2.12: Inverter delay systematic variation

21

As the intrinsic gain of the minimum gate length transistor may have

decreased with technology scaling initially, it has been maintained above 6 dB in the

last decade of scaling. This is because the inverter gain can affect the logic delay

when the gain gets too low. The intrinsic gain in the 32 nm CMOS logic transistors is

shown in table 2.1. So while it has decreased from the levels of the 130 nm node it

has not dropped below an unacceptable level in which analog circuits have difficulty

being implemented.

Table 2.1: Transistor Intrinsic Gain

2.9 Power Reduction

In digital circuits, the power consumption is mostly because of 3 current

components and they are the leakage current due to the reverse biased diodes formed

between the substrate, the well, and the source and drain diffusion regions of the

transistors, second is the short circuit current due to the presence of current carrying

path from the supply voltage to ground when certain PMOS and NMOS transistors

are simultaneously ON for a short period due the signal transitions at the input to the

logic gates and lastly is switching current due to charging and discharging of the load

capacitance. Between these three sources of power dissipation, the last component is

the most dominant. By ignoring the internal capacitances of logic gates, the common

power consumption for a logic gate is due to charging and discharging of load

capacitance. Based on equation 2.2, the power consumption is reduced in scaled

technology.

2* *digital ddP f C V� (2.2)

22

2( 2 )

( / )dd satV V

DRI�

�� (2.3)

As for analog circuit, power consumption depends on Dynamic Range, DR

and voltage supply as can be seen in equation 2.4. To obtain the aim of DR with

maximum voltage output swing, dynamic range can be obtained by equation 2.3

above.

analogdd

DRP

V� (2.4)

Based on the equation 2.3 and 2.4, analog power consumption shows

opposite result than power consumption in digital circuits. As a consequence, the

technology scaling results gives negative effect in analog circuits design.

2.10 Threshold Voltage Variations

The reduction of the different value between voltage supply, Vdd and

threshold voltage, Vth are critical for analog design. This is due to technology

scaling, technology node processes and analog design choices. To be precise, Vth

depends on several effects and of them because of technology variation (process,

voltage supply, temperature PVT variation).

In technology node process 65 nm, Vth variation due to PVT variation can be

tremendously large. This can be observed in table 2.2 where process corner has been

conducted. Based on table 2.2, the nominal value of Vth is 547 mV and it would

change with PVT from 425 mV to 646 mV, a huge margin amount. This change is

within 18% to 22%..

23

Table 2.2: Threshold voltage variation

2.11 Design reuse

The methodology of ‘design reuse’ by [15] is based on resizing rules

resulting on the application of the ACM (Advanced Compact Model) MOSFET

model. This model uses the same basic physical variables as the EKV model but

avoids the use of non-physical interpolating curves to bridge the gap between weak

and strong inversion [15].When the circuit is scale down to a smaller node process,

the scaling factor for this transition have to be defined. Table 2.3 shows us on how

the scaling factors are defined. The resizing equations are defined such as preserving

the DC gain, the gain-bandwidth product, the phase margin and the signal-to-noise

ratio of the circuit.

Table 2.3: Scaling factors between two node processes.

Scaling factor FormulaKv Vdd1/Vdd2

Kcox Cox1/Cox2

KL Lmin1/Lmin2

KE VE1/VE2

�� 1��2

Subscripts 1 and 2 refers to the initial and target technology respectively.

The aim of this resizing is to determine the new sizes of the transistors, to

keep the same performances of the original circuit and to reduce the area and power

consumption. The approach of this scaling rule is to maintain the same operating

point (ID, VGS) of the transistors. Scaling factor is defined to simplify the equation

which has been introduced in table 2.3.

24

1 2D DI I� ----------------------------- 2.5

1 2gs gsV V� ----------------------------- 2.6

� � � �2 21 1 1 2 2 2

1 1 2 21 22 2

o ox o oxgs T gs T

C W C WV V V V

L L

� � � ------------- 2.7

By simplifying equation 2.7,

2

1 112

1 2

gs TL

cox gs T

V VK WW

K K V V

��

---------------- 2.8

where KL, K�, Kcox, Vgs1, VT1 and VT2 are known.

From equation 2.8, scaling factor for W can be obtained as

2

1 12

1 1 2

gs TLw

cox gs T

V VW KK

W K K V V

��

---------- 2.9

Based on equation 2.9, the scaling factor for width depends on the use of

PMOS or NMOS transistors. During a scale down of the supply voltage, the gate

source voltages VGS are still the same. Consequently, the sizes of the transistors are

the same too. By using the scaling factor, a new transistor size can be obtained. This

scaling method conserves the analog performances and reduces the power

consumption and the area of the design [15].

2.12 Power scaling

Unlike in digital circuits, the power dissipation of analog circuit dominated

by static bias current in the amplifier rather than dynamic switching [16]. Analog

switched capacitor circuit model, figure 2.13 is used in this study. The bias current is

determined by the required speed and capacitive loading of the circuit. The speed is

limited by the time it takes the output voltage to settle to the desired accuracy. The

characteristic time constant (delay) of this circuit is given by equation 2.10 [16]. For

25

high-resolution switched-capacitor circuits, CS, CF, CLE are typically fixed by system

constraints related to thermal noise. Therefore, they do not scale with technology.

�� xed by the system clock speed [16].

Figure 2.13: Analog switched capacitor circuit model

1. T

m

C

f g� � (2.10)

( )T OP LE s IPC C C f C C� � � � (2.11)

F

s IP F

Cf

C C C�

� � (2.12)

IP oxC WLC� (2.13)

2.5OP j jswC WLC WC� � (2.14)

The static current required to get the desired speed � with a specified

capacitive load is determined by the relationship between I and gm. If strong

inversion operation in the saturation region is assumed, the drain current can be

modeled as equation 2.15. This model includes saturation effects and could include

mobility degradation. For this analysis however, only velocity saturation and channel

length scaling are considered [16]. From equation 2.10 and 2.16, the static power

consumption can be achieved as shown in equation 2.20.

26

( )d sat ox gt dsatI Wv C V V� � (2.15)

.2

gt satdgt

m gt sat

V E LIV

g V E L

��

(2.16)

gt satdsat

gt sat

V E LV

V E L�

� (2.17)

gt gs tV V V� (2.18)

2eff sat

sat

Ev

(2.19)

.2

gt satTgt dd

gt sat

V E LCP V V

f V E L� ��

� � � �� (2.20)

For simplicity, only Vgt and L scaling were considered meanwhile tox, Vt and

Vdd are fixed. Vgt scaling is important to circuit designers because unlike tox, Vt or

Vdd, it is one of the few parameters that they can control to optimize their designs.

Analog designers frequently keep Vgt conservatively fixed at a few hundred

millivolts to avoid sub-threshold operation [16]. In this case, equation 2.20 suggests

that scaling only L will not significantly change the power consumption but it

actually increase it slightly for small L. If only L is decreased in a design, then little

analog power savings will be realized. A larger power reduction can be achieved if

Vgt and L are simultaneously scaled.

When both L and Vgt are varied, for a given L (ignoring sub-threshold

effects), it appears that power will monotonically decrease as Vgt continues to

decrease. However, figure 2.14 shows that Idsat does not monotonically decrease with

Vgt, it reaches a minimum at some optimum Vgt [16]. By implicit that CT increases as

the transistor size (W) increases in equation 2.20, as Vgt decreases, W needs to

increase to provide a gm large enough to satisfy the settling time requirements of

equation 2.10.

27

Figure 2.14: Id vs. Vgs-Vt for several channel length

Using equations 2.15 and 2.16, gm can be expressed as equation 2.21 below.

For Vgt much larger than EsatL, this quantity remains fairly constant. For Vgt much

smaller than EsatL, gm is proportional to 2WVgt. Thus, as Vgt decreases, W must

increase proportionately to ensure an adequate gm.

� �� 2

2.

gt sat

m sat ox gt

gt sat

V E Lg Wv C V

V E L

��

� (2.21)

Increasing W will increases CT (via CIP & COP) and power (from equation

2.20). When CT increases faster than Vgt decreases, power is no longer reduced and

reaches a minimum. Intuitively, for large Vgt the device is intrinsically very fast (high

fT) compared to the circuit operating speed, and the device is small [16]. For small

Vgt the device is intrinsically slow (fT closer to circuit operating speed) and the

device must be very large to achieve that intrinsic speed [16]. The power optimum

occurs when the device parasitic are some fraction of the load [16].

28

2.13 Summary

Based on the literature review that has been conducted throughout this

research, it was noted that this research proposal has not been carried out by other

researchers. The scope of work presented an extensive analysis from node process of

130 nm to 32 nm using cascode amplifier, differential amplifier and telescopic

amplifier. This includes process corners which is also crucial in this work. Some

previous research presented related work, but their scope of work was limited to only

a few process technologies which did not cover as large range of process as this

work.

The observation in the design time has also been performed to investigate the

degree of design difficulty as transistor size move toward smaller dimension. This

information is very important so that analog designer would know what to expect as

design process migrates to small process.

29

CHAPTER 3

METHODOLOGY

3.1 General flow for the research.

This section will discuss the general idea on how the research works were

carried out. The research consists of 3 phases which include literature review,

circuits design, simulation, analysis and thesis writing. The general flow of the

research can be seen in figure 3.1. Phase 1 is where literature review was conducted.

In this phase, others research paper that related to the research were studied. This

study was conducted continuously during the research. The amplifier circuits that

have been used throughout the research have also been thoroughly studied. The

SPICE output netlists have also been analyzed as they contain useful informations

about the transistor’s operating region.

The second phase mainly focuses on circuit design and the analysis. The

simulation processes mainly were conducted in this phase which takes most of the

time of the research. The analysis process then been carried out based on circuit

simulation result. The design flow can be seen in figure 3.2. Others research paper

were also been studied.

30

The last phase of the research is thesis writing and it concludes the entire

research that been conducted. Yet, in this phase, the others research paper were also

been studied.

Figure 3.1: General flow of the research

Figure 3.2: Design and analysis flowchart.

31

3.2 Method of Design and simulation

The design of cascode amplifier, differential amplifier and telescopic

amplifier were conducted separately in this research. For each circuit, they were

designed in 5 node technology processes which are 130 nm, 90 nm, 65 nm, 45 nm

and 32 nm. The design procedure involved the usage of TSPICE simulation. Firstly,

the circuits were designed using hand calculations to obtain a rough value as starting

point in the simulation. The designs then were modified by fine tune the ratio (W/L)

and biasing voltage to meet the specification of the circuits. This process was

repeated until the designed circuits meet the circuit requirement.

AC and DC simulation were conducted in this work. From observation on

simulation result, the data then gathered. All these circuits were simulated in various

process corners and W/L ratio. The circuit performance such as gain, cut-off

frequency, output swing were investigated at node ‘out’ which can be seen in figure

3.3 (a),(b) and (c).The power dissipation was obtained from the output simulation

netlist.

The analysis on corner process simulation was executed to analyze the impact

of manipulated parameter on a circuit performance. All the data obtained from the

simulation were presented in tables and figures.

Figure 3.3(a): Differential Amplifier

32

Figure 3.3(b): Cascode Amplifier

Figure 3.3(c): Telescopic Differential amplifier

3.3 SPICE simulator

As stated in earlier chapter, SPICE is software that can be used to analyze the

operation of the electronic circuit which contains electronic components such as

transistor, resistor, capacitor and so on. SPICE can perform varieties of analysis. One

33

of them is DC analysis. DC analysis is performed to determine the operating point of

each device and can also use it to compute the small signal model parameters of the

devices. It also can perform transient response analysis for designed circuit such as

amplifier circuit.

SPICE was developed by University of Carlifornia-Berkerly. There are lots of

SPICE tools in the market and most of them are originated from Berkeley’s SPICE

program. Therefore, it supports common original SPICE syntax. The fundamental

algorithm ideas of SPICE tools are similar, but the control of time-steps, equation

solver and convergence control might be different. In order to perform the SPICE

simulation for given circuit, the user must provide it with circuit description, analysis

requests and output requests. The description of SPICE requirement can be seen in

table 3.1.

Table 3.1: Requirement in SPICE simulation.

Requirement Description

Circuit description A complete description of the circuit to be analyzed,

including its element, the signal source present and how

they connected together and also the parameter value of

models of the electronic devices utilized. All circuit

description must be written into netlist file which acts as

the input file to SPICE program. In SPICE netlist file, it

must have a title in the first line to identify the circuit

being analyzed and it must be ended with .End statement

in last line.

Analysis requests The types of analysis that the user wishes SPICE

program to perform such as transient, AC or DC

analysis.

Output request The type of output that required by user such as gain,

output swing, etc

34

Figure 3.4: An example of netlist file

Figure 3.4 shows an example of netlist file for differential amplifier. As

stated in previous table 3.1, the designer must provide 3 things with SPICE

simulation. Based on figure 3.4, the description of circuit lies in line 10 to line 23

where they represent the circuit elements, the input source and also how transistors

are connected to each other. In figure 3.4, ‘.lib’ represents the SPICE parameter

library that been used in the simulation. In this example, typical node process for 65

nm is used. The ‘.end’ must be included in the last line of netlist file so that the

program can identify the ‘finish’ point of the simulation. A command for the type of

analysis is included in ‘analysis section’ and in this example, AC and transient

analysis are been performed. The output request is included in ‘additional SPICE

commands’. It represents the desired output simulation of the design. In this

example, the gain, the output voltage swing and the output impedance are the desired

output of this simulation.

Line 10-23

35

3.4 SPICE Model Parameter

In order to run a simulation, SPICE model parameter is needed and in this

research, spice model parameter for 130 nm, 90 nm, 65 nm, 45 nm, and 32 nm were

used. These spice model parameter were generated by PTM. The corner model that

have been used in the simulation are TT, SS and FF which represent typical, slow

and fast process corner respectively. The spice model parameter are included in

design’s netlist as a library. Figure 3.5 shows how the SPICE model parameter netlist

files were collected from PTM website.

Figure 3.5: SPICE Model Parameter netlist file

PTM website

-Choose Nano Cmos Function

PTM website

-Select Technology Node Process

-Choose model parameter NMOS

or PMOS

PTM website

-Varition for corner process – 20%

- submit to proceed to get model

parameter

PTM website

-Spice model parameter for

nominal,fast and slow ready for

download.

36

3.4.1 Corner Process

The default value generated by PTM has been used except for the variation

which was to be set up at 20% due to finding in [28]. In process corner, there are 6

spice parameters that been varied in spice net list and its can be seen in table 3.2.

Based on the spice netlist file, the values of these parameters were identified to be

varied in variation process.

Table 3.2: Variation parameter

Spice

parameter Description

lint Length offset fitting parameter from I-V without bias

vth0 Threshold voltage

k1 First order body effect coefficient

u0 Mobility

ndep

Channel doping concentration at depletion edge for zero

body bias

Xj Junction depth

Transistors model were combined into 3 libraries so that it can be used in the

simulation (TSPICE). The library called as typical_xxx is constructed which

represents the combination between typical process for both transistor PMOS and

NMOS model. The combination between both transistor models for slow process is

named as slow_xxx. The combination between fast processes is called fast_xxx. The

_xxx is defined by technology node process such as typical_130 nm which represents

the library for 130 nm PTM technology node. An example of this library is included

in the appendix.

The understanding of DC current-voltage characteristic is essential in circuit

analog design. It provides the data that may help in circuit design and it is true in

design simulation such as to determine bias point for the transistor. The Ids vs Vds

and Ids vs Vgs graphs for typical in each technology node processes can be seen in

figure 3.6 to figure 3.15.

37

i)

ii)

Figure 3.6 : Ids vs Vds and Ids vs Vgs –NMOS (130 nm)

38

i)

ii)

Figure 3.7 : Ids vs Vds and Ids vs Vgs –PMOS (130 nm)

39

i)

ii)

Figure 3.8 : Ids vs Vds and Ids vs Vgs – NMOS (90 nm)

40

i)

ii)


41

i)

ii)


42

i)

ii)


43

i)

ii)


44

i)

ii)


45

i)

ii)


46

i)

ii)


47

Based on both Ids vs Vds and Ids vs Vgs graphs in figures 3.6 - 3.15 , the

data given can be related by the equation Id=Kp(W/2L)(Vgs-VT)2 for saturation

region, Id=Kp(W/L)[(Vgs-VT)Vds-Vds2/2] for linear region and Id=0 for cut-off region .

In general, as higher bias voltage is used, the transistor will switch faster means

higher current will be produced. But for smaller transistor process, eventhough the

same bias voltage and W/L ratio are used, the produced bias current will be smaller.

Please note that in small process, the power supply voltage is reduced, which causes

smaller Vgs-VT region for the transistor to stay in saturation region. The parameter Kp

increases for both NMOS and PMOS for smaller transistor size but as compared to

Vgs-VT, the increament of Kp will not hugely affect the drain current.

For analog design, the specification for current should be determined properly

so that the device can last longer. In order to attain that, the bias voltage for the

transistor should wisely be determined. As transistor size becomes smaller, the

headroom for the transistor becomes more crucial and it obviously can be seen in

smaller dimension, where it becomes harder to determine its value as the voltage

supply is also been scaled down. As we can observed in both Ids vs Vds and Ids vs Vgs

graphs, the different between bias voltage and source voltage of the transistor, Vg-Vs

should be larger than threshold voltage, VT so that the transistor is not operating in

cut-off region. Yet, the (Vgs-VT), Vgt must be smaller than voltage across the

transistor, Vds so that the transistor can operate in saturation region.

48

3.4.2 Voltage Supply, Vdd

For each technology node process, the voltage supply is different from one

another. The designed circuits’ use the voltage supply value proposed by the PTM

and it is illustrated in table 3.3 below.

Table 3.3: Voltage supply for technology node process.

As an example for technology node 65 nm, the designed circuit used a

voltage supply of 1.1 V. This voltage supply arrangement is made so that the

research would cover the actual design trend of technology node which is important

in nanometer regime.

TECHNOLOGY NODE (nm) VDD(V)

130 1.3

90 1.2

65 1.1

45 1

32 0.9

49

3.4.3 Hand Calculation

Hand calculation is one of the important parts in constructing the circuit

design. It can give a lot of idea when doing the optimization technique.

There are 2 ways in starting the design which are through hand calculation or

‘try and error’ method. The hand calculation produced a rough value of ratio (W/L)

for simulation. The amplifiers in figure 3.3 were designed using these two methods.

In simulation, the exact parameters was hardly obtained since the designed circuits

were simulated in BSIM3v3 and BSIM4 which are more details and accurate. In

hand calculation, MOSFET level 1 model was used since it was easier to do the

derivation compared to higher SPICE level. Even though the hand calculation is not

accurate, but it represents the general idea of the design. The derivation below is

made based on figure 3.3. For a given circuit specification, transistors size and bias

voltage for cascode amplifier, differential amplifier and telescopic amplifier can be

obtained from derivation.

3.4.3.1 Derivation for Cascode Amplifier

Please refer to Fig. 3.3 (b). Load is represented by transistor M3.

Vg3 represents the gate voltage for transistor M3.

For transistor M3,

(min) (max)out out outV V V� �

32

3 (max)

2

( )d

p dd out

W I

L k V V

� ��

(3.1)

33 3

2

( / )d

g dd tp

IV V V

k W L� � � (3.2)

50

Transistor M1

1.v outA Gm R� (3.3)

1

1

2 1.n d

vp d

k I WA

L I�� (3.4)

2

1

1

( )

2v p d

n

A IW

L k

��

(3.5)

Vg1 represent the gate voltage for transistor M1.

Vg2 represent the gate voltage for transistor M2.

11 1

2

( / )d

gs tn

IV V

k W L� � (3.6)

Transistor M2

(min) 1( ) 2( )out ds sat ds satV V V� � (3.7)

(min)1 1 2 2

2 2

( / ) ( / )d d

outn n

I IV

k W L k W L� � (3.8)

22

2

(min)1 1

2

2( / )

d

dn out

n

IW

L Ik V

k W L

� ��

��

� �

(3.9)

2 1( )2 2

2

( / )d

g ds sat tn

IV V V

k W L� � � (3.10)

Corner frequency can be obtained using equation 3.11

3

1

2dbout L

FR C�

� (3.11)

51

3.4.3.2 Derivation for Differential Amplifier

Please refer to Fig. 3.3 (a). Current mirror transistors, M3 and M4 represent as load.

(min) (max)ic icV ICMR V� �

Transistor M3 and M4

(3.12)

(3.13)

(3.14)

(3.15)

Transistor M2 and M1

(3.16)

(3.17)

(3.18)

(3.19)

(3.20)

(3.21)

(max) 4 2

4 (max) 2

4 24 4 4

4

42

4 3 4 4

( )2

2

( )

ic dd gs t

gs dd ic t

pds gs t

ds

p gs t

V V V V

V V V V

k WI V V

L

IW W

L L k V V

� � �

� � �

� �

� � � ��

22

2

2 42 4

2 2

2 2 4 2 2

2 22

2 1

2.

1//

2 21 1. .

( )

( )

2

n dsv m out out

out ds dsds ds

n ds nv v

ds ds ds n p

v n p ds

n

k I WA g R R

L

R r rg g

k I W k WA A

L g g I L

A IW W

L L k

� �

� �

� �

� ��

� � ��

��

222 2 2

2

22 2

2

( )2

2

( / )

nds gs t

dsgs t

p

k WI V V

L

IV V

k W L

� �

� �

52

Vg1and Vg2 bias point for transistor M1 and M2

Vg5 is bias voltage for transistor M5

Transistor M5

(3.22)

(3.23)

(3.24)

(3.25)

� �

1 2 (min) 2 5( )

255 5( )

5

52

5 5( )

55 5 1

5

2

2

2

/

g g ic gs ds sat

nds ds sat

ds

n ds sat

dsg gs t

n

V V V V V

k WI V

L

IW

L k V

IV V V

k W L

� � � �

�

� � ��

� � �

53

3.4.3.3 Derivation for Telescopic Amplifier

Please refer to Fig. 3.3 (c)

1( ) 2( ) 4( ) 6( ) 8( )ds sat ds sat ds sat ds sat ds sat ddV V V V V V� � � � � (3.26)

Since transistor M1 carries the largest current, allocate larger voltage across M1,

Vds1(sat)

1( ) 2( ) 3( )

1( ) 2( ) 4( ) 6( ) 8( )

,

, , ,ds sat ds sat ds sat

ds sat ds sat ds sat ds sat ds sat

I I I

V V V V V

�

�

Transistors M6, M7, M8 and M9 suffer from low mobility, allocate each of these

transistors Vds(sat) larger than transistor M2, M3, M4 and M5.

As Initial, allocate Vds(sat) for each transistor M2, M3, M4 and M5 are same.

6( ) 8( ) 2( ) 4( )ds sat ds sat ds sat ds satV V V V� � � (3.27)

Calculate gain for the circuit to see whether it meet the design specification.

(3.28)

(3.29)

Adjust the gain by using gain equation 3.30 and 3.31 information.

W and L for transistor were varied by the same factor to increase Rout.

(3.30)

(3.31)

2

1 2 5 6 9

( ) , ,2

pD gs th

k W W W WI V V

L L L L� �

� � � ��

� �4 4 2 5 6 8

2

out m ds ds m ds ds

v m out

R g r r g r r

A g R

�

�

2 ( / )

1

p d

vd

vd

k I W LA

I

WLA

L I

�

�

� �

� � �

54

To get maximum output swing, bias voltage for transistors M4, M6 and input CM

level must be determined.

Minimum input CM level,

2 1 2 2 1gs ds th ds dsV V V V V� � � � (3.32)

Bias voltage for transistor M4

4(min) 4 2 1gs ds dsV V V V� � � (3.33)

Bias voltage for transistors M6, M1 and M8

(3.34)

(3.35)

(3.36)

To extract pk and nk value, graft dI vs. gsV was plotted. For� , graft dI vs.

Vds was also plotted. Once both grafts were plotted, the pk and nk were obtained

from the graft slope (m) using equation 3.37. Meanwhile for � , it was extracted

using the equation 3.38 below.

2nk W

mL

��

(3.37)

' '

dsd n d dI I v I�� (3.38)

6(max) 6 8

11 1

1

88 8

8

( )

2

( / )

2

( / )

dd gs ds

dth

n

ddd th

p

V V V V

IV V

k W L

IV V V

k W L

� � �

� �

� � �

55

3.4.3.4 Tuning Procedure

In nanometer region, design process of cascode amplifier, differential

amplifier and telescopic amplifier pose a new set of challenges which were difficult

to meet the require specifications. In smaller dimension, the initial calculated W and

L values that were obtained proved could not help meet the design specifications.

Thus fine tune process need to be done. This is simply because the design employed

simple design approach SPICE level 1 process. In another word, the hand calculation

requires employment of details parameters. Note that, all first cut design procedure

was made in typical process.

Since it was hard to meet all circuit specification in all node process , the gain

were chosen first to be maintained in all node processes. The W and L from

calculation is essesntial in design as an initial value for circuit simulation. But it

needed some tuning procedure so that the design can meet the specification. As for

cascode amplifier, in general, the tuning procedure was not difficult since it only

dealt with three transistors. But, as technology node process moved toward smaller

dimension the degree of difficulties increased. The first step in tuning process was to

make sure that the operating regions for entire transistors were in saturation mode.

Equation 3.5 was used as a guideline in the tuning procedure. Then, the W and L

were fined tune to meet the gain specification. This process was done repeatedly

until the circuits met all the design specifications. Once the tuning process was done,

the circuits were simulated in process corner.

Compared to cascode amplifier, the tuning process in differential amplifier

was a lot harder and challenging. This is due to the number of the transistors that

have to be dealt with. Like the cascode amplifier, the degree of difficulties increased

as the design moved toward smaller transistor size. The tuning process began with

transistor operating region. The transistors had to be in saturation mode so that the

design was stable. To meet the design specifications, the information in equation

3.19 is needed. The derivation of differential amplifier was also needed to ensure the

operating region was in saturation mode. Then, the circuits were simulated in process

corner once the design process was completed.

56

As for telescopic amplifier, the degree of difficulties in the tuning process

was the highest amongst the previous circuits. In order to design the circuit, it

requires some technical background in analog design and some intuitive. The

knowledge that obtained from in equation 3.26 until equation 3.36 is essential in the

designs which help in tuning process. With the knowledge of equation and intuitive,

the bias point, W and L size were determined. It took longer iteration design time as

technology process moved toward smaller dimension.

3.4.4 Spice Simulation

Circuit simulations were carried out using TSPICE. For each circuit, it was

simulated using all process corners for 130 nm, 90 nm, 65 nm, 45 nm and 32 nm

node processes. In the simulation, parameters W and L were varied for investigation

purposes. W and L were varied relatively in all designed transistor for each circuits.

Figure 3.16 illustrates on how W and L were varied. All transistors were varied

including the bias voltage transistor from ratio of 1/1 to 2/2, 4/4, 6/6, 8/8 and 10/10.

1 2 4

1 2 4

W W W

L L L � � ��

Figure 3.16: W and L varied relatively in each transistor.

The circuit performance parameters were measured at the end of the

simulation. Gain, cut-off frequency, power dissipation, output voltage swing and

slew rate are the 5 circuit performance parameters that been investigated via this

analysis. Gain is one of the important circuit performance parameters which is

amongst the biggest concern to analog designer. In this matter, the circuit simulations

generate an output file which is used to measure the gain. The gain was measured

using W-Edit tool which is one of the tanner tool part software. The measurement

57

was made at ‘out’ node which can be seen in figure 3.3(a), (b) and (c).In order to

display the graph’s gain simulation, the simulation SPICE command for gain should

be defined. Simulation setting for AC analysis mode was made since the gain was

measured in AC mode.

Simulation setting:

.ac DEC 101 10 800Meg

.print ac vdb(N_5)

From the simulation setting above, the ‘out’ node refer to N_5 node and vdb

means that the graph was plotted in decibel (dB) domain. The spice simulations

generate the graph which can be observed in figure 3.17 and from that graph the gain

for fast corner process is 49.04 dB

The cut-off or corner frequency was measured using the same graph. Because

power is proportional to the square of voltage, the voltage signal is 1/ 2 of the pass

band voltage at the corner frequency. Hence, the corner frequency also known as the

-3dB point because 1/ 2 is approximately -3 decibels. Figure 3.17 also shows how

the corner frequency has been measured.

Figure 3.17: Gain and cut-off frequency measurement.

58

In circuit design, power dissipation is always being the circuit performance

that should be concerned. For analog circuit designer, lower power consumption is

much better than higher power consumption to the same designed circuit. The value

of power dissipation was collected through the output file from spice simulation. The

power dissipation involves the power across the biasing circuits and the designed

circuit. The output files below show the power dissipation for TSPICE simulation

circuit. Power dissipation also can be obtained using equation 3.39. In+1 is the drain

current across bias circuit.

� �1...diss dd d nP V I I �� (3.39)

where n=0,1,2,3,….

The output voltage swing is the maximum peak voltage that the output can

produce before it starts clipping. This voltage is dependent on the voltage supplied to

the circuit - the higher the supply voltage the higher the output voltage swing. Like

gain and corner frequency, the output voltage swing also was measured using W-Edit

tool. The measurement of output voltage swing is shown in equation 3.40 and figure

3.18 below.

o p pV V V�� (3.40)

59

Figure 3.18: Output voltage swing measurement.

3.5 Reuse Design

Table 3.4 shows the simulation result of reuse design for 130 nm and 32 nm

using differential amplifier. This reuse design uses the concept from previous chapter

to explain why this method was not used in this research. In this concept, the

transistors size of the actual design would be scaled using some manipulated factors

to obtain a new transistors size. The value of the scale factor can be obtained as

shown in Table 2.3. Then, the simulation results of these two node processes are

compared.

60

Table 3.4: Reuse design for 130 nm and 32 nm

Table 3.5: Operating Region

Based on simulation result from table 3.4 for each typical, slow and fast

process, in general, the circuit performance slightly changes compared to previous

node process. In power dissipation the result show some positive result where it

decreases more than 50% for each corner process. But, when it comes to the

transistor operating region, for typical process, all the designed transistors are in cut-

off region mode means that the design is not stable. The same thing happens to slow

and fast process too. Based on the result, this research will use a ‘first hand design’

so that the design would be operating in saturation.

Parameter/node process

130nm (typical)

32nm (typical)

130nm (ss)

32nm (ss)

130nm (ff)

32nm (ff)

Gain(dB) 42.97 36.95 44.25 37.36 41.76 36.19

F3dB(kHz) 6.76 4.61 4.61 1.13 9.63 11.99Output

Swing(mV) 137.83 67.64 156.56 55.44 120.24 63.9

PD(uWatt) 55.86 12.74232 41.97762 2.89024 74.7893 34.83192

61

3.6 Summary

This chapter explains how the research has been conducted. It was carried out

in three phases which involved the literature review, circuit design, circuit

simulation, analysis and thesis writing. The research began with literature review

which was carried out to understand the issues of the research. The important files

such as SPICE netlist that has been used in the research were collected and studied.

The circuit design, simulation and the analysis are the core of the research.

The circuit design and the simulation require longer iteration time process especially

when one moves toward smaller dimension. There are 3 types of amplifier that have

been designed which are cascode amplifier, differential amplifier and telescopic

amplifier. The cascode amplifier was chosen so that the impact on analog

performance due to low voltage supply can be observed. The analog performance

that have been investigated in the research are gain, cut-off frequency, output voltage

swing and power dissipation. Note that the phase margin has not been investigated in

the research since only single stage design was used in the circuit design which

ensures stability. There are three main analysis that have been conducted in the

research which are the impact of W and L, the impact of process corner and the

impact of node process to analog performance.

Lastly, this report was prepared to conclude the research. It took four

semesters to complete the research.

62

CHAPTER 4

AN ANALYSIS ON ANALOG CIRCUIT PERFORMANCE

4.1 Analog Performance

Due to the increasing interest in CMOS analog applications, the studies about

the impact of scaling on the analog performance are particularly relevant. In this

chapter, the analysis on several analog circuit performances will be discussed which

are gain, power dissipation, transition frequency, output voltage swing and slew rate.

These analog circuit performances are discussed based on the selected analog circuits

and node processes that have been stated in the earlier chapters. There are 3 types of

analyses that will be discussed in this chapter which involves the analysis on corner

process, the impact of channel width, W and length, L and also the impact of node

process to analog performance.

4.2 The analysis on corner process and node process

As transistor size move toward smaller dimension, process variations become

more crucial especially in analog area. As stated in previous chapters, the analog

circuit which is a cascode amplifier, differential amplifier and differential telescopic

amplifier were simulated using corner process. All of these analog circuits were

simulated on corner processes to observe the impact of process variation (corner

process) on analog performance.

63

Gain measures the ability of a circuit (amplifier) to increase the power or

amplitude of a signal. It’s defined as the mean ratio of the signal output of a system

to the signal input of the same system. In this analysis, the gain was obtained by

using T-Spice and W-Edit waveform editor which are the software tool provided by

Intel Malaysia research grant. The circuit performance simulation results for gain are

discussed in this section. Figure 4.1 (a), (b) and (c) show the simulation result of gain

for cascode amplifier, differential amplifier and telescopic amplifier respectively.

The rest of the simulation result of gain for these three circuits can be viewed in the

appendix section. These figures show the simulation for typical, slow and fast

process. The circuits were designed based on gain so that the comparison between

these node processes can be analyzed. Since, it was hard to design a gain accurately

in every node process, the possible closest value of gain in every node process was

designed.

Figure 4.1 a) Cascode amplifier – 45 nm

64

Figure 4.1 b) Differential amplifiers – 130 nm

Figure 4.1 c) Telescopic amplifiers – 45 nm

Based on the observation in figure 4.1, the simulation results for corner

process in different type of amplifier shows different pattern. Yet, gain is likely less

affected by corner process in differential amplifier compared to cascode amplifier

and telescopic amplifier. In order to get better view and more reliable observation,

the analysis was made where the value of gain (typical, slow and fast) were

manipulated and plotted using equation 4.1.

65

/(%) 100%slow fast typical

typical

A ADifferential

A

��

(4.1)

Figure 4.2 shows the graphs for different values of gain between slow process

and fast process to typical process. This graph was also plotted to observe the affects

of corner process when the designer uses smaller node processes.

Figure 4.2 a) Differential Amplifier

Figure 4.2 b) Cascode Amplifier

66

Figure 4.2 c) Telescopic Amplifier

Based on figure 4.2(a), in overall, the differential amplifier is not severely

affected by corner process where the differential percentage in corner process is only

up to 13%. The margin for both slow typical and fast typical are also small.

Compared to slow and fast processes, the slow process shows the worst margin in

corner process especially in node process 65 nm where it increases to 13%. Even

though the slow process shows the worst result in the differential percentage, the

gain in slow process is actually greater than both typical and fast process which is

good for the design.

Meanwhile in figure 4.2(b), the differential percentage for both slow-typical

and fast-typical decreases from node process 130 nm to 45 nm before they increase

in node process 32 nm (84%). From the observation in figure 4.2(b), in general, the

corner process severely affects the cascode amplifier where the differential

percentage for both slow-typical and fast-typical are quite large which is up to

84%.But in corner process itself, the fast process show the worst gain compared to

typical and fast process in cascode amplifier.

In figure 4.2(c), process corner shows a huge differential percentage for

both fast-typical and slow-typical. From the observation, the telescopic amplifier is

severely affected by fast process in the range from 40%-100% of differential

percentage compared to slow process by 40%-60%. Yet, by referring to figure 4.1(c),

67

it is obvious that both fast and slow processes severely affected the telescopic

amplifier’s performance.

Transition frequency or cut-off frequency is inversely proportional to gain.

Any affection on gain will also affect the cut-off frequency. Figure 4.3 shows the

simulation result for cut-off frequency. For better view, these figures were plotted

based on typical process. In figure 4.3(a), the cut-off frequency of typical process for

cascode amplifier is 104.42 Hz meanwhile in figure 4.3(b) and (c) the cut-off

frequency are 37.75 kHz and 409.26 Hz respectively.

Figure 4.3 a) Cascode amplifier (130 nm)

68

Figure 4.3 b) Telescopic amplifiers (90 nm)

Figure 4.3 c) Differential amplifiers (32 nm)

69

The simulation results of cut-off frequency for corner process were

manipulated using the same equation 4.1 where the differential percentage of cut-off

frequency is plotted versus node process to observe the pattern in smaller dimension.

The plotted graphs are illustrated in figure 4.4.

Figure 4.4 a) Differential amplifiers

Figure 4.4 b) Telescopic amplifiers

70

Based on figure 4.4, the margin of differential percentage on differential

amplifier is less compared to cascode and telescopic amplifier. Overall, the transition

frequency is severely affected by corner process and as a node process moves toward

smaller dimension, the corner processes especially the fast process is likely the one

which mostly affects the cut-off frequency. In telescopic amplifier, the differential

percentage increases as transistor size moves to a smaller dimension. But, as for

cascode amplifier, the differential percentage decreases from node process 130 nm to

45 nm before it increases at node process 32 nm. From figure 4.4, the margin for

telescopic amplifier is huge. The reason of the huge margin is because of the

unpredictable data in process corner due to the linearity of the design.

Power dissipation is one of the most important elements in analog circuit

performances. In analog design, the design of lower power consumption circuit is

important so that the lifetime of the device can be maximized. In that sense, the

issues of low power consumption always been addressed by designers and

researchers. Based on the simulation, the fast process produces more power

dissipation compared to typical and slow process. This is happen in all these 3

amplifier circuits for every node processes. The differential percentage of power

dissipation for each node process can be observed in figure 4.5.

Figure 4.5 a) Differential amplifiers

71

Figure 4.5 b) Cascode amplifiers

Figure 4.5 c) Telescopic amplifiers

Based on figure 4.5, it is obvious that the differential percentage of power

dissipation for fast-typical process show larger different compared to slow-typical for

all three amplifier. It means that the different of power dissipation for fast process –

typical is worst than slow-process since the power dissipation in fast process

originally greater than typical and slow process. In differential amplifier, the

different of slow-typical slowly increases from node process 90 nm to 32 nm in

range from 30% to 41% but in node process 130 nm, the different of slow-typical is

72

around 43%. As for fast-typical process, the differential percentage increases from

node process 130 nm to 45 nm before it slightly decrease at node process 32 nm. The

worst case occurs in node process 45 nm where the differential percentage is 71%

(fast process). Overall, it can be concluded that in differential amplifier, as the

technology node process moves toward smaller dimension, the affect of corner

process would be worst especially in fast process.

In both cascode amplifier and telescopic amplifier, the pattern of differential

percentage is almost the same in every node process for both ss-typical and ff-

typical. From the observation for power dissipation, the differential percentage for

both cascode and telescopic amplifier are severely affected as technology node

process move from 130 nm to 32 nm for both ss-typical and ff-typical. In figure

4.5(a), the differential percentage for ss-typical from node process 130 nm to 90 nm

decreases while in figure 4.5 (b) and (c),the differential percentage increases.

Figure 4.6 a) Differential amplifier

73

Figure 4.6 b) Cascode amplifier

Figure 4.6 c) Telescopic amplifier

74

4.3 The impact of W and L to analog performances

The idea of this analysis is to investigate the impact of analog performance

when the transistor size (W and L) are scale up by x1/1, x2/2, x4/4, x6/6, x8/8 and

x10/10. For a few node processes, the transistor size (W and L) were varied until

x6/6. The process was stop at x6/6 due to unrealistic results obtained for bigger W

and size.

4.3.1 Gain

Figure 4.7 shows the impact of output resistance from W and L analysis.

From the observation on figure 4.7 (a), the output resistance increases in all corner

processes as transistor size is varied from x1/1 to x10/10. But in figure 4.7 (b) and

(c), the output resistance decreases in all corner processes. Like the output resistance,

the gain also shows similar result since the output impedance is proportional to gain.

From figure 4.8(a), in all corner processes, the gain increases as transistor size W and

L increases, meanwhile for figure 4.8(b) and (c), the gain decreases.

Figure 4.7(a): Output resistance for differential amplifier (node process-65 nm)

75

Figure 4.7(b): Output resistance for cascode amplifier (node process-65 nm)

Figure 4.7(c): Output resistance for Telescopic amplifier (node process-130 nm)

From the observation in figure 4.8, as the transistor size, W and L are varied

from x1/1 to x2/2, x4/4, x6/6, x8/8 and x10/10, the gap between plotted corner

process become smaller.This is also true for other node processes which can be seen

in appendix section. A small different value between result in corner process and the

design specification is important especially in fabrication process so that the product

is less dependent on corner process.

020406080

100120140

x1/1 x2/2 x4/4 x6/6

Resi

stan

ce(M

ohm

)

Ratio W/L

Output Resistance vs W/L

typical

slow

fast

0

20

40

60

80

100

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

Resi

stam

ce(M

ohm

)

Ratio W/L

Output Resistance vs W/L

typical

slow

fast

76

Figure 4.8 (a): Gain vs W/L for differential amplifier node process 32 nm

Figure 4.8 (b): Gain vs W/L for cascode amplifier node process 45 nm

Figure 4.8 (c): Gain vs W/L for Telescopic amplifier node process 90 nm

4042444648505254

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

dB

Ratio W/L

Gain vs W/L

typical

slow

fast

0102030405060

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

dB

Ratio W/L

Gain vs W/L

typical

ss

ff

01020304050607080

x1/1 x2/2 x4/4 x6/6

dB

Ratio W/L

Gain vs W/L

typical

slow

fast

77

By referring to figure 4.8 (differential amplifier), for all node processes and

corner process, the gain increases as the transistor size W and L are varied from 1/1

to 10/10. Maximum voltage gain is limited by its source to drain conductance gds.

By increasing the output resistance, more gain could be obtained. This can be seen in

figure 4.7(a) and figure 4.8(a) where the gain for node process 65 nm increases due

to the increasing of output resistance. Equations 4.2 to 4.4 show how gain can be

obtained.

(4.2)

(4.3)

(4.4)

Based on equation 4.4, the (2KpW/L)1/2 is always constant because in the

analysis the ratio of W/L is not change. The parameter� and Id are the ones which

affects the gain. For the saturation region, drain current, Id can be obtained using

equation 4.5 below.

2. .( )2

pd gs t

k WI v v

L ��

(4.5)

E

L

V L� �� (4.6)

Based on equation 4.5, since the ratio W/L is kept constant, the drain current

should be maintained. It means the gain is inversely proportion to� . But, based on

equation 4.6, � decreases due to the increase of transistor length, L. Thus, it can be

concluded that by increasing the L, gain can be increase too

.

2 1.

2 1.

v m out

p dv

d

pv

d

A G R

K I WA

L I

K WA

L I

�

�

�

�

�

78

vL A� (4.7)

4.3.2 Cut-off frequency

In electronic circuits, cutoff frequency or corner frequency is the frequency

either above or below which the power output of a circuit, such as a line, amplifier,

or electronic filter has fallen to a given proportion of the power in the pass band. This

section will discuss the impact of W and L on cut-off frequency. Figure 4.9 below

show the result of cut-off frequency for differential amplifier.

(a)

(b)

0

200

400

600

800

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

Hz

Ratio W/L

F3dB vs W/L

typical

slow

fast

0100200300400500600

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

Hz

Ratio W/L

F3dB Vs W/L

typical

slow

fast

79

(c)

(d)

(e)

Figure 4.9: Cut-off frequency vs W/L for differential amplifier

a) 32 nm b) 45 nm c) 65 nm d) 90 nm e) 130 nm

0

500

1000

1500

2000

2500

3000

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

Hz

Ratio W/L

F-3db vs (W/L)

typical

slow

0

1000

2000

3000

4000

x1/1 x2/2 x4/4

Hz

Ratio W/L

F3dB vs W/L

typical

slow

fast

01234567

x1/1 x2/2 x4/4 x6/6

KHz

Ratio W/L

f3dB vs W/L

typical

slow

fast

80

Based on figure 4.9, the cut-off frequency for every node process and corner

process decreases as transistor size W and L are being scaled up. Like gain, the

difference of cut-off frequency between the corner processes becomes smaller as

transistor size W and L are scaled up. But, in cascode amplifier the cut-off frequency

shows a totally different result as differential amplifier result. Based on figure

4.10(a), (b), (c), and (e) which are for node processes 32 nm, 45 nm, 65 nm and 130

nm respectively, the cut off frequency increases as W and L are varied from 1/1 to

6/6 or 10/10. But, for node process 32 nm, the cut-off frequency decreases in fast

process. In node process 90 nm, the cut-off frequency results show unstable data

which is ignored in this analysis.

(a)

020406080

100120140160

x1/1 x2/2 x4/4 x6/6

Hz

Ratio W/L

F3dB vs W/L

typical

ss

ff

81

(b)

(c)

0

50

100

150

200

250

300

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

kHz

Ratio W/L

F3dB vs W/L

typical

ss

ff

0

1000

2000

3000

4000

5000

x1/1 x2/2 x4/4 x6/6

Hz

Ratio W/L

F3dB vs W/L

typical

slow

fast

82

(d)

(e)

Figure 4.10: Cut-off frequency vs W/L for cascode amplifier


Figure 4.11 below shows the result of transistor sizing for telescopic

amplifier. From the observation, the cut-off frequency is decreasing in the analysis.

But, in node process 32 nm, 45 nm and 90 nm, the cut-off frequency are increasing at

2/2 before it starts to decrease at 4/4. However, the difference between the corner

processes is getting smaller as the transistor size W and L are varied up from 1/1 to

6/6 or 10/10.

02000400060008000

10000120001400016000

x1/1 x2/2 x4/4 x6/6

Hz

Ratio W/L

F3dB vs W/L

typical

slow

fast

0100020003000400050006000

x1/1 x2/2 x4/4 x6/6

Hz

Ratio W/L

F3dB vs W/L

typical

slow

fast

83

(a)

(b)

0

500

1000

1500

2000

2500

3000

3500

x1/1 x2/2 x4/4 x6/6

Hz

Ratio W/L

f3dB vs W/L

typical

slow

fast

05

1015202530

x1/1 x2/2 x4/4 x6/6

kHz

Ratio W/L

F3dB vs W/L

typical

ss

ff

84

(c)

(d)

020406080

100120140

x1/1 x2/2 x4/4 x6/6

kHz

Ratio W/L

F3dB vs W/L

typical

ss

ff

05

10152025303540

x1/1 x2/2 x4/4 x6/6

KHz

Ratio W/L

F3dB vs W/L

typical

slow

fast

85

(e)

Figure 4.11: Cut-off frequency vs W/L for Telescopic amplifier


In the analysis, the cut-off frequency can be obtained using equation 4.8

below. From the equation, it can be found that the cut-off frequency is been

controlled by the parameter of total capacitance and output resistance. This can be

seen in differential amplifier result (figure 4.9) where the cut-off frequency

decreases.

3

1

2 .dBout out

FR C�

� (4.8)

Since the transistor size W and L is been varied, the effect of output

capacitance cannot be ignored since it is also one of the dominant parameters that

effect the cut-off frequency. By varying up the transistor size W, the output

capacitance would increase too because the width is proportional to the output

capacitance. However, in the analysis, the effect of total capacitance is smaller

compared to output resistance which explains the result in figure 4.10.

0100200300400500600700800

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

KKz

Ratio W/L

F3dB vs W/L

typical

slow

fast

86

4.3.3 Power Dissipation

Figure 4.12 shows the result of transistor sizing W and L on power

dissipation. From the observation, there is no severe impact on power dissipation as

transistor size W and L are varied from 1/1 to 6/6 or 10/10. However, the power

dissipation is severely affected by fast process for every node processes.

(a)

(b)

0

50

100

150

200

250

300

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

nWat

t

Ratio W/L

Power Dissipation vs W/L

typical

slow

fast

0

50

100

150

200

250

300

350

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

nWat

t

Ratio W/L


typical

slow

fast

87

(c)

(d)

0

5

10

15

20

25

30

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

uWat

t

Ratio W/L


typical

slow

fast

0

10

20

30

40

50

60

x1/1 x2/2 x4/4

uWat

t

Ratio W/L

Power dissipation vs W/L

typical

slow

fast

88

(e)

Figure 4.12: Power dissipation vs W/L for Differential amplifier


Figure 4.13 shows the result of transistor sizing for cascode amplifier on

power dissipation. Based on the result, the impact of transistor sizing is the same as

differential amplifier where there is no impact. The figure also shows that the fast

process severely affects the power dissipation in every node processes.

(a)

01020304050607080

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L

Power dissipation vs W/L

typical

slow

fast

0100200300400500600700800900

x1/1 x2/2 x4/4 x6/6

nWat

t

Ratio W/L


typical

ss

ff

89

(b)

(c)

(d)

0

5

10

15

20

25

30

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

uwat

t

Ratio W/L


typical

ss

ff

0

20

40

60

80

100

120

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L


typical

slow

fast

020406080

100120140

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L


typical

slow

fast

90

(e)

Figure 4.13: Power dissipation vs W/L for Cascode Amplifier


(a)

0102030405060708090

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L


typical

slow

fast

0

5

10

15

20

25

30

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L


typical

slow

fast

91

(b)

(c)

(d)

05

1015202530

x1/1 x2/2 x4/4 x6/6

uwat

t

Ratio W/L


typical

ss

ff

012345678

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L


typical

ss

ff

0

5

10

15

x1/1 x2/2 x4/4 x6/6

uWat

t

Ratio W/L

Power Dissippation vs W/L

typical

slow

fast

92

(e)

Figure 4.14: Power dissipation vs W/L for Telescopic Amplifier


In figure 4.14 which is the simulation result for telescopic amplifier, there is

also no impact on power dissipation like differential amplifier and cascode amplifier.

In the analysis, the power dissipation can be modeled as equation 4.9 below. The

power dissipation in the analysis is controlled by Id and since the voltage suppy,Vdd

is fixed for given node processes.

d ddP I V� (4.9)

� �2

2d gs T

k WI V V

L ��

(4.10)

From equation 4.9 and 4.10, the power dissipation can be found as equation 4.11

� �2.

2 gs T dd

k WP V V V

L ��

(4.11)

Since the ratio of W/L is not changed, there is no severe impact on current

where in the analysis, the current is assumed to be constant when the transistor size

W and L are scaled up.

0

5

10

15

20

25

30

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

uWat

t

Ratio W/L


typical

slow

fast

93

4.3.4 Output Voltage Swing

The output voltage swing is the maximum peak voltage that the output can

generate before it starts to clip. This voltage is dependent on the voltage supplied to

the amplifier. The higher the supply voltage, the higher the output voltage swing can

be. The result for output voltage swing can be seen in figure 4.15, figure 4.16 and

figure 4.17.

(a)

(b)

0

100

200

300

400

500

600

700

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

mV

Ratio W/L

Output swing vs W/L

typical

slow

fast

0100200300400500600700800

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

mV

Ratio W/L

Output Swing Vs W/L

typical

slow

fast

94

(c)

(d)

600

650

700

750

800

850

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

mV

Ratio W/L

Output swing vs W/L

typicalslowfast

0

50

100

150

200

250

300

350

x1/1 x2/2 x4/4

mV

Ratio W/L

Output swing vs W/L

typical

slow

fast

95

(e)

Figure 4.15: Output voltage swing vs W/L for Differential amplifier


Based on figure 4.15 which represents the result for differential amplifier, the

output voltage swing increases as the transistor size W and L are varied from 1/1 to

6/6 or 10/10.For corner process, there is no severe impact on output voltage swing

when the transistor size is been scaled up.

(a)

050

100150200250300350400450500

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

slow

fast

020406080

100120140160180200

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

ss

ff

96

(b)

(c)

(d)

0100200300400500600

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

mV

Ratio W/L

Output V. Swing vs W/L

typical

ss

ff

0

10

20

30

40

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

slow

fast

020406080

100120140160

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

slow

fast

97

(e)

Figure 4.16: Output voltage swing vs W/L for Cascode amplifier


Figure 4.16 shows the result of output voltage swing for cascode amplifier.

Based on figure 4.16 (a), (b), (c) and (e), the output voltage swing decreases when

the transistor size W and L moves to higher scale. In node process 90 nm, only the

output voltage swing for typical process decreases meanwhile for slow and fast

process, the graph show the unstable result.

(a)

01020304050607080

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

slow

fast

0

20

40

60

80

100

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

slow

fast

98

(b)

(c)

(d)

0

100

200

300

400

500

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

ss

ff

010203040506070

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output Swing vs W/L

typical

ss

ff

0100200300400500600700800

x1/1 x2/2 x4/4 x6/6

mV

Ratio W/L

Output swing vs W/L

typical

slow

fast

99

(e)

Figure 4.17: Output voltage swing vs W/L for Telescopic amplifier


The result of output voltage swing for telescopic amplifier is shown in figure

4.17 above. For every node process, the output voltage swing decreases as transistor

size is been scaled up. But in node process 32 nm, the output voltage swing is

increasing at 2/2 before it decreases at 4/4. As for corner process, the difference

between typical, slow and fast process for output voltage swing become smaller as

the transistor size is been scaled up.

0102030405060708090

100

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

mV

Ratio W/L

Output Swing vs W/L

typical

slow

fast

100

4.4 Summary

The result of the analysis conducted in this section is summarized in table 4.1,

4.2, 4.3 and 4.4. There are 3 types of analysis that have been conducted which are the

impact of node process to analog performance, the impact of corner process on

analog performance and the impact of W and L on analog performance.

Table 4.1 An Impact for Gain

IMPACT

Gain

Differential Cascode Telescopic

Node process positive negative nil

Corner process nil nil nil

W and L positive negative negative

Table 4.2 An Impact for Cut-off frequency

IMPACT

F3dB


Node process negative nil positive

Corner process nil Nil nil

W and L negative Positive(typical) negative

Table 4.3 An Impact for Power Dissipation

IMPACT

Power Dissipation


Node process negative negative negative

Corner process negative(ff) Negative(ff) Negative(ff)

W and L Nil nil nil

101

Table 4.4 An Impact for Output Voltage Swing

IMPACT

Output Voltage Swing


Node process Nil nil nil

Corner process Nil Nil nil

W and L nil Negative negative

As size of transistor continuously scale down and constant changes in the

manufacturing process, a deeper analysis for more advanced technological process is

necessary to be investigated. The performance analysis of nanometer transistor on

differential amplifier shows more reliable compared to cascode and telescopic

amplifiers which give us a hint that the usage of differential amplifier in smaller

dimensions of transistors could help solve design issues.

102

CHAPTER 5

CONCLUSIONS AND RECOMMENDATIONS

5.1.1 Summary and Conclusion

The impact of nanometer transistors on analog performances were analyzed

in this research. The node technology process which are 130 nm, 90 nm, 65 nm, 45

nm and 32 nm were used in simulation for each differential amplifier, cascode

amplifier and telescopic amplifier circuits. The impact on analog performance should

be investigated to observe its trend when the technology node processes move

toward smaller dimension. In a competitive market, this knowledge is essential

especially to analog designer to design or redesign with a lesser time so that the

product can arrive to market early. Yet, a faster and reliable design solution should

be explored so that the design can meet the design specification with lesser design

time. The research has fulfill the objectives which are to study the impact of vertical

scaling on analog circuit performance, to evaluate the effectiveness of design reuse

and to find out the degree of design difficulty when design migrates to nano region

process.

Simulations were done to analyze the impact of nanometer transistor on

analog performance. The analyses included the impact of node processes to the

differential of corner process, the impact of corner process and the impact of

transistor size W and L on analog performance. By comparing the three chosen

103

amplifiers, the result of differential amplifier shows more reliable, predictable and

gives positive impact on analog performance.

From simulation, in each node process and amplifiers, the impact of corner

process on analog performance shows different result for each chosen amplifier. But,

for every node process and amplifier, fast process shows negative impact to analog

performance. In differential amplifier, the analog performance such as gain, cut-off

frequency and voltage output swing show almost no impact by corner process. For

telescopic amplifier, the corner process shows negative impact for gain and voltage

output swing but for cut-off frequency, there is no impact.

The second analysis is the impact of node process. For differential amplifier,

the analog performance such as gain, cut-off frequency and power dissipation show

negative impact meanwhile for voltage output swing there is no impact.

Finally, the impact of W and L on analog performance was analyzed by

manipulating the transistor size. For different type of amplifiers, the results lead to

different set of impacts on analog performance. For differential amplifier, the gain

shows positive impact with increment of W and L. But, for cut-off frequency it

produces negative impact. For both power dissipation and output voltage swing,

there are no severe impact in the analysis. The analysis of W and L on analog

performance for cascode amplifier and telescopic amplifier produce unstable results

where the plotted graphs show unexpected results. This is hard to determine the

actual impact especially when different node processes are taken into consideration

which produces unpredictable result. But, like differential amplifier there is also no

severe impact on power dissipation.

104

Small transistor size brings new design challenges. It takes longer iteration

process to meet all design specifications. This is shown in table 5.1 where its take

longer time to design when node processes moves toward to smaller dimension. The

duration of design time for each amplifier is based from rough estimation tim.e

Based on table 5.1 and figure 5.1, it take extra time to design a complex circuit and

also design analog circuit in smaller transistor size. It is more difficult for example to

achieve high gain performance. Using conventional design approach may require the

usage of extra W and L at the expense of speed, linearity, power dissipation and etc.

Table 5.1: Duration of the design

Amplifier 130 nm 90 nm 65 nm 45 nm 32 nm

Cascode 2 days 2 days 3 days 4 days 6 days

Differential 3 days 5 days 7 days 7 days 10 days

Telescopic 7 days 10 days 15 days 16 days 27 days

Figure 5.1: Design time

0

5

10

15

20

25

30

130 90 65 45 32

Days

Node Process (nm)

Design Time

Cascode Amplifier

Differential Amplifier


105

5.2 Recommendations

Written below is a list of suggestion which can be considered to extend this research

work.

(i) The designed circuit should be fabricated to obtain real

measurements.

(ii) Embark on a research to design novel circuits which their

performances are less dependent on process technology.

106

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down,” IBM J. Res. & Dev, 2002. 169-180.

27. Ian A.Young , “ Analog mixed-signal circuits in advanced nano-scale CMOS technology for microprocessors and SoCs”, Proceedings of the ESSCIRC, 2010.61-70.

28. A. Baschirotto, V. Chironi, G. Cocciolo, S. D’Amico, M. De Matteis, P. Delizia, “Low Power Analog Design in Scaled Technologies”, Topical Workshop on Electronics for Particle Physics, Paris, France, 2009. 103-110.

109

APPENDIX A

Telescopic amplifier 130 nm

Telescopic amplifier 90 nm

05

10152025303540

x1/1 x2/2 x4/4 x6/6 x8/8 x10/10

Gai

n(dB

)

Ratio

Gain vs W/L

typical

slow

fast

01020304050607080

x1/1 x2/2 x4/4 x6/6

Gai

n(dB

)

Ratio

Gain vs W/L

typical

slow

fast

110

Differential amplifier 130 nm

0

10

20

30

40

50

60

x1/1 x2/2 x4/4 x6/6

dB

Ratio W/L

Gain vs W/L

typical

slow

fast

111

APPENDIX B

Netlist file for node process 130 nm –typical

.lib typical_130nm

.model pmos pmos level = 54

+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0

+capmod = 2 igcmod = 0 igbmod = 0 geomod = 1

+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1

+permod = 1 acnqsmod= 0 trnqsmod= 0

* parameters related to the technology node

+tnom = 27 epsrox = 3.9

+eta0 = 0.0092 nfactor = 1.5 wint = 5e-09

+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08

* parameters customized by the user

+toxe = 2.35e-09 toxp = 1.6e-09 toxm = 2.35e-09 toxref = 2.35e-09

+dtox = 7.5e-10 lint = 1.05e-08

+vth0 = -0.337 k1 = 0.433 u0 = 0.00796 vsat = 70000

+rdsw = 240 ndep = 1.22e+18 xj = 3.92e-08

*secondary parameters

+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1

+lwl = 0 wwl = 0 xpart = 0

+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2

112

+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0

+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009

+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0

+cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0

+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12

+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56

+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007

+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006

+rsh = 5 rsw = 85 rdw = 85

+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008

+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005

+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002

+egidl = 0.8

+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002

+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004

+eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012

+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008

+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1

+xrcrg1 = 12 xrcrg2 = 5

+cgbo = 2.56e-011 cgdl = 2.653e-10

+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1

+moin = 15 noff = 0.9 voffcv = 0.02

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000

113

+fnoimod = 1 tnoimod = 0

+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1

+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1

+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1

+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1

+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010

+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5

+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1

+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001

+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001

+xtis = 3 xtid = 3

+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007

+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008

+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15

+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

* Customized PTM 130nm NMOS

.model nmos nmos level = 54








+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08

114



+dtox = 6.5e-10 lint = 1.05e-08

+vth0 = 0.388 k1 = 0.474 u0 = 0.05852 vsat = 100370

+rdsw = 200 ndep = 1.6e+18 xj = 3.92e-08

* secondary parameters

+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2


+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009

+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04

+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5

+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007


+rsh = 5 rsw = 85 rdw = 85

+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0



+egidl = 0.8



115





+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



116

.endl

117

Netlist file for node process 130 nm –slow

* Customized PTM 130nm PMOS: ss

.lib ss_130nm









+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08



+dtox = 7.5e-10 lint = 5.6e-09

+vth0 = -0.366 k1 = 0.458 u0 = 0.00733 vsat = 70000

+rdsw = 240 ndep = 1.37e+18 xj = 4.704e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


118

+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000





119


+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



* Customized PTM 130nm NMOS: ss









+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08



+dtox = 6.5e-10 lint = 5.6e-09

+vth0 = 0.416 k1 = 0.499 u0 = 0.05651 vsat = 100370

+rdsw = 200 ndep = 1.77e+18 xj = 4.704e-08

120


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10

121



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

122

Netlist file for node process 130 nm –fast

* Customized PTM 130nm PMOS: ff

.lib ff_130nm









+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08



+dtox = 7.5e-10 lint = 1.54e-08

+vth0 = -0.305 k1 = 0.405 u0 = 0.00869 vsat = 70000

+rdsw = 240 ndep = 1.22e+18 xj = 3.136e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


123

+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000





124


+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



* Customized PTM 130nm NMOS: ff









+cgso = 2.4e-10 cgdo = 2.4e-10 xl = -6e-08



+dtox = 6.5e-10 lint = 1.54e-08

+vth0 = 0.357 k1 = 0.447 u0 = 0.06086 vsat = 100370

+rdsw = 200 ndep = 1.6e+18 xj = 3.136e-08

125


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10

126



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

127


.lib typical_90nm

* Customized PTM 90nm PMOS









+cgso = 1.9e-10 cgdo = 1.9e-10 xl = -4e-08



+dtox = 7.5e-10 lint = 7.5e-09

+vth0 = -0.356 k1 = 0.443 u0 = 0.00675 vsat = 70000

+rdsw = 200 ndep = 1.53e+18 xj = 2.8e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

128

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






129

+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.9e-10 cgdo = 1.9e-10 xl = -4e-08



+dtox = 6.5e-10 lint = 7.5e-09

+vth0 = 0.408 k1 = 0.486 u0 = 0.05383 vsat = 113760

+rdsw = 180 ndep = 2.02e+18 xj = 2.8e-08


130

+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



131

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

132



.lib ss_90nm









+cgso = 1.9e-10 cgdo = 1.9e-10 xl = -4e-08



+dtox = 7.5e-10 lint = 4e-09

+vth0 = -0.385 k1 = 0.469 u0 = 0.00618 vsat = 70000

+rdsw = 200 ndep = 1.71e+18 xj = 3.36e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

133

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

134






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.9e-10 cgdo = 1.9e-10 xl = -4e-08



135

+dtox = 6.5e-10 lint = 4e-09

+vth0 = 0.437 k1 = 0.511 u0 = 0.05171 vsat = 113760

+rdsw = 180 ndep = 2.24e+18 xj = 3.36e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8






136


+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

137



.lib ff_90nm









+cgso = 1.9e-10 cgdo = 1.9e-10 xl = -4e-08



+dtox = 7.5e-10 lint = 1.1e-08

+vth0 = -0.325 k1 = 0.416 u0 = 0.00741 vsat = 70000

+rdsw = 200 ndep = 1.53e+18 xj = 2.24e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

138

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

139






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.9e-10 cgdo = 1.9e-10 xl = -4e-08



140

+dtox = 6.5e-10 lint = 1.1e-08

+vth0 = 0.377 k1 = 0.458 u0 = 0.05617 vsat = 113760

+rdsw = 180 ndep = 2.02e+18 xj = 2.24e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8






141


+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

142



.lib typical_65nm









+cgso = 1.5e-10 cgdo = 1.5e-10 xl = -3e-08



+dtox = 7.5e-10 lint = 5.25e-09

+vth0 = -0.378 k1 = 0.456 u0 = 0.00548 vsat = 70000

+rdsw = 165 ndep = 1.97e+18 xj = 1.96e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

143

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

144






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.5e-10 cgdo = 1.5e-10 xl = -3e-08



+dtox = 6.5e-10 lint = 5.25e-09

+vth0 = 0.429 k1 = 0.497 u0 = 0.04861 vsat = 124340

145

+rdsw = 165 ndep = 2.6e+18 xj = 1.96e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







146

+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

147


.lib ss_65nm










+cgso = 1.5e-10 cgdo = 1.5e-10 xl = -3e-08



+dtox = 7.5e-10 lint = 2.8e-09

+vth0 = -0.406 k1 = 0.481 u0 = 0.00498 vsat = 70000

+rdsw = 165 ndep = 2.19e+18 xj = 2.352e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


148

+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000





149


+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.5e-10 cgdo = 1.5e-10 xl = -3e-08



150

+dtox = 6.5e-10 lint = 2.8e-09

+vth0 = 0.458 k1 = 0.522 u0 = 0.04653 vsat = 124340

+rdsw = 165 ndep = 2.87e+18 xj = 2.352e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8






151


+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

152


.lib ff_65nm










+cgso = 1.5e-10 cgdo = 1.5e-10 xl = -3e-08



+dtox = 7.5e-10 lint = 7.7e-09

+vth0 = -0.346 k1 = 0.429 u0 = 0.00609 vsat = 70000

+rdsw = 165 ndep = 1.97e+18 xj = 1.568e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

153

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






154

+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.5e-10 cgdo = 1.5e-10 xl = -3e-08



+dtox = 6.5e-10 lint = 7.7e-09

155

+vth0 = 0.398 k1 = 0.47 u0 = 0.05098 vsat = 124340

+rdsw = 165 ndep = 2.6e+18 xj = 1.568e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8






156


+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

157



.lib typical_45nm









+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08



+dtox = 7.5e-10 lint = 3.75e-09

+vth0 = -0.418 k1 = 0.488 u0 = 0.00439 vsat = 70000

+rdsw = 155 ndep = 2.5e+18 xj = 1.4e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

158

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

159






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08



+dtox = 6.5e-10 lint = 3.75e-09

+vth0 = 0.469 k1 = 0.528 u0 = 0.04372 vsat = 147390

+rdsw = 155 ndep = 3.28e+18 xj = 1.4e-08


160

+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



161

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

162



.lib ss_45nm









+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08



+dtox = 7.5e-10 lint = 2e-09

+vth0 = -0.446 k1 = 0.512 u0 = 0.00397 vsat = 70000

+rdsw = 155 ndep = 2.76e+18 xj = 1.68e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

163

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

164






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08



+dtox = 6.5e-10 lint = 2e-09

+vth0 = 0.498 k1 = 0.554 u0 = 0.04175 vsat = 147390

+rdsw = 155 ndep = 3.6e+18 xj = 1.68e-08


165

+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



166

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

167



.lib ff_45nm









+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08



+dtox = 7.5e-10 lint = 5.5e-09

+vth0 = -0.387 k1 = 0.46 u0 = 0.0049 vsat = 70000

+rdsw = 155 ndep = 2.5e+18 xj = 1.12e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

168

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1

169






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08



+dtox = 6.5e-10 lint = 5.5e-09

+vth0 = 0.438 k1 = 0.501 u0 = 0.04595 vsat = 147390

+rdsw = 155 ndep = 3.28e+18 xj = 1.12e-08


170

+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



171

+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

172



.lib typical_32nm









+cgso = 8.5e-11 cgdo = 8.5e-11 xl = -1.4e-08


+toxe = 1.75e-09 toxp = 1e-09 toxm = 1.75e-09 toxref = 1.75e-09

+dtox = 7.5e-10 lint = 2.7e-09

+vth0 = -0.452 k1 = 0.514 u0 = 0.0035 vsat = 70000

+rdsw = 150 ndep = 3.1e+18 xj = 1.008e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

173

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000





174


+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 8.5e-11 cgdo = 8.5e-11 xl = -1.4e-08



+dtox = 6.5e-10 lint = 2.7e-09

+vth0 = 0.501 k1 = 0.552 u0 = 0.03936 vsat = 178470

+rdsw = 150 ndep = 4.03e+18 xj = 1.008e-08

175


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10

176



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

177



.lib ss_32nm









+cgso = 8.5e-11 cgdo = 8.5e-11 xl = -1.4e-08



+dtox = 7.5e-10 lint = 1.44e-09

+vth0 = -0.481 k1 = 0.539 u0 = 0.00315 vsat = 70000

+rdsw = 150 ndep = 3.41e+18 xj = 1.2096e-08


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

178

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






179

+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 8.5e-11 cgdo = 8.5e-11 xl = -1.4e-08



+dtox = 6.5e-10 lint = 1.44e-09

+vth0 = 0.53 k1 = 0.578 u0 = 0.03746 vsat = 178470

+rdsw = 150 ndep = 4.41e+18 xj = 1.2096e-08

180


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10


181


+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

182



.lib ff_32nm









+cgso = 8.5e-11 cgdo = 8.5e-11 xl = -1.4e-08



+dtox = 7.5e-10 lint = 3.96e-09

+vth0 = -0.421 k1 = 0.486 u0 = 0.00394 vsat = 70000

+rdsw = 150 ndep = 3.1e+18 xj = 8.064e-09


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = -0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.05 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.126 etab = 0

183

+vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0

+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10



+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






184

+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008












+cgso = 8.5e-11 cgdo = 8.5e-11 xl = -1.4e-08



+dtox = 6.5e-10 lint = 3.96e-09

+vth0 = 0.47 k1 = 0.525 u0 = 0.04151 vsat = 178470

+rdsw = 150 ndep = 4.03e+18 xj = 8.064e-09

185


+ll = 0 wl = 0 lln = 1 wln = 1

+lw = 0 ww = 0 lwn = 1 wwn = 1


+k2 = 0.01 k3 = 0

+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2



+dvtp1 = 0.1 lpe0 = 0 lpeb = 0

+ngate = 2e+020 nsd = 2e+020 phin = 0


+voff = -0.13 etab = 0

+vfb = -0.55 ua = 6e-010 ub = 1.2e-018

+uc = 0 a0 = 1.0 ags = 1e-020

+a1 = 0 a2 = 1.0 b0 = 0 b1 = 0

+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04




+rsh = 5 rsw = 85 rdw = 85




+egidl = 0.8







+cgbo = 2.56e-011 cgdl = 2.653e-10


186


+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5

+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0

+at = 33000






+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1






+xtis = 3 xtid = 3


+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008



.endl

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IMPACT OF NANOMETER TRANSISTOR ON ANALOG