Impact of Statistical Variability and Charge Trapping on 14 nm SOI

FinFET SRAM Cell Stability !

X. Wang1, B. Cheng1, A.R. Brown2, C. Millar2, J. B. Kuang3, S. Nassif3, A.

Asenov1,2!!!1 Device Modelling Group, University of Glasgow, UK !

2 Gold Standard Simulations Ltd, UK 3 IBM Research – Austin, USA !!ESSDERC, 16-20 September 2013, Bucharest Romania! 1!

Outline!q  Introduction!q  14 nm node DG SOI FinFETs!q  Simulation of Random Charge Trapping and Statistical Variability Sources!q  Compact Modelling Methodology!q  Charge Trapping Impact on SRAM SNM!q  Charge Trapping Impact on SRAM WNM!q  Summary!

2!

Introduction •  Why this study?!•  Novel 3-D architecture FinFET will be widely adopted at

14 nm technology, with reduced variability on SOI substrate due to tolerance to low channel doping.!

•  However, (1) statistical aspect of reliability due to random individual trapping becomes an increasingly important issue. (2) In addition, charge trapping impact is affected by statistical variability sources.!

•  Accurately modeling reliability of nanoscale transistors in circuit level should take care of above mentioned properties, therefore requires a “statistical” method, rather than describing average reliability behavior.!

•  SRAM stability is susceptible to variability, therefore statistical study is needed.!

3!

FinFET

Intel!22nm!!

TSMC!Chang et.,

IEDM,2009!

IMEC!Veloso et.

IEDM, 2009!

IBM!Chang et., VLSI tech.,

2011!

Bulk substrate! SOI substrate!

Fin Edge Roughness:! width, height, slope!

4!

Simulation Design of 14nm SOI FinFETs (GU-IBM collaboration)

Ref.: ITRS 2010 update!

Double-Gate !SOI FinFET!

!

Lg (nm)! 20!EOT (nm)! 0.8!WF (nm)! 10!HF (nm)! 25!NSD (cm-3 )! 3.0E20!NCH (cm-3 )! 1.0E15!VDD (V)! 0.9!IOFF (nA/μm) ! 10!IDSAT (mA/μm) ! 0.9/0.8!DIBL (mV/V)! 56/65!

Wfin

tox

Hfin

LG

BURIED OXIDE

SUBSTRATE

SOURCE

GATE

DRAIN

HMMC calibrated @ 85°C!

20 30 40 50Position [nm]

0.0

0.5

1.0

1.5

2.0

2.5

Veloc

ity [x

107 cm

s-1 ] source drain

Default DD

Calibrated DD

VG 0.4- -0.8!

Monte Carlo!

5!

Intrinsic Parameter Fluctuations Statistical Variability Sources

Random dopants! Polysilicon/Metal Gate!Granularity!

Line Edge Roughness!

potential!

TiN!

6!

Statistical variability simulation

•  Each variability source has different impact on the device parameters and performance.!

RDD: ΔRSD , ΔNA!

FER: ΔWFIN , Δconfinement!

GER: ΔLG , ΔSCE!

MGG: ΔΦM , Δψsurf !

Wang, et al, IEDM 2011, pp103-106!

ΔRSD!

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Interaction: Charge trapping vs Statistical variability sources

•  FER: local shortenings!

•  MGG: metal grains with high currents underneath!

•  RDD: current percolation paths!

8!

Sensitive regions!

Wang et al, SISPAD 2012, pp.296-299!

Vt RTS Distribution and Reliability are affected by Statistical Variability

9!

0 2 4 6 8 10VT (mV)

0.001

0.01

0.1

1

1-CD

F

Uniform Device’Atomistic’ Devices

Single Trapping

Single Trapping!

Wang et al., SNW 2012, pp.77-78!•  In the presence of SV, the RTS distribution tail is increased!

Uniform device! Atomistic device!

RTS: random telegraph signal!

Multi-trapping!

Random charge trapping effect on VT

•  First, the average VT shift increases with degradation heuristically;!

•  Most important, the statistical variability increases with degradation.!

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0.1 0.15 0.2 0.25 0.3 0.35 0.4VT (V)

-4

-2

0

2

4

Nor

mal

Qua

ntile

01E115E111E12

Trapping Density (cm-2)

Poisson distribution !of trapping charge !number is assumed!

Statistical Compact Modelling Method

•  A small set of BSIM-CMG compact model parameters is used to extract statistical samples at fresh stage, also applied to degradation.!

•  In circuits random fresh samples are assigned, responding stressed samples are put for stressed transistors.!

•  Assume trapping effect is dynamically recoverable.!

•  e.g., M2 is biased with high VG and low VD, subject to PBTI!

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6-Transistor SRAM cell!

retention!

PU!

PD!

PG! PG!

PU: pull-up transistor, p-FinFET;!

PD: pull-down transistor, n-FinFET;!

PG: pass-gate transistor, n-FinFET;!

What happens to SRAM SNM after stress?

•  Generally, stress induced trapping leads to less static noise margin !

•  Heavier N/PBTI, more threshold shift, less stability!!

12!

0 0.2 0.4 0.6 0.8VL (V)

0

0.2

0.4

0.6

0.8V

R (V

)

Fresh Stress (state A)Stress (state B)

A

B

SNM(A)

SNM(B)

SNM: static noise margin, the SRAM stability for read mode!State A: left 0, right 1; State B: left 1, right 0!

SNM Distribution

•  First of all, the distribution is non-Gaussian.!•  Compared with 111-fin SRAM cells, 112-fin cells

increase SNM.!•  With charge trapping induced degradations, the SNM

is reduced.!13!

Two types of SRAM cells!with fin-number ratio!

of PU:PG:PD,!111 SRAM and 112 SRAM!

are examined!

Charge trapping effects on SNM

•  The average SNM is reduced by up to 30 mV, with charge trapping induced degradations.!

•  The statistical variation of SNM increases by 30-40% with degradation.!

•  112-fin SRAM cells show better stability. Compared with 111-fin cells, 112-fin cells increases SNM by ~45% in average.!

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0 2e+11 4e+11 6e+11 8e+11 1e+12Trapping Density (cm-2)

100

150

200

250SN

M (m

V)

SNM(A), 1:1:1SNM, 1:1:1SNM(A), 1:1:2SNM, 1:1:2

0 2e+11 4e+11 6e+11 8e+11 1e+12Trapping Density (cm-2)

6

8

10

12

14

16

18

20

SNM

(mV

)

SNM(A), 1:1:1SNM, 1:1:1SNM(A), 1:1:2SNM, 1:1:2

What happens to SRAM WNM after stress?

!•  In contrary to SNM, WNM increases a bit due to

charge trapping.!•  The WNM distribution is non-Gaussian.!

15!

0 0.2 0.4 0.6 0.8VR (V)

0

0.2

0.4

0.6

0.8V

L (V

) FreshStressed

WNM

WNM: write noise margin, SRAM stability for write mode!

Charge trapping effects on WNM

•  The average WNM increases after stress, which is contrary to read SNM.!

•  The standard deviation of WNM increases after stress, which is similar to read SNM.!

16!

0 2e+11 4e+11 6e+11 8e+11 1e+12Trapping Density (cm-2)

320

340

360

380

400

420

WN

M (m

V)

WNM (state A), 1:1:1WNM, 1:1:1WNM (state A), 1:1:2WNM, 1:1:2

0 2e+11 4e+11 6e+11 8e+11 1e+12Trapping Density (cm-2)

8

10

12

14

16

WN

M (m

V)

WNM (state A), 1:1:1WNM, 1:1:1WNM (state A), 1:1:2WNM, 1:1:2

SNM vs WNM with SV and random charge trapping

•  Anti-correlation between SNM and WNM exists for one storing node.!

•  Minimum defined SNM and WNM show decorrelations, due to statistically independent transistors responding to two storing states.!

17!

0 2e+11 4e+11 6e+11 8e+11 1e+12Trapping Density (cm-2)

-0.8

-0.6

-0.4

-0.2

0

Corre

latio

n Co

effic

ient

(VL=’0’,VR=’1’), 1:1:1Minimum, 1:1:1(VL=’0’,VR=’1’), 1:1:2Minimum, 1:1:2

Correlation between SNM and WNM

Impact on Six-sigma yield stress induced degradations

•  6-sigma of read SNM is greatly affected by stress induced charge trapping, not only due to average SNM reduction, but also by boosted statistical variability. !

•  112-fin SRAM cells show much better stability than high-density fin cells.!

18!

0 2e+11 4e+11 6e+11 8e+11 1e+12Trapping Density (cm-2)

0

100

200

300

400

µ -

6 (m

V)

SNM, 1:1:1SNM, 1:1:2WNM, 1:1:1WNM, 1:1:2

Summary •  The random charge trapping effect can be

accurately captured using the similar statistical compact modelling practice with statistical variability.!

•  SRAM cell read stability is degraded by stress induced charge trapping; The statistical variation of SNM and WNM increased with degradations.!

•  112 FinFET SRAM shows much better stability compared with high-density SRAM cells.!

•  With the more random trapping, the read SNM six-sigma yield is reduced dramatically due to enhanced variation. !

19!

Acknowledge

•  It is in part supported by Scottish Funding Council through Knowledge Transfer Project “Statistical Design and Verification of Analogue Systems”.!

!!

!!!Thank you for your attention.!

!! !

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