Implementation of UTOPIA Level 2 for Parallel Cell / Tr a ...literature.cdn.keysight.com/litweb/pdf/5965-4856E.pdfImplementation of UTOPIA Level 2 for Parallel Cell / Traffic Generator

Implementation of UTOPIA Level 2 for Parallel Cell / Traffic Generator and Analyzer, Page 1

Product NumberHP E4829B

Implementation of UTOPIA Level 2for Parallel Cell / Tr a ffic Generatorand AnalyzerHow to use the HP E4829B with UTOPIA Level 2implementation

Product Note

Introduction

The latest design of ATM layerdevices and ATM switches allowsa bandwidth of up to 622 Mbit/sper port. However, typical linerates in ATM backbones are still inthe range of 25 to 155 Mbit/s. Inorder to allow multiple physicalinterfaces to connect to one ATMlayer, the ATM forum defined theUTOPIA Level 2 MultiPHYstandard. Not only does higherintegration lead to lower costs, butthere is also a greater bandwidth.

Application

In “UTOPIA, an ATM-PHY Inter-face Specification, Level 2” [1], theATM forum released the speci-fication for multiple interfaces(MultiPHY). The various interfacesare described in chapters 4.2, 4.3,and in the appendix of the ATMforum’s UTOPIA Level 2 speci-fication. The most important

modes are: single Clav polling(chapter 4.2) and direct statusindication (chapter 4.3).

The MultiPHY interface usuallyoccurs between PHY devices/lineinterface cards (LIFs) and theATM layer device. PHY/LIFs hostone or multiple ports with typicalline rates ranging from 1.5 to 155 Mbit/s. The ATM layer itselftypically handles 622 Mbit/s.

Following the industry’s trends,the HP E4829B supports UTOPIALevel 2 according to chapters 4.2and 4.3, with the PODs HP E4885A/E4886A handling the UTOPIALevel 2 handshake and signaling.

Existing HP E482xA/B systemscan be upgraded by adding newsoftware and PODs. UTOPIA Level 2 is supported from softwarerevision A.2.4, which detectswhich interfaces are connectedand automatically adapts thesystem software so that itfunctions properly. UTOPIA Level 1 and custom interfaces aresupported by HP E4889A PODs. It is possible to mix operatingmodes in a system which has morethan one module. Table 1summarizes which interfacessupport the UTOPIA specification.It is not possible to mix Level 1/Level 2 operation within onemodule.

Figure 2: Block diagram of an ATM switch showing the HP E4829Bconnecting to parallel interfaces

Figure 1: HP E4829B entry system

LIF board


With UTOPIA Level 2, the testsystem emulates the ATM layerdevice as well as one or multiplephysical ports (PHY device or LIFboard). It handles the addresspolling and port selection for up to31 physical ports in single Clavpolling mode (chapter 4.2) and upto four static Clav signals in directstatus indication mode (chapter4.3). Individual traffic rates perport can be emulated. Theinterface is 8/16 bit wide, runningat a clock speed of up to 50 MHz(equivalent to 400/800 Mbit/s). Inthis description, the followingterminology is used:

• TX ATM: transmits data to thePHY layer.

• TX PHY: receives data from theATM layer.

• RX PHY: transmits data to theATM layer.

• RX ATM: receives data fromthe PHY layer.

ATM layer emulation

The system replaces the TX ATMand the RX ATM, as indicated infigure 3. The emulation of the TX ATM is performed by the TX POD (HP E4885A), whereas for the emulation of the RX ATM,the RX POD (HP E4886A) is used.Both PODs generate the addresssignals normally provided by theATM layer device.

PHY device emulation

The system replaces the RX PHYand the TX PHY, as indicated infigure 4. The emulation of the RX PHY is performed by the TX POD (HP E4885A), whereasthe TX PHY is emulated with theRX POD (HP E4886A). Both PODsare capable of detecting addresses,a function normally performed bythe PHY layer device. In order tobring up and debug boards, thesystem can also emulate singlemissing PHY devices on the testboard.

Compatibility

The functional verification of ATMdesigns can be carried out by aUTOPIA Level 1-compliant system.The compatibility betweenUTOPIA Level 1 and Level 2 allowsLevel 2 interfaces to beinterconnected and act as a singleport. However, this only permitsfunctional verification.

In the same way, a Level 1-compliant device can be fullytested by a Level 2 solution (indirect status indication mode). Thesystem can be set up to deal withonly one port to ensure that Clavsignals which have not been usedare de-asserted.

Polling and selection

As described in chapter 4.2 of theUTOPIA Level 2 specification, thedifferent MPHY ports must bepolled during one cell transfercycle. Two clock cycles areneeded for the ATM layer to pollthe status of one MPHY port. If thecell size is 27 words/53 bytes,typically 13/26 different ports canbe polled during one cell transfer(in the 16/8 bit mode).

The HP E4829B supports anycombination of ports to be active.The active ports are always polledin ascending order. The port addresscan be selected from the completefive bit address range (0 to 31).

Figure 5: Signaling generation for a systemusing the RX PODTable 1: UTOPIA specification and interfacing of the HP E4829B

Figure 3: ATM layer emulation

Figure 4: PHY device emulation

Specification Level 1 Level 2, chapter 4.2 Level 2, chapter 4.3Terminology single PHY MPHY, MPHY, direct

single Clav polling status indicationNumber of ports 1 1 to 31 1 to 4Number of 1 1 1 to 4Clav signalsPriority required required optionalInterface HP E4889A (TX) HP E4885A (TX) HP E4886A (RX)

System emulates ATM layer / switching device

IUT IS RX PHY

System is RX ATM,RX POD connected.

System is TX ATM,TX POD connected.

IUT IS TX PHY

System emulates PHY device / ports

IUT IS RX ATM

System is RX PHY,TX POD

connected.

ATMlayer

ATMlayer

Switchmatrix

System is TX PHY,RX POD

connected.

IUT IS TX ATM


Depending on the polling results,the HP E4829B (ATM layer) has todecide which port to serve first.Together with the TX POD (HP E4885A), the system providesan individual cell sequence foreach port which is defined fromone of the four prioritized trafficgenerators according to theparameters Tcell and Tpause.

Clav signaling

Together with the RX POD (HP E4886A), the system offersfour priority encoded signalinggenerators. Any port can beflexibly assigned to any one ofthem. For the RX ATM, thesignaling generators are priorityencoded. The higher priority portsare served first, while ports withinthe same priority class are servedin a weighted round-robin manner.

In the case of the TX PHY, for eachof the signaling generators, abandwidth equivalent to theexpected traffic rate is specified.The parameter is Tcell, similar tothe traffic generation at thetransmitter.

ATM Layer Emulation

Test case TX ATM

The system emulates the ATM layer and sends traffic to aMultiPHY device (IUT). Therefore,the TX POD (HP E4885A) isconnected to the IUT as shown infigure 6.

Step 1:For each individual port, adedicated cell sequence is set up.The sequence may contain anykind of cells. A cell is built in aflexible manner from singlememory-based and real-timegenerated data segments (see [2]and [3]). The physical port numberis linked to each cell sequence.

Step 2:One of the four traffic generatorsmust be linked to a trafficsequence. The traffic generatorshapes the cell streams and passesthe cells over to the POD ports(cell buffers). Traffic generator #1has the highest priority, whereastraffic generator #4, the lowest.

Step 3:The POD carries out polling asdefined by the traffic profileresulting from all the trafficgenerators together. Depending onthe polling result, the POD willtransfer the appropriate cell to theUTOPIA interface. If more thanone port signals acceptance of acell, the port with the lowestaddress will be served first.

If an IUT port does not acceptcells, the cells coming from thetraffic generator may overflow thePOD port buffer (which has adepth of three cells). In this case,the cell from the traffic generatorwill be discarded until the IUTaccepts further cells and frees upthe POD port buffer. Thediscarding of cells is ongoing,which is indicated by the system’smonitor screen.

Figure 6: ATM layer emulation: system is TX ATM, TX POD (HP E4885A) is connected

Figure 7: ATM layer emulation: system is RX ATM, RX POD (HP E4886A) is connected


Test case RX ATM

The HP E4829B emulates the ATMlayer and receives data from aMultiPHY device (IUT). The RX POD (HP E4886A) is connec-ted to the IUT as shown in figure 7.

Step 1:The POD handles the polling(address generation) in ascendingorder for all activated ports. Whenseveral ports signal cellavailability, selection of a certainport takes place according to theassigned priority. The higherpriority ports are served first,while ports within the samepriority class are served in aweighted round-robin manner.

Step 2:Available cells are received fromthe IUT and are marked with portinformation. The POD transfersthe cells immediately to themodule, where cells are analyzedand processed in the same way aswith Level 1 implementation (see [3]). The trigger masks areenhanced and allow thespecification of a physical portnumber, together with the celldata itself.

Step 3:Typically, the system acts as anideal ATM layer which neverdelays any cells from transferring.Therefore, a bandwidth of 100 % isalways provided. The absolutebandwidth is defined only by thereceiver clock.

PHY Device Emulation

Test case RX PHY

The system emulates a MultiPHYdevice and sends traffic to an ATMlayer device. The TX POD (HP E4885A) is connected to theIUT as shown in figure 8.

Step 1:For each individual port, adedicated cell sequence is set up.The sequence may contain anykind of cells. The physical portnumber is linked to each cellsequence.

Step 2:One of the four traffic generatorsmust be linked to a trafficsequence. The traffic generatorshapes the cell streams and passesthe cells over to the POD ports(cell buffers). Traffic generator #1has the highest priority, whereastraffic generator #4, the lowest.

Step 3:A POD port can buffer three cells.The POD monitors the addressbus, and signals available cells(RXClav) according to theparameters Tcell and Tpause whencells are in buffer. If more thanone port signals acceptance of acell, the one with the lowestaddress will be served first.

Cells transferred by the trafficgenerator without request fromthe IUT (ATM layer) are discarded.The discarding of cells is indicatedby the system’s monitor screen.

Test case TX PHY

The HP E4829B emulates theMultiPHY device and receives datafrom an ATM layer device (IUT).The RX POD (HP E4886A) isconnected to the IUT as shown infigure 9.

Step 1:To activate a port, the TX POD isassigned to one of the foursignaling generators. For eachgenerator, an individual bandwidthrepresenting expected traffic canbe specified. The bandwidthspecification defines the maximumtraffic which the test system canserve for the corresponding port.

Step 2:The POD monitors the addressbus. With the TXClav asserted, thePOD signals cell transfer into itsbuffer. After a cell transfer to acertain port is completed, theTXClav for this port will not beasserted again until the actual datarate is lower than the specifiedbandwidth. The system acts as anideal PHY device which neverdiscards any cells from transfer.

Figure 8: PHY device emulation: system is RX PHY, TX POD (HP E4885A) is connected


Step 3:The POD immediately transfersthe cells, including the portinformation, to the module, wherecells are analyzed and processedin the same way as with UTOPIALevel 1 implementation.

The trigger masks are enhancedand allow the specification of aphysical port number, togetherwith the cell data itself.

Software

Configuration

The system software adaptsautomatically according to thePODs connected. Figure 10 showsthe configuration screen forconfiguring a UTOPIA Level 2operation after a system boot.

Either 8 or 16 bit wide operation isavailable for the module. The TXand RX PODs can be individuallyassigned for either ATM or PHYemulation. Both can be selectedindividually for single Clav(chapter 4.2) or direct status(chapter 4.3) modes.

Traffic generation

Traffic generators are capable ofhandling more than one sequenceof cells. A sequence of cells can beassigned for each port. Figure 11shows the screen for trafficediting.

Figure 9: PHY device emulation: system is TX PHY, RX POD (HP E4886A) is connected

Figure 10: Configuration screen

Figure 11: Traffic generation setup with port and sequence control


Clav signaling

Figure 12 shows the screen for asetup with the Clav signaling for aTX PHY. There are four individualsignaling generators, and abandwidth in terms of expectedcell rate can be specified for eachone by the parameter Tcell.

A port becomes active byassigning it to one of the foursignaling generators.

Monitor screen

The system’s monitor screen isshown in figure 13. It providesgraphical feedback on the status oftransmitter ports. Any non-activeport is marked gray. As long as anactive port is able to transmit cells,it is shown in green; as soon ascells have to be discarded, it isshown in red. There are twoindications: one is called “Current”,which gives an indication of thecurrent status, and the other iscalled “Overall”, which retains thestatus from the last click on the“Reset” button.

Figure 12: Signaling generator port and expected traffic control

Figure 13: Monitor screen


Main window

The main window, shown in figure 14, is enhanced for:

• sequence edit: “Sequence”,• port edit: “Port”,• monitor: “Port”,• connect status:

“Disconnect/Connect”.

The monitor screen in figure 13can be viewed by clicking on the“Port” button. The possiblemultiple sequences are editedfrom the “Sequence” button, andthe port configuration for thereceiver, including the signalinggenerators, is set up from the“Port” button in the receiver setup.

“Connect/Disconnect” are newkeys which handle the connectionstatus. In “Disconnect” mode, allsystem outputs are in a highimpedance state. In “Connect”mode, all outputs are driven andthe clock is applied to the device-under-test. The system will startcell generation and analysis afterclicking on the “Run” button.

Figure 14: Main window


Interfacing

HP E4885A/E4886A

Figure 15 shows the TX/RX POD(interchangeable), together with a120 mm 80 pin cable assembly andan adapter for reducing the signaldensity to 40 pin. The 80 pin cablebelongs to the POD, whereas theadapter shown is part of theoptional interface kit for Level 2(HP E4821A option #502).

There are several ways ofconnecting a POD to the IUT:

• connect the POD via the 80 pintest cable and connectors on thetest board,

• connect the POD via the 80 pintest cable (PC-edge).

Used in conjunction with theinterface kit, the followingmethods of connection are alsopossible:

• connect the POD via the 80 pincable and the 80 to 40 pinadapter.

• connect the POD with theflexible lead cable by using the80 to 2 x 50 pin adapter.

• connect the POD with 50 pinribbon cables by using the 80 to2 x 50 pin adapter.

Figure 15: POD with an 80 pin connector, 120 mm ribbon cable and 40 pin adapter


POD connector

The POD connector pin layout isshown in figure 16 and is definedin table 2.

Pin # Signal Pin # Signal1 AUX0 3 AUX15 AUX2 7 AUX39 AUX4 11 AUX513 AUX6 15 AUX717 D0 19 D121 D2 23 D325 D4 27 D529 D6 31 D733 D8 35 D937 D10 39 D1141 D12 43 D1345 D14 47 D1549 PRTY 51 SOC53 LENB 55 A057 A1 59 A261 A3 63 A465 CLAV0 67 CLAV169 CLAV2 71 CLAV373 CLKIO 75 EXTREF77 TRG_IN 79 TRG_OUTall even GND

Table 2: Signals on an 80 pin connector

Note: all even pins carry Gnd.

Using connectors on the IUT

test board

The 80 way cable plugs into theconnectors provided on the testboard. The following list includesconnector part numbers andmanufacturers for parts which canbe used on a test board.

• 80 pin vertical plug e.g. AMP-2-557102-1.

• 80 pin right angled plug e.g. AMP-2-557100-1, MOLEX 71661-2080.

• 80 pin vertical plug for SMT e.g. MOLEX 71661-5080.

PC-edge connection

This method allows a connectionto the test board by a methodsimilar to that of PC-edgeconnectors. It can therefore beperformed without additionalconnectors, as long as the PCboard layout is prepared, as shownin figure 15. The PC boardthickness is 1.6 mm.

The layout requirements areoutlined in figure 17.

Figure 16: Signals at an 80 pin POD connector (HP E4885A/E4886A interchangeable)

Figure 17: Layout details for a PC-edge connection with an 80 pin cable

Connection via 80 way cable

and 80 to 40 pin adapter

Table 3 shows the signalassignment at the 40 pin adapter.The adapter is provided in bothvertical and right angled versions.

Pin # Signal Pin # Signal1 GND 21 GND2 AUX0 22 AUX13 AUX2 23 AUX34 D0 24 D15 D2 25 D36 D4 26 D57 D6 27 D78 D8 28 D99 D10 29 D1110 D12 30 D1311 D14 31 D1512 PRTY 32 SOC13 LENB 33 A014 A1 34 A215 A3 35 A416 CLAV0 36 CLAV117 CLAV2 37 CLAV318 CLKIO 38 EXTREF19 TRG_IN 39 TRG_OUT20 GND 40 GND

Table 3: Signal assignment of 80 to 40 pin adapters

The 40 pin adapter is a signalconcentrator. It supports thesmallest footprint on the testboard by compromising thenumber of grounding pins.Therefore, it is recommended thatyou place the connector on thetest board as close as possible(less than 2 inches) to the IUT.

The following list includesconnector part numbers andmanufacturers for parts which canbe used on a test board whenusing the 40 pin adapter.

• 40 pin vertical plug e.g. AMP-557102-5.

• 40 pin right angled plug e.g. AMP-557100-5, MOLEX 71661-2040.

• 40 pin vertical plug for SMT e.g. MOLEX 71661-5040.

Flexible probes

The flexible lead cables availablewith the UTOPIA Level 1 interfacekit are also usable for Level 2interfacing. The Level 2 interfacekit provides four flexible cables,together with two 80 to 2 x 50 wayadapters for connection to both ofthe Level 2 PODs.

Ribbon cables

As well as the flexible cables, 50 pin ribbon cables are alsoprovided. These can be used bystandard 50 pin (IDC) headers inthe 0.1 inch spacing included inthe test board layout.

Electric characteristics

All POD signals, both in and out,are driven from FCT technology.

DC parameters for TTL levels are:Ioh/Iol = 24 mA,Iih/Iil = 1 µA.

AC impedance is typically a totalof 50 pf when used with a 120 mmribbon cable.

ESD protection is provided perMIL-STD-833.

Signal transition time is typically1.5 ns. It is therefore highlyrecommended that you applytransmission line techniques to atest board layout in order toguarantee proper signaldistribution over the customdesign. Transmission linetechniques keep the number oferrors, which can cause significantovershoot and ringing due to fastedge rates, to a minimum. This

also avoids coupling and noisebetween adjacent signals andother lines.



Signals View

Single Clav polling

(according to UTOPIA Level 2,chapter 4.2).

The figures on this page show thetransmission of one cell from theATM layer to the PHY layer. In thisexample, the test system’stransmitter emulates the TX ATM,and the test system’s receiveremulates the TX PHY. Threeactivated ports are shown in thisexample: 03, 07 and 0C.

Figure 18 shows the start oftransmission. In the polling phase,all ports (03, 07 and 0C) signaltheir ability to receive a cell. Port 03 is then selected andtransmission to this port begins(data = 0301, which indicates thefirst word of the cell transfer toport 03).

In figure 19, the cell transfer ispaused at word #15. It is possibleto set this up from the graphicaluser interface, where the start andlength of the pause can becontrolled. It can be seen thatpolling continues and that ports 07and 0C still signal their ability toreceive a cell.

In figure 20, the end of the celltransfer is shown. You might askwhy the last word (0327) staysthere longer; this is due to the highimpedance of the bus. The data isonly valid for the cycle after 0326;additional cycles are only requiredfor discharging.

By controlling the bandwidth ofthe port emulated by the testsystem, port 03 signals that it isunable to take another cell at thismoment. Ports 07 and 0C are stillable to receive a cell, and so port 07 will be the next to beselected.

In case the HP E4829B (ATMlayer) has to pause the datatransmission because no data isavailable, polling is continued. Ona first come first served basis, theHP E4829B will start cell transfer.

References

[1] ATM Forum, “UTOPIA, anATM-PHY Interface Specification,Level 2”, Version 1.0, 7/96.

[2] Parallel cell/traffic generatorand analyzer HP E4829B, productoverview, p/n 5964-1667E.

[3] Parallel cell/traffic generatorand analyzer HP E4829B, technicalspecifications, p/n 5963-9923E.

Figure 18: Polling, selection and start of transmission of a cell

Figure 19: Transmission paused

Figure 20: End of cell transmission


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Data subject to change

Copyright © 1997

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Documents

Implementation of UTOPIA Level 2 for Parallel Cell / Tr a ...literature.cdn.keysight.com/litweb/pdf/5965-4856E.pdfImplementation of UTOPIA Level 2 for Parallel Cell / Traffic Generator