IMST Workshop2008 1 - University of Exeter Blogsblogs.exeter.ac.uk/imst/files/2009/12/Jan-Van-Houdt.pdf · Ig = dQfg/dt = Ctot dVfg/dt = Cg dVT/dt Coupling ratio = Cg/Ctot = fraction

$Page 1: IMST Workshop2008 1 - University of Exeter Blogsblogs.exeter.ac.uk/imst/files/2009/12/Jan-Van-Houdt.pdf · Ig = dQfg/dt = Ctot dVfg/dt = Cg dVT/dt Coupling ratio = Cg/Ctot = fraction$
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc

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MTC 2008 : Flash memoryIMEC© 2008

Jan Van HoudtPage 1

Flash memory

Jan Van HoudtMemory Group Manager

© imec 2008

Outline

• Introduction: volatile versus nonvolatile • Basic physical mechanisms for Flash• Comparison of current memory types• Challenges for further Flash scaling • Emerging concepts

– Evolutionary approaches

– Revolutionary approaches: alternative NVM

• Conclusions


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Jan Van HoudtPage 2

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Introduction : the memory market

Source: Gartner Dataquest, 2007Semiconductor Forecast Worldwide--Forecast Database [SEQS-WW-DB-DATA]

Memory23%

Micro19%

Analog6%

Discrete6%

ASIC9%

Logic5%

ASSP23%

Non-opto sensors

1%Opto8%

TOTAL IC MARKET2006 Revenues $259.7 billion

10.7% Growth

DRAM57%

SRAM3%

NOR12%

NAND21%

EEPROM4%

PSRAM3%

MEMORY IC MARKET2006 Revenues $60.3 billion

Market Percentage by Device

• Flash share increased rapidly in the last few years

• From 11% in 1998 to 33% in 2006

All of these memories are charge-based!

© imec 2008

Samsung42%

Toshiba28%

Hynix17%

Micron6%

Intel3%

ST2%

Qimonda0%

Renesas2%

Introduction: the Flash market

2002 Flash market shareTotal $7.8 Billion

2007 Flash market shareTotal $21.8 Billion

Spansion30%

Intel26%

ST15%

Samsung7%

SST4%

other18%

NAND13.9

NOR7.9

Numonyx


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Jan Van HoudtPage 3

© imec 2008

Introduction: NVM forecast

• Introduction• Floating gate versus charge trap• Alternative/emerging Nonvolatile Memory• Conclusions

Source: Alan Niebel (Webfeet Research), 2007 ICMTD

© imec 2008

Introduction

• Moore’s law is coming to an end for logic (ultimate CMOS)– not much cost reduction from scaling (unless for some high-end products)

– power issue prohibits scaling

– performance limited by software and memory access rather than by processor clock frequency

• However, the hunger for higher memory density is insatiable– 640Kbyte is not enough for everyone…;-)

– after cell phone,PDA,MP3,digicam,USB memory new markets are SSD and videoQUESTION: I read in a newspaper that in 1981 you said, ``640K of memory should be enough for anybody.'' What did you mean when you said this? ANSWER B. Gates: I've said some stupid things and some wrong things, but not that. No one involved in computers would ever say that a certain amount of memory is enough for all time.The need for memory increases as computers get more potent and software gets more powerful. In fact, every couple of years the amount of memory address space needed to run whatever software is mainstream at the time just about doubles. This is well-known.


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Jan Van HoudtPage 4

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Introduction: why Flash is driving Si scaling

Ever larger demand for memory capacity (grows faster than required computing power)Especially in the area of nonvolatile, demand is huge (mobile apps, battery issue): -> “Hwang’s law” (NAND density x2/year)

Price elasticity: the lower the price, the more Flash takes over part of the mass storage market -> growth (8GB = 25$)Extensive error-correction and redundancytechniques drive further integration w/o major yield issues (NVM can be “corrected” unlike logic)

© imec 2008

Introduction: the killer applications…

• In 2000 cellular phones boosted NOR Flash to become a 10B$ market

NORNAND

“The NAND market, the fastest-growing semiconductor market in history, has enormous price elasticity: as prices drop more new applications adopt the technology. This allows NAND to displace existing forms of media, fosteringaccelerated growth.” (Semico Research)

• In 2005 multimedia applications caused a second boom, now in NAND Flash (20B$ market)


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Jan Van HoudtPage 5

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Introduction: the killer applications…

• SSD (solid state drive) : the new killer application ?

32, 64, 128 GB modules256GB announced

© imec 2008

EE Times June 2nd 2008

• …Intel Corp. and MicronTechnology Inc. have claimed the technical lead in the NAND Flash memory market with the launch of the first sub-40nm NAND flash device. Reportedly moving ahead of Toshiba, Samsung Electronics and others in the process race, the Intel-Micron duo has rolled out 34nm, 32Gbit multi-level cell (MLC) NAND flash. Previously, the leading-edge NAND device from Intel and Micron was a 50nm part. This process technology was jointly developed by IM Flash Technologies LLC, Intel and Micron's joint NAND venture. A single 32Gbit chip could store more than 2,000 digital photos or hold up to 1,000 songs on an MP3 player, according to the companies. The 32Gbit NAND chip is said to bethe only monolithic device at this density that fits into a standard 48-lead TSOP, said Brian Shirley, VP of Micron's Memory Group. "These advancements will expand the value proposition and accelerate the adoption of solid-state drive (SSD) solutions in computing platforms," said Pete Hazen, director of marketing of Intel's NAND products group, in a statement. The device will enable more cost-effective SSDs, doubling the current storage volume of these devices and driving capacities to beyond 256Gbyte in today's standard, smaller 1.8-inch form factor. Two 8-die stacked packages would realize 64Gbyte of storage. This is enough for recording anywhere from 8 to 40 hours of high-definition video in a digital camcorder, according to Micron and Intel…


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Jan Van HoudtPage 6

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Introduction: definitions

• A memory is a device that can hold information with or without the need for an external voltage supply

• This functionality typically requires at least 2 structural elements and/or mechanisms:– A storage element/mechanism (capacitor, floating gate, programmable

resistor…)

– A means for reading this storage element (mostly an access transistor for addressing purposes) <-> cross point array!!

– Therefore, cell structures are often referred to as 2T2C, 1T1R, 6T4C etc…

– Since a transistor (w/o contacts) takes 4F2, A 1T1X cell typically takes 6-8F2

with F = feature size

• Only a few memory cells are truly 1T (Flash, FeFET,…)

© imec 2008

Introduction: definition of volatile memory

• A volatile memory is a memory that can only hold its information in the presence of an external voltage supply

• Main benefits/requirements: – Fast random access for read/write/erase

– Unlimited cyclability (high throughput memory)

• 2 major classes:– Static RAM (6T): low power, fast but… large cell (few Mbits)

– Dynamic RAM (1T1C): very dense but…refresh needed (now at 1Gb)


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Jan Van HoudtPage 7

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• SRAM cell (6T) is large but fast (internal amp)

PG1 PG2

PUP1 PUP2

PDN2PDN1

Vdd

gnd

WL WL

BLBBLA

0.31um2 in 45 nm150F2

© imec 2008


• DRAM cell (1T1C) is small but leaky • signal ~ charge ~ C ~ area -> trench or crown

required

Transfer gate

WL

BL

Storage node

Field plateSource : Samsung

Source : Infineon

Transistor

MIM crown capacitor

Transistor

Trench capacitorTypical size : 8F2


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Jan Van HoudtPage 8

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Introduction: definition of NVM

• A nonvolatile memory is a memory that can hold its information without the need for an external voltage supply

• Examples– hard disk

– magnetic tape

– CD/DVD

– Mask ROM

– static RAM with battery (!)

– Electrically Erasable Programmable ROM

– Nonvolatile RAM

• Increasing demand for NVMs in portable/mobile applications (battery!)

• ‘Nonvolatile’ means at least 10 years of data retention. This requires “thorough” programming mechanisms that usually create some kind of damage (limited endurance)

• Usually, write speed is slow(er) and fast random access is only available for reading (NOR)

© imec 2008

Introduction: the SoC memory hierarchy

CPU

Stand-alone DRAM

Em-bedded

NVM

Higher-level

cache

SRAM

SRAMSRAM

Stand-alone Flash

on-chip off-chip

• Many different memories with different sizes & requirements


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Jan Van HoudtPage 9

© imec 2008

Outline

– Introduction

• Basic physical mechanisms for Flash– Comparison of memory types

– Challenges for further Flash scaling

– Emerging concepts

• Evolutionary approaches• Revolutionary approaches: alternative NVM

– Conclusions

© imec 2008

Basic physical mechanisms

• Fowler-Nordheim tunneling• Channel hot-electron injection• Reliability characteristics


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Jan Van HoudtPage 10

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Mechanisms: the Floating Gate (FG) concept

• Floating Gate (FG) devices:– originally introduced by Kahng and Sze in ‘67 for EPROM

– threshold voltage is shifted by injecting electrons through a dielectric onto or ejecting electrons off a floating (polysilicon) gate

– If electrons are put on the gate, the transistor gets a high VT (threshold voltage) and is therefore offwhen selected

– If electrons are removed from the gate, the transistor gets a low VT and the transistor is therefore onwhen selected

• possible injection/ejection mechanisms:– tunneling

– channel hot electron injection

Ig = dQfg/dt = Ctot dVfg/dt = Cg dVT/dtCoupling ratio = Cg/Ctot = fraction of voltage coupled to FG

ΔVT = Qfg/Cg : charge can scale with dimensions

• mainstream nonvolatile memory technology of today (due to high CMOS compatibility and high quality of silicon dioxide)

• High scalability is due to small cell size and information storage based on charge density (C/cm2)

S D

18V

Cg

© imec 2008

Mechanisms: Fowler-Nordheim

• Quantummechanical tunneling through a triangular energy barrier

Silicon

Oxide Poly

S D

18V

S D

-12V

5V

uniform

non-uniform


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© imec 2008


• Low programming speed even at high voltage

10-6

10-5

10-4

10-3

10-2

10-1

100

Programming time (s)

0

1

2

3

4

5

6

7

Thr

esho

ld v

olta

ge (

V)

VCG

= 14VV

CG = 16V

VCG

= 18VV

CG = 20V

transient programming characteristic

© imec 2008


• Fowler-Nordheim tunneling: properties• large oxide fields (>10MV/cm) required• high voltages needed• defect-related breakdown is main issue -> error correction• appearance of Stress-Induced Leakage Currents (SILC)

• used for both programming and erasing (±ΔVt)• very low power (<<1nA/cell) -> massive parallellism possible!• influence of trapping on Vt/channel current

S D

18V


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© imec 2008

Mechanisms: Channel Hot Electron injection

• Channel electrons undergo impact ionization at the drain at high lateral fields

• This impact ionization creates an electron-hole pair. If the electron has sufficient energy and the vertical field is in the upward direction, this electron can be injected over the gate oxide into the floating gate

• Efficiency = gate current/drain current ~ 1E-6• Industry standard for NOR Flash

(ETOX or Eprom with Thin Oxide)

Silicon

Oxide

Poly

3.2eV

S D

9V

4.5V

© imec 2008


• High programming speed at high drain current

10-6

10-5

10-4

10-3

10-2

10-1

100

Programming time (s)

0

1

2

3

4

5

Thr

esho

ld v

olta

ge (

V)

VD

= 2VV

D= 2.5V

VD

= 3VV

D= 3.5V

VD

= 4V


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© imec 2008


• properties– only for positive shift (+ΔVt)

– high power consumption (~200µA/cell), junction optimization is key

– moderate voltages (Vpp)

– Vfg > Vd: electron trapping decreases programmability

• oxide field < 5MV/cm -> trapping saturates as pre-existing traps are filled

– Vfg < Vd: increased lateral field and reverse oxide field induce hole + electron injection

• leads to hole trapping, interface state generation and mobility reduction (read current!)

© imec 2008

Mechanisms: source-side injection

• Source Side (hot-electron) Injection (SSI)

• Examples: HIMOS™, SST’s Superflash™

Silicon

Oxide

Poly

=high injection efficiency

+?

high Vgdlow V

high collection efficiency

low Vghigh Vd

high generation rate

high Vfglow Vg

5V

S

S

D

D

high lateral field and favorable vertical field


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© imec 2008


– Special case of hot carrier injection : injection occurs at the source side of the floating gate

– Typical structures : split gate transistor or sidewall cell

– Lateral and vertical field components are decoupled: efficiency is optimized (1E-4)

VdVcg Vfg

© imec 2008


• Source-side injection: properties– only for positive shift (+ΔVt)

– moderate-to-low power consumption (~10µA/cell)

– lower voltages/no overerase issue (embedded!)

– injection inside the transistor channel!

• influence on programmability and on Vt, mobility

– subthreshold slope decreases -> leakage currents in programmed state

– relies on surface impact ionization -> excellent high T behaviour


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© imec 2008


PG

D

CG

SFG

4

3

2

1

0

-1

-2

V t [V

]

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100

Programming time [s]

25°C 75°C 125°C 175°C

Vpg = 9V, Vd = 3.3V, Vcg = 0.9V

mainly for embedded application (e.g. Automotive micro’s, ON Semiconductor)

© imec 2008

Comparison different mechanisms

• “Available” gate current characteristics– shape determines program/erase properties (speed,

power, voltages, reliability)

floating-gate voltage

CHEI

SSI

t = 0t = Tp

FN

gate current

• SSI > CHEI > PPT> FNT in terms of speed

• speed can be traded for lower voltage


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© imec 2008

Endurance: definition

• the ability to perform according to the specifications without degradation when subjected to repeated write/erase (W/E) cycling

• cell level: – threshold voltage as a function of W/E cycles

– read-out current degradation

• circuit level:– failure rate as function of W/E cycles

V

write/erase cycles

T

high VT

low VT

read-out voltage

programming margin

erase margin

cell window

© imec 2008

Endurance: cell vs. circuit

• Tunneling cells are limited by breakdown and SILC rather than by trapping: 1M cycles feasible on cell-level

• Gradual degradation of imperfect oxide:– redundancy and ECC (at expense of array efficiency)

– reduction of peak lateral field (EEPROMs)

-3

-2

-1

0

1

2

3

V t [V

]

106105104103102101100

#P/E cycles

double poly Flotox


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© imec 2008

Retention: definition

• the ability to retain valid data over prolonged period of time under storage conditions (=nonvolatility)

• Cell level: – ability to retain charges in the absence of applied external bias

(= intrinsic retention)

• Circuit level:– retention of the worst cell in the array before and after cycling

(defect-related -> extrinsic retention)

• Typically characterized by closure of the Vt-window versus storage time at high temperature or electric field

© imec 2008

Retention: Arrhenius diagram

• tΔVt ~ exp(EA/kT) with EA the activation energy of the charge loss mechanism

102

103

104

105

t 500

mV

[h]

3.02.52.01.5

1/T [ x10-3/K]

T = 70ºC

t = 16 years

EA= 0.54eV

• intrinsic retention due to e- tunneling and thermionic emission is virtually unlimited (tunnel oxide > 7nm)

• retention is limited by defects eventually activated by stress


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© imec 2008

Disturb effects

• Disturb immunity refers to – the ability to retain valid data over a prolonged period of time under

operating conditions

• Cell level: – resistance to soft-write effects during read-out of a cell (special case

of read disturb)

• Circuit level:– influence of program/erase/read voltage(s) on unselected cells

– program-, erase-, and read disturb

– strongly depending on array organization (Flash <-> EEPROM)

© imec 2008

Disturb effects

• Example: some bits showing anomalous charge loss in cells with thin oxide after disturb tests: extrinsic SILC or “moving bits” (worse after cycling)

Tox = 6 nm

Moving bits

Main distribution


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© imec 2008

Overerase

• Overerase refers to – the situation where the low (erased) threshold voltage is too low in

order to further provide a reliable cell and/or array operation

• Circuit level:– cell behaves as depletion device causing leakage currents during

reading

Only NOR issue (see later)

© imec 2008

Overerase: leakage currents

• Due to the lack of a select device, overerasedcell causes leakage current in NOR array during read-out -> information on that bitline is lost

I=0

I≠00

Low Vt distribution has to be carefully controlled during P/E cycling (verify cycles, soft program after erase)


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© imec 2008

Outline

– Introduction

– Basic physical mechanisms for Flash

• Comparison of memory types– Challenges for further Flash scaling



– Conclusions

© imec 2008

Comparison of memory types

• Functionality pyramid of semiconductor NVMs

EEPROM

Flash EEPROM

EPROM

PROM/OTP (One-Time Programmable ROM)

(mask) ROM

Device complexity and cost

• electrically programmable • electrically byte-erasable

• electrically programmable • electrically block-erasable

• electrically programmable • UV chip-erasable

• one-time user programmable • not erasable

• one-time programmable • not erasable

floating gate

based


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© imec 2008


• EPROM: small cell– CHEI for programming (fast, high power)

– UV light for erasing (slow)

– no electrical erase -> only for code

– quartz window needed in package -> expensive

S D

12V

5V

thick gate oxide

© imec 2008


• EEPROM: large cell area (select device required)– FNT for program/erase (low power)

– high cost technology, difficult to scale down

– still used for low density applications (trimming, calibration, smart cards)

A

A'

Floating gate

Control gate

n+n+

Control gate

Floating gate

A - A'

“Flotox” device

WL

BL

Vselect

Vpp= 15V


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© imec 2008


• Flash memory = best of 2 worlds(economical compromise between EPROM and EEPROM): – small cell and no select device (cfr. EPROM, low bit cost but not byte-erasable)

– FNT for electrical (block) erase (cfr. EEPROM, no quartz window, in-circuit erase)

– initially only for (EP)ROM replacement, later on also for data storage (NOR)

– NAND Flash came later using FN tunneling for both programming and erasing

S D

18V

S D

9V

4.5V

NOR NAND

© imec 2008

Flash comes in 2 flavors: NOR and NAND

• NOR: programmed by Channel Hot Electron injection: ‘lower’ voltages (10F2)

• NAND: programmed by Fowler-Nordheimtunneling: high voltages (4F2)

S D

18V Silicon

Oxide Poly

Silicon

Oxide

Poly

S D

9V

4.5V


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© imec 2008

Flash: NOR versus NAND

• NOR: ½ drain (BL) contact/cell: fast access -> code• NAND: contactless: slow access -> data

WL1

BL

Vpp=8V

4.5V

WL20

WL

BL

Vselect

Vpp= 18V

0

0

© imec 2008


• NOR– fast random access, fast programming, robust -> code

– larger cell size ~10F2

Source

Bit line

Word line

Source

Bit line

Word line

basic layout y-pitch cross-sectionx

y

x-pitch cross-sectionarray equivalent circuit

Source

Bit line

Word line

Source

Bit line

Word line


y

x

y



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© imec 2008

NOR in detail

Floating gateControl gateBuried source

Bitline contact

Tunnel oxide

Interpoly(coupling)dielectric(ONO)

© imec 2008


• NAND: true cross point array– slow access (but fast burst read), low program power -> data

– smallest cell size : ~4F2

Source

Bit line

W .L.

Bit line sel.

B it line sel.Source

Bit line

W .L.

Bit line sel.

B it line sel.


y

x-pitch cross-sectionarray equivalent circuitSource

Bit line

W .L.

Bit line sel.

B it line sel.Source

Bit line

W .L.

Bit line sel.

B it line sel.


y

x

y


F

FF/2

F/2

F/2 F/2


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© imec 2008

NAND in detail

7 nm tunnel oxide

Poly floatinggate

15 nm ONO interpolydielectric (IPD)

Equal line width and space: bothat minimum CD

Minimum pitch STI : AR=~5

Control gatewrapped around floatinggate to maximizecoupling

© imec 2008


• Comparison EPROM - EEPROM - Flashmemory EPROM EEPROM NOR Flash NAND Flash

write speed

10µs 1ms 10µs 100 µs

erase speed

15’ 10ms 100ms-1s 1ms

power high low high low cell area small large small very small

cost high high medium low cycles ~ 10 105 104-105 104-105

voltages 12 15 8/-8 18


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© imec 2008

Flash applications: NOR and NAND

• NOR (Spansion, Numonyx), now @1-2Gb in 65nm technology node– Fast cell programming (10µs)

– Fast random read access (50-100ns)

– High programming power (200µA/bit)

– Used for code storage (robust): cellular!

• NAND (Samsung, Toshiba/SanDisk, Hynix, Micron/Intel), now @ 16-32Gb in 56/43nm technology node– Slow programming (but fast page mode : massive parallellism)

– Fast burst (serial) read, slow random read access -> needs cache

– Low programming power

– Used for data (file) storage applications

– Blockbuster(s): MP3, digicam, PDA, USB drives, cards, SSD

© imec 2008

Multilevel memory

Programming to 3 different Vt levels allows to store 2 bits/cell (2n levels = n bits): margins divided by 3!This multilevel capability of floating gate memory allowed for a unique step in bit size scaling (2F2 for NAND/5F2 for NOR)The principle is hard to extend to 4 bits (16 levels!) because of reliability constraints and analogue capabilities of the Flash process but 3 bits/cell is in development

00 (erased level Vt0)01 (Vt1)10 (Vt2)11 (Vt3)

0

1

#bits

Vt


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© imec 2008

Outline

– Introduction


– Comparison of current memory types

• Challenges for further Flash scaling – Emerging concepts


– Conclusions

© imec 2008

Challenge #1: interpoly dielectric (IPD)

• When scaling proceeds, there is no more room to wrap the control gate around the FG

• Planarization substantially lowers coupling area (sidewalls are lost)

• Solution: high-k interpoly dielectric layer

wrapped WL =>

WL

sti sti

High-k IPD layer

tunnel

planar WL

sti

WL

sti

issues: retention, programming saturation and Vpp


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© imec 2008

Self-aligned FG cell -> high-k IPD

HiK + TiN + poly deposition

Stacked etch

IPD

STI

CG

TD

After 193nm litho

STI

FG

Tunnel OxIPD

CG

© imec 2008

Challenge #2: tunnel oxide and voltage scaling

Percolation theory allows failure rate prediction due to anomalous charge loss or ‘moving bits’(Degraeve et al., IEDM 2001)

tox

x1

x2

x3

Anode interface

Cathode interface

Percolation ifx1 and x2 and x3 < xperc

10-12

10-10

10-8

10-6

10-4

10-2

100

fract

ion

failu

res

12111098765oxide thickness (nm)

I = 10-22AEox = 2.5 MV/cm

area = 10-9 cm2

xperc = 3.5 nm

Dot = 3 x 1016cm-3

1016

3 x 1015

1015

3 x 1014

1 trap2 traps

3 traps


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© imec 2008

Challenge #2: tunnel oxide and voltage scaling

• No tunnel oxide scaling -> no more voltage scaling!• Esp. NAND will have major breakdown issue at <30nm nodes

(20V/30nm = 6.6MV/cm)• Solutions: engineered barriers and high-k interpoly dielectric

(IPD) layer

WL

sti sti

High-k IPD layer

tunnel

© imec 2008

High-k requirements

Retention is primary requirement, hence high quality high-k material (low shallow-trap density)EOT ~ 4.5nm OK for interpoly layer (currently 13nm ONO) K-values of 15-20 are sufficient for couplinggood interface with FG and with (top) gate materialmetal gate helps to reduce interaction with high-kLong-term: physical thickness should be reduced as well… WL1 WL2

spacing

tphy


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© imec 2008

Challenge #3: number of electrons on FG

• At 20nm, less than 100 electrons are present on the FG for Vt=1

• If 20% charge loss is the spec, we talk about ~10 electrons…• Solutions: novel device architectures

© imec 2008

Roadblock #4: electrostatics

• Electrostatic interference between floating gates– Technological solution: charge trapping in a dielectric layer

WL

sti sti


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© imec 2008

Challenge #4: electrostatics

• Electrostatic interference between floating gates– Design solution: intelligent programming algorithms taking content of

surrounding cells into account

0+ 11

11

K. Prall, 2007 NVSMW

• Decrease in coupling ratio when adjacent WL’s start to influence FG potential

–Decrease vertical dimensions (thin FG, thin IPD)

–Low-k fill between cells

–New FG architectures

© imec 2008

Challenge #5: litho

• 32 nm generation requires dense 64 nm pitch patterning

• Solution: double patterning techniques or 3D

==

MASK A MASK B

== ++

litho-defined

spacer-defined


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© imec 2008

Additional roadblocks for NOR

• channel length can not be scaled below ~ 0.2µm because of high (4V) drain voltage for channel hot-electron (CHE) programming (punch-through)

• engineered barrier doesn’t work for CHE programming (carrier scattering reduces mobility and hence impact ionization in case of non-SiO2 gate dielectric)

• this explains (together with the half BL contact) why NOR size ~10F2 and going up with scaling

• consequently, as W is scaled, read current (~W/L) goes down• final generation = 45nm???

-> NOR Flash market is a target for a new memory technology!

S D

9V

4.5V

© imec 2008

Outline

– Introduction




• Emerging concepts• Evolutionary approaches• Revolutionary approaches: alternative NVM

– Conclusions


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© imec 2008

Evolution or revolution?

• The major difference with logic is that memory is a commodity market with very low (if not negative) margins

• This leads to (even) larger conservatism• A new memory technology should therefore be

– very cheap = very dense (<2F2/bit): requires multibit/cell and/or 3D structure

– low programming power (for high throughput)

– nonvolatile (battery)

– able to step in at actual densities (32Gb NAND announced for 2008)

© imec 2008

What designers want…

• A unified or universal or ultimate memory having:– Nonvolatility (>10 years)

– Low voltage operation (<1.2V)

– Low power operation (battery)

– High density (<4F2)

– Fast random Write/Erase/Read access (few ns)

– High endurance (1E15 cycles)

– Low cost (CMOS compatible)

– Mature

– Scalable over many generations

– … anything else??

• Main problem: – it should be able to compete with established concepts (Flash/DRAM) -which

are unlikely to give up momentum- and enter the market at the same density level!

=> The holy grail…


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© imec 2008

The memory landscape

• we still use the DRAM as introduced in ‘71 and the Floating Gate as in Kahng and Sze’s EPROM in ’67… all Q-based

volatile

SRAMfast, large, embedded

DRAMdense, stand-alone, refresh

ZRAM?

nonvolatile

Flash(FG, CT)

65nm, 1-2Gb

5x nm, 16Gb

E(E)PROM

PCM

90nm, 512Mb demo

MRAM/FRAM

niche apps

RRAM

-binary & complex oxides

-organics

-PMC

CD/DVD

Long term-domain wall switching

-molecular

-probe storage

-holographic

-ionics

-nanotube/wire‘old’ new

© imec 2008

Emerging concepts: 2 approaches

• Switching to evolutionary concepts (short learning curve –short time-to-market): no ambition to replace DRAM– charge trapping layers

– nanocrystals

– 3D

• Switching to revolutionary concepts (new concept/materials)– Magnetic RAM (MRAM)

– Phase Change Memory (PCM)

– Resistive switching (R-RAM)

– Exploratory concepts


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© imec 2008

Outline

– Introduction





– Conclusions

© imec 2008

Emerging concepts: charge trapping memory

– Electrons or holes are transported through the oxide and stored in traps inside the nitride

– Removes the electrostatic interference problem in ultra-small floating gate cells

– Main problem was retention when using direct tunneling (thin bottom oxide)

Si

SiO

2

SiO

2

Si3 N

4

Poly-S

i

S O N O S


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© imec 2008

Charge trapping memory : NROM™

• The return of nitride memory…

• e.g. NROM™ (SaifunTechnologies, now Spansion)

Oxide-Nitride-OxideStack

Bit 1

Bit 2

Bit 1 Bit 2

Programming

ProgrammingRead

Read

WSi - Poly Gate

Bit Line Oxide

Bit Line n+

p Substrate

+* Storing electrons in a nitride layer i.s.o. a floating gate removes the moving bits problem (no tail bits)* Using hot carrier programming allows the bottom oxide to be thicker (~5nm) than in the former SONOS technology and allows 2-bit storage

-* Channel hot-electron injection requires 9.5V at gate and ~150µA/bit* Complicated drain engineering* Both bits can interfere -> new retention problem that limits channel length scaling* Soft-write (after cycling) due to screening and small window

© imec 2008

Charge trapping memory: the SONOS issue

• SONOS was first nonvolatile memory in the 70s• Main issue was the compromise between retention and

window– in order to make program/erase (P/E) current different from leakage current

through top oxide, direct tunneling is needed as P/E mechanism

– giving in on retention and on erase margin gives marginal technology solution (which does not allow for multilevel programming)

SiO2SiN

SiO2

polySiSONOS

gate SiO2

SiNSiO2

Si

-> high-k top dielectric allows to alter electric field in top layer as compared to tunnel layer, hence increase tunnel thickness

FN

DT


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© imec 2008

Charge trapping memory: the TANOS solution

• Main issues: retention and erase performance• Main material requirements:

– p-type metal gate needed for deep erase (needed for multilevel)

– deep hole and electron traps in trapping layer (retention)

– high-k top layer with ‘high’ conduction band offset (wrt nitride) and low shallow-trap density (ev. completed with thin SiO2 sealing layer^)

Al2O3SiN

SiO2

Metal gateT*ANOS

gateAlO SiN

SiO2

Si

* = Ta(C)N(O)^ L. Breuil et al., NVSMW/ICMTD 2008

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Pro’s and con’s of TANOS

• Pro’s+ smallest possible storage node = material defect!

+ planar technology => lower cost

+ no more tail bits (localized traps)

+ smaller cell-to-cell interference (2007 ICMTD & NVSMW)

+ minor changes to design libraries and in-system functionality

• Con’s- need to work on retention and disturbs (thinner tunnel)

- high-k top dielectric + metal gate required

- need to open up the window for multilevel (erase speed)

- does not provide any voltage scaling

at present the only viable alternative for floating gate NAND Flash


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© imec 2008

Emerging concepts: nanocrystal memory

• Main advantages: single poly, defect immunity, low power programming, 2-bit storage capability

• Main disadvantages: narrow trap density window which compromises cell scaling and causes trap-up in top oxide, small read signal, process control

• Note: presented at IEDM 95 by IBM for DRAM replacement but discontinued, later renewed interest from Freescale for embedded Flash replacement

poly

polyONO

conventional cell

SiO2

nanocrystal cell

poly

SiO2

After J. De Blauwe IEDM 2001

© imec 2008

3D

• Stack multiple layers on-chip (Samsung, IEDM 2006)

Source : Samsung IEDM’06

1st layer of silicon

2nd layer of silicon

Common source line

Stacked contact for bitline


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© imec 2008

3D

• True vertical Flash technology (Toshiba, VLSI 2007)

litho/cost limitations -> 3D

but… 3D doesn’t follow Moore’s law…

(doubling # layers is limited, cfr. MLC)

© imec 2008

Outline

– Introduction

– Basic physical mechanisms




– Conclusions


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© imec 2008

Emerging concepts: 2 approaches

• Switching to evolutionary concepts (short learning curve – short time-to-market): no ambition to replace DRAM– charge trapping layers

– nanocrystals

– 3D

• Switching to revolutionary concepts (new concept/materials)– Magnetic RAM (MRAM)

– Phase Change Memory (PCM)

– Resistive switching (R-RAM)

– Exploratory concepts

© imec 2008

Emerging concepts: Magnetic RAM

• Based on electron spin dependent resistivity of a Magnetic Tunnel Junction (MTJ) in a magnetic field

Isolation Transistor

“ OFF”

FixedMagnetic LayerDigit Line

Bit Line

Isolation Transistor “ ON”

Free Magnetic Layer, InformationStorage.

{Tunneling Barrier{

{

Sense Current

Read Mode

Program Current He

Program CurrentHh

Program Mode

After Saied Tehrani, NVSMW 2001


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© imec 2008

Emerging concepts: MRAM

• Advantages : – fast low voltage switching (<1V)

– non-destructive read

– very high read/write endurance

– operation-wise it is a unified memory but…

• Disadvantages:– high write power (current driven -> large peripheral devices)

– easier switching when driving current through the MTJ -> new disturbs !

– small MR (read) signal: resistance ratio << 2

– uniformity and reliability of MTJ (AlO/MgO)

– multilayer stack of very thin layers of new materials such as Ni, Fe, Co, Mn

• Applications: – radhard (space)

– niche market (low density, 4Mb in 0.18µm)

© imec 2008

Emerging concepts: Phase Change Memory

• Based on the melting and (re-)crystallization of a Chalcogenide material such as Ge2Sb2Te5– Known from the 70s and widely used for CDRW and DVD

– Switching between crystalline and amorphous state using a heat pulse

– Crystalline : low resistivity (moderate heating >300C)

– Amorphous : high resistivity (melting >600C and rapid cooling)


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Emerging concepts: Phase Change Memory

• Advantages : – High endurance (>1E12)

– Non-destructive read

– Large window (i.c.w. MRAM)

– Writes almost as fast as DRAM (~50ns) at low voltage

– reasonable maturity obtained (512Mb circuits in 90nm)

• Disadvantages:– Material stability (bit failures with cycling)

– Large programming power (but current scales with cell dimensions)

– Endurance/power too high for DRAM replacement

• Applications: – NOR Flash replacement beyond 45nm

– EEPROM/SRAM replacement in embedded memory

© imec 2008

Emerging concepts: Resistance RAM

• Based on materials having a bi-stable resistance state (high/low-R) that can be switched electrically by V or I– MTJ-MRAM also bi-stable R but switched MAGNETICALLY

– PCM also bi-stable R but requires PHASE CHANGE

• Materials : – binary and complex oxides (OxRRAM)

– chalcogenides (Conductive Bridging RAM or Programmable Metallization Cell)

– organic materials I

V

I

V

Low-R

High-RI

V

I

V

I

V

I

V

Low-R

High-R


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© imec 2008

Emerging concepts: Resistance RAM

• Advantages : – random access memory

– low cost (back-end), low voltage concept (embedded!)

– can be realized with ‘standard’ metals (NiOx, CuOx, WOx)

• Disadvantages:– no maturity (~64kb demo’s)

– 6-8F2/cell w/o multilevel capability (binary mechanism)

– scalability of the programming mechanism remains questionable

– reliability not proven

• Applications: – NAND replacement if 3D-integratable

– embedded memory

© imec 2008

Outline

– Introduction

– Basic physical mechanisms





• Conclusions


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© imec 2008

NVM Roadmap

NAND-Flash (FG)

Technology node F [nm]

Cell size[F2]

10

20

30

40

180 130 90 65 5x 3x

NOR-Flash (FG/NROM)

MRAM

FeRAM

PCM OxRRAM ?

2x

TANOS

4x 1x

niche and niche and embedded embedded applicationsapplications

codecode datadata

notes: PCM may be applied in embedded applications as well (65nmnotes: PCM may be applied in embedded applications as well (65nm) )

evolutionaryevolutionary

disruptivedisruptive

status (production)status (production)

Spintronics

16Gb 32Gb

© imec 2008

Conclusions

• The demand for (nonvolatile) memory is likely to further increase very fast in the next decade (esp. data storage applications)

• Mainstream memories are based on electrical charge stored on a floating gate :– By tunneling : NAND for data storage

– By CHEI : NOR for code storage

• Scaling of these memories can go on using the known concepts at least until the 2x nm generation


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© imec 2008

Conclusions

• Trapping based concepts may offer viable (cost-effective and scalable) alternatives for NAND

• A “zoo” of new concepts are emerging for NOR/NAND replacement– FeRAM and MRAM: niche applications

– PCM for NOR replacement (and later on embedded memory)

– RRAM for NAND replacement ?

© imec 2008

Documents

IMST Workshop2008 1 - University of Exeter Blogsblogs.exeter.ac.uk/imst/files/2009/12/Jan-Van-Houdt.pdf · Ig = dQfg/dt = Ctot dVfg/dt = Cg dVT/dt Coupling ratio = Cg/Ctot = fraction