IncisiveUniSim Ds

7/27/2019 IncisiveUniSim Ds

1/4

DATASHEET

INCISIVE UNIFIED SIMULATOR

The Incisive Unified Simulator is the core of the Cadence Incisive functional

verification platform. Its also the first simulator to natively support Verilog,

SystemVerilog, VHDL, SystemC, SystemC Verification Library, PSL, SVA, and OVL.

With dynamic assertion checking, full transaction-level support, HDL analysis,

unified test generation, and optional Acceleration-on-Demand, the Incisive platform

delivers the fastest, most efficient verification for nanometer-scale ICs.

INCISIVE FUNCTIONAL

VERIFICATION PLATFORM

The functional verification of

nanometer-scale ICs requires speed

and efficiency. Yet today's fragmented

methodologies make it impossible to

optimize either. Each verification

stage has its own methodology, tools,

models, and user interface. Engineers

must re-create almost everything at

every stage. The Incisive verfication

platform is the world's first functional

verification platform that supports a

unified methodology to deliver the

fastest, most efficient verification in

the industry.

Figure 1: The Incisive Unified Simulator is the core of the Incisive platform

Analog/Mixed-signal

Acceleration/Emulation

Acceleration-on-Demand

Unified testgeneration

Transactionsupport

Assertions

Comprehensivecoverage

Debug/analysis

Simulation

Third-partyEDA support

Algorithmdevelopment

IP

NC-VHDLSimulator

NC-VerilogSimulator

NC-SCSimulator

Incisive

Unified

Simulator

IncisiveXLD

Incisive Palladium systems

Incisive AMS

CoWare SPW

Incisive verification IP

HDL analysis


2/4

INCISIVE UNIFIED SIMULATOR

The Incisive Unified Simulator provides

everything you need to verify todays

toughest designs. Its single-kernel

architecture natively supports Verilog,

SystemVerilog, VHDL, SystemC,

SystemC Verification (SCV) Library, PSL,

SVA, and OVL. The Incisive platform

includes a comprehensive verificationenvironment including dynamic

assertion checking, full transaction-level

support, and unified test generation.

You can extend the functionality of

the Incisive simulator with other

elements from the Incisive platform,

including Acceleration-on-Demand,

analog/mixed-signal/RF verification,

and algorithm development and

verification.

BENEFITS

Offers the ultimate simulation-based

speed and efficiency

Increases RTL performance by 100 times

with native transaction-level simulation

and optional Acceleration-on-Demand

Reduces testbench development up

to 50% with transaction-level support,

unified test generation, and

verification component re-use

Shortens verification time, finds

bugs faster, and eliminates exhaustive

simulation runs with dynamic

assertion checking

Decreases debug time up to 25%

through unified transaction/signal

viewing, HDL analysis capability,

and unified debug environment for

all languages

FEATURES

HETEROGENEOUS SINGLE-KERNEL

ARCHITECTURE

The Incisive single-kernel architecture

enables unified simulation throughbehavioral, transaction, register-

transfer, and gate-levels of abstraction.

It utilizes a unique interleaved native-

compiled architecture that supports

Verilog, SystemVerilog, VHDL, SystemC,

SCV Library, PSL, SVA, and OVL.

Design and testbench models can

be interleaved in any language and

any level of abstraction without the

performance and integration overhead

caused by co-simulation. The Incisive

Unified Simulator produces efficient

machine code for high-speed

execution. Linked-list scheduling of the

resulting data structures pre-processes

signal actions while maximizing

effectiveness of modern caching

algorithms available in the leading

compute platforms.

UNIFIED SIMULATION AND

DEBUG ENVIRONMENT

A unified simulation and debug

environment allows the Incisive

Unified Simulator to manage multiple

simulation runs easily and analyze your

design and testbench at any point in

the verification process regardless

of the composition. Throughout

the design and verification flow, the

Incisive simulator provides hardware

analysis checks, source browsing,

transaction/waveform viewing, and

code/transaction/assertion coverage

analysis. Application programming

interfaces based on industry standards

are available at all levels to enable

user-defined checks and analysis. All

engineers on a project learn one

and only one environment.

INTEGRATED TRANSACTION

ENVIRONMENT

The Incisive Unified Simulator includes

an integrated transaction environment

that supports transaction specification,

simulation, recording, aggregation,

analysis, and debug. Raising the level

of abstraction from the signal level

(enable, r/w, address, and data) to the

transaction level (data events such as

read and write) speeds verification.

Transaction-level models and testbenches

Analog HDL

Mixed-level

Interleaved native-compiled architecture

Multilanguage Mixed-signal

Verilog

SystemVerilogVHDL SystemC

C, C++PSL, SVA, OVL

Figure 2: Incisive single-kernel native-compiled architecture

Figure 3: Incisive simulation integrates transaction/waveform debugging and simulation

analysis software


3/4


4/4

Code reusability

Clock domain synchronization

FSM coding

Acceleration policy checks

Gate-level netlist analysis for any DFT

errors introduced during synthesis

Verilog, SystemVerilog, VHDL, andmixed-language support

Powerful customization capability

using VPI/VHPI

Graphical interface to sort, filter, and

analyze messages with source code

RESULT ANALYSIS

Debug and GUI

Waveform window

Register window

Unified transaction/signal viewing

Schematic tracer

Expression calculator

Signal flow browser

Source viewer

Error browser

Tcl/Tk scripting for

customizable displays

Log signal and transaction data

to SST database

Performance analysis software outlines

areas of code where most simulation

time is spent

Code coverage

Supports Verilog, SystemVerilog,

VHDL, and mixed-language designs

Automatic finite state machine

extraction

Coverage attributes supported

include blocks, paths, expressions,

variables, gates, FSM (states,

sequences), and toggle

Coverage re-use

Rank order coverage contributions

Bit-wise expression scoring Functional coverage analysis

Supports Verilog, System Verilog,

VHDL, SystemC, SCV, PSL, SVA, and

OVL

Logs data to SST2 database

Tcl/Tk scripting for custom analysis

THIRD-PARTY SUPPORT

ASIC libraries

More than 30 ASIC vendors have

certified their libraries for the

Incisive platform

More than 150 unique libraries

Models

Third-party model support

through the Cadence verification

IP partner program Software

Third-party software support

through the Cadence Connections

program with more than 30

verification company partners

INTERFACES

PLI (IEEE 1364)

VPI (PLI 2.0, IEEE 1364)

OMI (IEEE 1499)

VHPI Compiled SDF

PLATFORMS

Sun Solaris

HP-UX

Linux

INCISIVE PLATFORM

PRODUCT LINE-UP

INCISIVE UNIFIED SIMULATOR Unified simulator with heterogeneous

single-kernel architecture

Native Verilog, SystemVerilog, VHDL,

and SystemC support

Native SystemC Verification Library

PSL, SVA, and OVL support

Fast, unified test generation

Acceleration policy checks and

HDL analysis

Unified simulation and debug

environment Unified kernel supports analog/

mixed-signal and algorithm design

INCISIVE XLD TEAM VERIFICATION

Provides 10 Incisive Unified

Simulator licenses

Adds 1M gates Acceleration-on-Demand

Enables local or remote access

Increases capacity with Cadence

EDA card

Supports simulation acceleration

and in-circuit emulation

INCISIVE PALLADIUM FAMILY OF

ACCELERATORS/EMULATORS

Simulation acceleration and in-circuit

emulation in one system

Provides up to 100x-10,000x RTLperformance

Run-time performance with up to

750KHz speed

Compiles up to 30M gates per hour on

a single workstation

Expandable to 256M gates

Allows up to 32 simultaneous users

Leader in microprocessor and IP support

CADENCE SERVICES

AND SUPPORT Customer-focused solutions that

increase ROI, reduce risk, and achieve

your design goals faster

Collaborative approach and design

infrastructure virtual teaming

Proven methodology and flow tuned

to your design environment

Design and EDA implementation

expertise

Product and flow training to fit your

needs and preferred learning style

More than 80 instructor-led

courses certified instructors, real-

world experience

More than 25 Internet Learning

Series (iLS) online courses

Cadence customer support that keeps

your design team productive

Cadence applications engineers

provide technical assistance

SourceLink online support gives you

access to software updates, technical

documentation, and more 24hours a day, 7 days a week

FOR MORE INFORMATION

Email us at [email protected] or visit

www.cadence.com.

2005 Cadence Design Systems, Inc. All rights reserved.Cadence, the Cadence logo, Connections, NC-Verilog,SourceLink, and Verilog are registered trademarks, andIncisive is a trademark of Cadence Design Systems, Inc. OSCIand SystemC are registered trademarks of Open SystemCInitiative, Inc. in the United States and other countries andare used with permission. All others are propertiesof their respective holders.

5418C 04/05

Documents

IncisiveUniSim Ds